JPH0154723B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device, and particularly to a key input circuit for an electronic desktop calculator (hereinafter referred to as a calculator).

Calculators generally use a plurality of keys as a means of inputting information. In recent years, as calculators have become significantly more personalized, their shapes have become smaller and smaller, and key devices used as information input means have also become smaller. Therefore, when pressing a certain key, it often happens that adjacent keys are pressed together by mistake. In addition, as calculators have become smaller, their selling prices have become significantly cheaper, and input key devices have shifted from expensive reed relays to inexpensive mechanical switches, conductive rubber, and the like. If the key input device is made smaller and cheaper, the structure will be simplified, which naturally increases the occurrence of chattering due to the parts used. In general, calculator malfunctions caused by key input devices include cases where a key is pressed twice or more than once, as described above, and cases where a key is judged to have been pressed multiple times due to chattering. There is. Therefore, conventional calculators use key input devices that have complicated circuit configurations with a large number of gates and are equipped with a double-key press prevention device or a chattering prevention device.

The purpose of the present invention is to effectively utilize the circuits that are originally included in calculators, without using additional devices such as double-pressing prevention devices and chattering prevention devices, which were conventionally considered indispensable. An object of the present invention is to provide a key input determination device that can prevent malfunctions of a calculator caused by malfunctions of a calculator.

According to the present invention, in order to be able to make a judgment regarding a key input using the circuit that a calculator is originally equipped with, that is, the memory circuit and the arithmetic circuit, the first
0 is added to the signal obtained by the second key scan, the result is stored in the storage section, and the signal obtained by the next second key scan is compared with the stored signal in the calculation section. , if a match is detected, the key input is determined to be valid.

Therefore, the inputted key signal is inputted to the storage circuit through the arithmetic circuit, and the next inputted key signal is similarly inputted to the arithmetic circuit. Therefore, key determination is possible without having many extra additional circuits.

Next, embodiments of the present invention will be described with reference to the drawings. First, the basic configuration of a general calculator is shown in the block diagram of FIG. In the figure, an addressing flip-flop 9 specifies the address of a read-only memory (hereinafter simply referred to as ROM) 1,
The stored ROM code is output from ROM1. When a portion of the ROM code is introduced into the instruction dataer 4, the instruction decoder 4 translates it into various types of instructions and energizes the corresponding instruction output lines. Shift pulses (hereinafter referred to as bit signals) are applied to the shift register group 2, and stored data is held cyclically by shifting sequentially for each shift pulse. The adder/subtractor 3 is controlled by the output of the instruction decoder, and has the function of sequentially adding and subtracting two input data strings. 10 is a judgment circuit which receives the input of the adder/subtractor 3, judges this and determines the next instruction address.
Command to ROM1. The timing counter 8 is a circuit that generates a digit timing signal sequence that is sequentially generated at a constant period in a time-division manner and a bit signal sequence that is sequentially generated at a quarter period of the digit timing signal. After being shaped by the digit drive circuit 6, the digit timing signal sequence is applied to the grid of the display tube as a dynamic display signal and to the key input device as a key scanning signal. Furthermore, both the digit timing signal and the bit signal serve as basic signals for arithmetic processing. The phase relationship between the digit timing signal and the bit signal is shown in FIG.
Display data is applied to the display tube plate via a segment drive circuit 7 which operates to adapt the binary coded decimal numbers to the display glyphs. Clock oscillator 5
is used as a signal source for supplying clock pulses to each of the components. There is another key input circuit, but it is not shown in the figure because it will be described in the explanation of the present invention.

In Figure 1, there are generally multiple shift register groups 2, and all shift registers are used for the first time in the process of arithmetic processing, but all shift registers are used in the process of display and key reading. I usually don't. Therefore, actively utilizing the surplus shift register during the key reading process helps achieve the objectives of the present invention.

An embodiment of the present invention will be described with reference to FIG.
Reference numeral 21 denotes a shift register consisting of a one-word bit storage element, which shifts one bit at a time in response to a bit signal applied from the input side. An output is obtained from one end of the shift register 21 and introduced into the first input terminals of an AND gate 26 and an AND gate 28, respectively. 22 is an instruction decoder and ROM
command signal lines 22-1, 22-, respectively, depending on the output of
2 and 22-3 to output a high level signal. The output line 22-1 is connected to the first input terminal of the AND gate 27, and is also connected to the first input terminal of the AND gate 26 via the inverter 32. This output line 22-1 selects the output of the shift register 21 and the output of the adder/subtractor 23,
One of them is introduced into the input of the shift register 21 via the OR gate 24. Output line 22-2 is connected to first input terminals of AND gates 29 and 30, respectively. Output line 22-
2 is activated, the key input signal is applied to the third input terminal of AND gates 29 and 30, and the second
"1" is introduced into the second input terminal of the adder/subtractor 3 in synchronization with the bit signals t ₁ and t ₂ input to the input terminals. The output line 22-3 is connected to the second input terminal of the AND gate 28, and when the output line 22-3 is activated, the output of the shift register 21 is connected to the adder/subtractor 2.
Introduced in 3. Digit timing signals T ₁ , T ₂ , T ₃ ,
..., _T9 is added to the key matrix circuit 31 of the key input means. Key matrix circuit 31
The output signals of are introduced from commonly connected output lines to AND gates 30 and 29 via key output terminals K1 and K2. The instruments constituting this matrix are composed of switch circuits as shown in FIG. 3a. The output of the adder/subtractor 23 is also input to the address slip-flop 33,
Specifies the ROM address of the next word.

FIG. 4 is a flowchart showing the key reading process of instructions stored in the ROM. First, as shown in FIG. 4, when a key wait command is output, the output line 22-2 of the command decoder 22 is activated. Output line 22-1 is energized and is therefore a logic "1" while the output of inverter 32 is a logic "0". Output line 22-3 is not energized, so AND gate 28 is blocked. Now, when the key K51 is pressed, the digit timing signal _T5 is input to the AND gate 30 via the output terminal K1. The AND gate 30 energizes the output line at timings T ₅ and t ₁ and introduces the key input signal to the second input terminal of the adder/subtractor 23 via the OR gate 25 . Since the output line 22-3 of the AND gate 28 on the other input side of the adder/subtractor 23 is in the cutoff state, that is, the logic "0", the adder/subtracter 23 adds the logic "0" to the key input signal and outputs " Output 1”,
Eventually, through the AND gate 27 and the OR gate 24, the shift register 2
Logic "1" is written only at the timing positions of T ₅ and t ₁ of 1.

If there is no key input, the command in FIG. 41 is repeated, but since there is a key input, the next word will cause the command to be executed as shown in FIG. 42.
The subtraction instruction for register output and key input signal is in ROM
It is output from Then, the output lines 22-2 and 22-3 of the instruction decoder 22 are activated. At this time, the output line 22-1 is cut off. shift register 21
The output of is sent to the adder/subtractor 23 via the AND gate
is applied to the first input terminal of. Further, data is circulated via an AND gate 26 and an OR gate 24. At this point, if the same key K51 as in the case of the previous word command _{in FIG} . A timing signal is input to the second input terminal of the adder/subtractor 23. Here, the adder/subtractor 23 performs subtraction between the first input and the second input, but since both inputs have the same content, a numerical value "0" is output as the result of the subtraction. The resulting logic "0" is input to the address flip-flop 33 to designate the ROM address, and a key read operation for the next word instruction is executed as shown in FIG. 4. The result of the above calculation is the numerical value “0”
If not, it indicates that the keys pressed between the first command and the second command word are different. If chattering occurs, the pressed key input signal will not be generated, so the first command and the second
The key input signals between the instruction words are different, and a logic "1" is input to the address flip-flop 33 indicating a state in which the operation result is not "0". Therefore, the key reading operation is not carried out and the process returns to the command shown in FIG. 4, waiting for a key signal. Since the key input signal is stored at a location corresponding to the digit timing signal of the shift register 21, key identification can be easily performed.

Next, when key K52 is pressed, the output of AND gate 29 energizes the output line in synchronization with bit signal _t2 . Therefore, a key input signal is written into the second bit of the digit corresponding to the digit timing signal _T5 of the shift register 21, as shown in FIG. 5b. The difference between the signals from the K1 terminal and the K2 terminal is determined by the difference in the bit position of each digit of the shift register. For example, in the case of a so-called double press in which keys K51 and K52 are pressed at the same time, key input signals are input to bits 1 and 2 of the shift register position corresponding to digit timing signal _T5 . As shown in Figure 5d, double pressing of a key can be easily recognized. Even if keys K41 and K51 are pressed twice, the key input signal is introduced into the first bit position of the shift register 21 corresponding to the digit timing signals _T4 and _T5 , so it can be easily pressed as shown in Fig. 5c. I can judge. It goes without saying that multiple key presses of triple presses or more can also be determined in a similar manner.

In the explanation of the above embodiment, a shift register was used as the storage circuit, but the present invention may also be implemented using a storage device, such as a random access memory, which can send stored data to the adder/subtractor in synchronization with each digit timing signal. It can be configured. Further, although the period of one-quarter of the digit timing pulse is defined as one bit signal period, the period of the bit signal is not limited to the above-mentioned value. For example, it may be 1/2, 1/3, 1/5, etc., and the number of keys can be increased by dividing the digit timing signal into multiple parts. Furthermore, it is not necessary that all of the digit timing signals applied to the key input device be applied to the grid of the display tube, and the number of T ₁ , T _{2 .} . . , T ₉ shown in the embodiment may be arbitrary.

Further, in the description of the above embodiment, the logic of the key input signal was explained using positive logic, but the same effect can be obtained even if the key input signal is supplied to the addition/subtraction circuit or the shift register in a form with the polarity inverted.

As explained above, according to the present invention, by simply adding a few new gate circuits to the conventional arithmetic processing circuit that constitutes a calculator, it is possible to greatly prevent malfunctions caused by chattering and double pressing of keys. Effects can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the basic configuration of an electronic desktop calculator, Fig. 2 is a timing chart showing the phase relationship between the digit timing signal and bit signal used in the calculation of Fig. 1, and Fig. 3 is a timing chart showing the present invention. A block diagram showing one embodiment, FIG. 4 is a flowchart showing the operating procedure of the embodiment of FIG. 3, and FIG. 5 is an explanation showing the state of key input signal data of the shift register in the embodiment of FIG. 3. It is a diagram. Explanation of symbols: 21: Shift register, 22: Instruction decoder, 23: Adder/subtractor, 24, 25: OR gate, 26 to 30: AND gate, 31: Key matrix circuit, 32: Inverter, 33:
Flip-flop for address.

Claims (1)

[Claims] 1. In a key input determination device provided in an electronic device having storage means for storing calculation data and calculation means for processing the data stored in the storage means, key input data is input to one of the calculation means. means for supplying the output of the storage means to the other input terminal of the calculation means via a first gate circuit; and means for supplying the output of the calculation means to the other input terminal of the calculation means via a second gate circuit. means for supplying the data to the storage means, and when the key input data detected in the first key scanning period is applied to the calculation means, the first gate circuit is closed and the output of the first gate circuit is is set to zero, the calculation means performs addition or subtraction between the key input data and zero, and the result is stored in the storage means via the second gate circuit, and the first key scanning period During a subsequent second key scanning period, data applied from a key input device to the one input terminal of the calculation means and the key input data stored in the storage means are used to open the first gate circuit. When the result of subtraction by the calculation means is zero, the key input data stored in the storage means is determined to be valid, and when the result is other than zero, the key input data is determined to be invalid. A key input determination device characterized in that it is possible to determine a key input by using the storage means and the calculation means provided in an electronic device.