JPS6233456A - Schottky barrier diode - Google Patents

Schottky barrier diode

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Publication number
JPS6233456A
JPS6233456A JP17275685A JP17275685A JPS6233456A JP S6233456 A JPS6233456 A JP S6233456A JP 17275685 A JP17275685 A JP 17275685A JP 17275685 A JP17275685 A JP 17275685A JP S6233456 A JPS6233456 A JP S6233456A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
epitaxial layer
type
schottky barrier
barrier diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17275685A
Other languages
Japanese (ja)
Inventor
Takeshi Omukae
大迎 毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP17275685A priority Critical patent/JPS6233456A/en
Publication of JPS6233456A publication Critical patent/JPS6233456A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the forward voltage of a Schottky barrier diode, by providing with one conductive type of a separating region with a higher impurity concentration reaching from the epitaxial layer surface to the semiconductor substrate surface around the epitaxial layer, and the one conductive type of a buried layer formed at a section in the separating region on the semiconductor substrate. CONSTITUTION:An N<+> type buried region 3 is formed at least on a section in the separating region 6 by diffusing selectively antimony on a semiconductor substrate 2. Accordingly, since the current path flowing into the semiconductor substrate 2 from the barrier metal electrode 7 can be shortened, the resistance at this section can be reduced. On the other hand, an N<+> type separating region 6 is formed so as to reach from the epitaxial layer 4 surface to the N<+> type semiconductor substrate 2 surface around the N-type epitaxial layer 4. Since the N<+> type separating region with a higher concentration than the N-type epitaxial layer 4 may be formed and thus a portion of current may be flowed into the N<+> type separating region 6, increase of the boundary area between the semiconductor substrate 2 and the epitaxial layer 4 of the Schottky barrier diode and thus decrease of the resistance can be attained.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はショットキーバリア・ダイオードの順方向電圧
(V? )の特性改善に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to improving the forward voltage (V?) characteristics of a Schottky barrier diode.

(ロ)従来の技術 従来のショットキーバリア・ダイオード121)は特開
昭55−43893号公報(第4図)に示す如く、N”
ffiのシリコン半導体基板いと、該N”Wのシリコン
半導体基板@上に積層されるN型のエピタキシャル層■
と、該N型のエピタキシャル層04)上に熱酸化法等を
用いて積層されるシリコン酸化膜(ハ)と、該シリコン
酸化膜(ハ)を写真蝕刻法で開孔されたコンタクト孔と
、ここでコンタクト孔はシリコン半導体基板@の略中夫
に形成される、前記コンタクト孔を介して積層されるバ
リアメタル電極(3)と、ここでバリアメタル電極(資
)はMo%NiおよびAIを積層して形成される、前記
バリアメタル電極(3)の略中夫にワイヤボンド法を用
いて形成されるA(1ワイヤ等とにより構成されている
(B) Conventional technology A conventional Schottky barrier diode 121) has an N''
ffi silicon semiconductor substrate and an N-type epitaxial layer laminated on the N''W silicon semiconductor substrate@
, a silicon oxide film (c) laminated on the N-type epitaxial layer 04) using a thermal oxidation method or the like, and a contact hole formed in the silicon oxide film (c) by photolithography. Here, the contact hole is formed approximately in the middle of the silicon semiconductor substrate@, and the barrier metal electrode (3) is laminated through the contact hole. It is composed of A (1 wire, etc.) formed by a wire bonding method approximately at the center of the barrier metal electrode (3) which is formed by stacking.

(ハ)発明が解決しようとする問題点 一般にショットキーバリア・ダイオードはスイッチング
時間が短く、高速スイッチング動作に適することが知ら
れており、またショットキーバリア・ダイオードの順方
向の障壁の高さはスイッチング速度に反比例するため、
より低い順方向の障壁の高さを有するショットキーバリ
ア・ダイオードが望ましい。従って順方向電圧V、の小
さいショットキーバリア・ダイオードが望ましく、本発
明が問題とするところはこのショットキーバリア・ダイ
オードの順方向電圧V、を小さくすることにある。
(c) Problems to be solved by the invention It is generally known that Schottky barrier diodes have short switching times and are suitable for high-speed switching operations, and the height of the forward barrier of Schottky barrier diodes is Since it is inversely proportional to the switching speed,
Schottky barrier diodes with lower forward barrier heights are desirable. Therefore, a Schottky barrier diode with a small forward voltage V is desirable, and the problem of the present invention is to reduce the forward voltage V of this Schottky barrier diode.

に)問題点を解決するための手段 本発明は高不純物濃度の一導電をの半導体基板(2)と
該半導体基板(2)上に形成された一導電型のエピタキ
シャル層(4)と該エピタキシャル層(4)に接触する
バリアメタル電極(力と該バリアメタル電極(7〕が前
記エピタキシャル層(4)と接触しない領域に形成した
絶縁膜(5)とを具備するショットキーバリア・ダイオ
ード(1)に於いて、前記エピタキシャル層(4)の周
縁に前記エピタキシャル層(4)表面より前記半導体基
板(2)表面まで達する高不純物濃度の一導電型の分離
領域(6)と、前記半導体基板(2)上の分離領域(6
)内の少なくとも一部に形成される一導電型の埋め込み
領域(3)とにより構成することで解決するものである
B) Means for Solving Problems The present invention provides a semiconductor substrate (2) of one conductivity type with high impurity concentration, an epitaxial layer (4) of one conductivity type formed on the semiconductor substrate (2), and the epitaxial layer (4) of one conductivity type formed on the semiconductor substrate (2). A Schottky barrier diode (1) comprising a barrier metal electrode (4) in contact with the layer (4) and an insulating film (5) formed in a region where the barrier metal electrode (7) does not contact the epitaxial layer (4). ), an isolation region (6) of one conductivity type with a high impurity concentration reaching from the surface of the epitaxial layer (4) to the surface of the semiconductor substrate (2) is provided at the periphery of the epitaxial layer (4); 2) Upper separation area (6
) and a buried region (3) of one conductivity type formed in at least a part of the region (3).

(ホ)作用 一般にシッットキーバリア譬ダイオードの順方向電圧■
、を決める要因としてショットキーバリア・ダイオード
の直列抵抗R1がある。
(E) Function Generally speaking, the forward voltage of a Schittky barrier diode is
, is the series resistance R1 of the Schottky barrier diode.

従来の構成に於いては一導電型のエピタキシャル層(財
)の濃度と厚さによって略決まっていたが、前記エピタ
キシャル層(4)の周縁に前記エピタキシャル層(4)
表面より前記半導体基板(2)表面まで達する一導電型
の分離領域(6)を形成することで、前記高不純物濃度
の一導電型の分離領域(6)に一部電流が流れ込むため
、ショットキーバリア・ダイオードの順方向電圧V、を
小さくすることができる。
In the conventional structure, the concentration and thickness of the epitaxial layer (material) of one conductivity type were approximately determined, but the epitaxial layer (4) was formed on the periphery of the epitaxial layer (4).
By forming an isolation region (6) of one conductivity type reaching from the surface to the surface of the semiconductor substrate (2), a portion of current flows into the isolation region (6) of one conductivity type with high impurity concentration, so that Schottky The forward voltage V of the barrier diode can be reduced.

一方前記埋め込み領域(3)を設けることで前記半導体
基板(2)へ流れ込む電流経路を短かくすることができ
るため前述と同様に頭方向電圧V、を小さくすることが
できる。
On the other hand, by providing the buried region (3), the current path flowing into the semiconductor substrate (2) can be shortened, so that the head direction voltage V can be reduced as described above.

(へ)実施例 以下に本発明による一実施例を第1図を参照しながら説
明する。
(F) Embodiment An embodiment of the present invention will be described below with reference to FIG.

第1図に示す如く、N+型のシリコン半導体基板(2)
と、該半導体基板(2)上に選択的に更にアンチモンを
拡散して形成されるN+型の埋め込み層(3)と、ここ
で前記N+型の埋め込み層(3)は前記半導体基板(2
)上の分離領域(乙)内の少なくとも一部に形成される
、前記N+型のシリコン半導体基板(2)上に積層され
るN型のエピタキシャル層(4)と、該N型のエピタキ
シャル層(4)上に熱酸化法等を用いて積層されるシリ
コン酸化膜(5)と、該シリコン酸化膜(5)の周縁を
写真蝕刻法等で開孔した拡散孔に拡散法を用いて前記エ
ピタキシャル層f4J表面より前記半導体基板(2)表
面まで達するように形成されるN+型の分離領域(6)
と、前記エピタキシャル層(4)に接触するパリアメク
ル電極(力と、ここで該バリアメタル1電極(7)はシ
リコン酸化膜(5)を選択的に除去してコンタクト孔を
設けMo、 Ni、 AIの順にスパッタリング法等に
より形成される、前記バリアメタル電極(7)が前記エ
ピタキシャル層(4)または分離領域(6)と接触しな
い領域に形成した絶縁膜(5)とにより構成される。
As shown in Figure 1, an N+ type silicon semiconductor substrate (2)
and an N+ type buried layer (3) formed by selectively further diffusing antimony on the semiconductor substrate (2), where the N+ type buried layer (3) is formed on the semiconductor substrate (2).
), an N-type epitaxial layer (4) stacked on the N+ type silicon semiconductor substrate (2) and formed in at least a part of the isolation region (B) on the N-type epitaxial layer ( 4) A silicon oxide film (5) is laminated on the silicon oxide film (5) using a thermal oxidation method or the like, and the epitaxial layer is formed using a diffusion method into a diffusion hole formed at the periphery of the silicon oxide film (5) by a photolithography method or the like. an N+ type isolation region (6) formed to reach the surface of the semiconductor substrate (2) from the surface of layer f4J;
The barrier metal 1 electrode (7) in contact with the epitaxial layer (4) is formed by selectively removing the silicon oxide film (5) and providing a contact hole with Mo, Ni, AI. The barrier metal electrode (7) is formed by a sputtering method or the like in this order, and is composed of an insulating film (5) formed in a region not in contact with the epitaxial layer (4) or the isolation region (6).

本発明の特徴とするところは、前記埋め込み領域(3)
と前記分離領域(6)にある。前記N+型の埋め込み領
域(3)は前記半導体基板(2)上に選択的にアンチモ
ンを拡散し、分離領域(6)内の少なくとも一部に形成
される。ここで分離領域(6)はメツシュ状等に形成し
ても良い。従って前記バリアメタル電極(7)から半導
体基板(2)へ流れ込む電流の経路を短かくすることが
できるため、この部分の抵抗を減少できる。
The feature of the present invention is that the embedded area (3)
and in the separation area (6). The N+ type buried region (3) selectively diffuses antimony onto the semiconductor substrate (2) and is formed in at least a part of the isolation region (6). Here, the separation region (6) may be formed in a mesh shape or the like. Therefore, the path of the current flowing from the barrier metal electrode (7) to the semiconductor substrate (2) can be shortened, so that the resistance in this portion can be reduced.

一方前記N 型の分離領域(6)はN型のエピタキシャ
ル層(4)周縁に前記エピタキシャル層(4)表面より
前記N+型の半導体基板(2)表面まで達するように形
成される。ここでは形成法としてイオンインプラ等を用
いた拡散等が考えられる。従って前記Nをのエピタキシ
ャル層(4)より高濃度のN+型の分離領域(6)が形
成されることで、一部の電流が前記N”Wの分離領域(
6)に流れ込むため、ショットキーバリア・ダイオード
(1)の前記エピタキシャル層(4)と半導体基板(2
)の境界面積を増加したことになり、抵抗を減少したこ
とになる。
On the other hand, the N type isolation region (6) is formed at the periphery of the N type epitaxial layer (4) so as to reach from the surface of the epitaxial layer (4) to the surface of the N+ type semiconductor substrate (2). Here, diffusion using ion implantation or the like may be considered as a forming method. Therefore, by forming an N+ type isolation region (6) with a higher concentration than the N epitaxial layer (4), a part of the current is transferred to the N''W isolation region (
6), the epitaxial layer (4) of the Schottky barrier diode (1) and the semiconductor substrate (2)
) has increased the boundary area, which means that the resistance has decreased.

また第2図・第3図は本発明の実施例であり夫れ夫れN
”型・P+型のガードリングを用いた場合のショットキ
ーバリア・ダイオードの断面図である。
Moreover, FIGS. 2 and 3 show embodiments of the present invention, and each figure is an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a Schottky barrier diode using a "type" type/P+ type guard ring.

(ト)  発明の効果 本発明は斯上の説明からも明らかな如(、前記半導体基
板(2)上に選択的にアンチモンを拡散し、分離領域(
6)内の少なくとも一部に形成したN+型の埋め込み領
域(3)と、前記N型のエピタキシャル層(4)周縁に
前記エピタキシャル層(4)表面より前記N+型の半導
体基板(21表面まで形成されるN+型の分離領域(6
)とにより、ショットキーバリア・ダイオードの抵抗を
減少させ順方向電圧■、を小さくすることができる。
(g) Effects of the Invention As is clear from the above description, the present invention provides a method for selectively diffusing antimony onto the semiconductor substrate (2) and forming a separation region (
6) an N+ type buried region (3) formed in at least a part of the N+ type semiconductor substrate (21) and an N+ type buried region (3) formed at the periphery of the N type epitaxial layer (4) from the surface of the epitaxial layer (4) to the surface of the N+ type semiconductor substrate (21); N+ type isolation region (6
), it is possible to reduce the resistance of the Schottky barrier diode and reduce the forward voltage (2).

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図は本発明の実施例であるショットキー
バリア・ダイオードの断面図、第4図は従来のショット
キーバリア・ダイオードの断面図である。 主な図番の説明は (1)はショットキーバリア・ダイオード、(2)は半
導体基板、(3)は埋め込み層、(4)はエピタキシャ
ル層、(5)はシリコン酸化膜、(6)は分離領域、(
7)はバリアメタル電極である。 出願人 三洋電機株式会社 外1名 代理人 弁理士  佐 野 静 失 策1図 第2図 第3図 第4図
1 to 3 are cross-sectional views of a Schottky barrier diode according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of a conventional Schottky barrier diode. The explanation of the main figure numbers is (1) is Schottky barrier diode, (2) is semiconductor substrate, (3) is buried layer, (4) is epitaxial layer, (5) is silicon oxide film, (6) is Separation area, (
7) is a barrier metal electrode. Applicant Sanyo Electric Co., Ltd. and 1 other representative Patent attorney Shizuka Sano Mistake 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)高不純物濃度の一導電型の半導体基板と該半導体
基板上に形成された一導電型のエピタキシャル層と該エ
ピタキシャル層に接触するバリアメタル電極と該バリア
メタル電極が前記エピタキシャル層と接触しない領域に
形成した絶縁膜とを具備するショットキーバリア・ダイ
オードに於いて、前記エピタキシャル層の周縁に前記エ
ピタキシャル層表面より前記半導体基板表面まで達する
高不純物濃度の分離領域と、前記半導体基板上の分離領
域内の少なくとも一部に形成される一導電型の埋め込み
領域とにより構成されることを特徴としたショットキー
バリア・ダイオード。
(1) A highly impurity-concentrated semiconductor substrate of one conductivity type, an epitaxial layer of one conductivity type formed on the semiconductor substrate, a barrier metal electrode in contact with the epitaxial layer, and the barrier metal electrode not in contact with the epitaxial layer. In the Schottky barrier diode, the Schottky barrier diode includes an isolation region with a high impurity concentration extending from the surface of the epitaxial layer to the surface of the semiconductor substrate at the periphery of the epitaxial layer, and an isolation region on the semiconductor substrate. A Schottky barrier diode comprising a buried region of one conductivity type formed in at least a part of the region.
JP17275685A 1985-08-06 1985-08-06 Schottky barrier diode Pending JPS6233456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17275685A JPS6233456A (en) 1985-08-06 1985-08-06 Schottky barrier diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17275685A JPS6233456A (en) 1985-08-06 1985-08-06 Schottky barrier diode

Publications (1)

Publication Number Publication Date
JPS6233456A true JPS6233456A (en) 1987-02-13

Family

ID=15947741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17275685A Pending JPS6233456A (en) 1985-08-06 1985-08-06 Schottky barrier diode

Country Status (1)

Country Link
JP (1) JPS6233456A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04261065A (en) * 1991-01-29 1992-09-17 Mitsubishi Electric Corp Semiconductor device
US6583485B2 (en) * 2000-03-30 2003-06-24 Koninklijke Philips Electronics N.V. Schottky diode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04261065A (en) * 1991-01-29 1992-09-17 Mitsubishi Electric Corp Semiconductor device
US6583485B2 (en) * 2000-03-30 2003-06-24 Koninklijke Philips Electronics N.V. Schottky diode

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