JPS6232497A - Sound source unit for electronic appliance - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a sound source device for electronic equipment, and more particularly to a sound source device suitable for generating sound effects for an electronic game machine such as a television game machine.

(Prior art) An interesting prior art for this invention is the Japanese Patent Publication No. 54-3352.
It is disclosed in Publication No. 5. This conventional technology uses frequency modulation (FM
), this is a so-called digital synthesizer that digitally synthesizes a musical tone that approximates the timbre of an instrument.

This conventional technique can be effectively used for keyboard instruments that need to generate musical tones of the timbre depending on the type of musical instrument.

On the other hand, in electronic game machines such as video game machines, it is necessary to generate sound effects that are effective in enhancing the game content or attracting players' interest. An example of such a sound effect is a continuous change sound (hereinafter referred to as a "sweep sound") in which the frequency is continuously increased or decreased.
) is possible.

(Problems to be Solved by the Invention) However, with the above-mentioned conventional technology, such a sweep sound cannot be generated. The reason is as follows.

Musical tone (e) in the prior art is given by the following equation (.

e=A sin (ωct+I(t) sin 0m t
) In the above formula, ■ The term (t) sinωmt is the product, the maximum value is I(t), and the minimum value is -I (Oscillation occurs in the range of t>, and as a result) the average value of the term (t) sinωmt becomes O. Therefore, the average value of tone (e) is given by the following equation.

e=As in ωc t As described above, in the conventional technology, the average frequency remains constant, and the above-mentioned sweep sound cannot be generated.

Therefore, the main object of the present invention is to provide a sound source device for electronic equipment that can generate a sweep sound.

Another object of the present invention is to provide a sound source device for electronic equipment that can be advantageously applied to generating sound effects for electronic game machines.

(Means for Solving the Problems) Simply put, the present invention is based on a first storage means for storing waveform data of a fundamental wave as a digital value, based on modulation envelope data (B(t)). , comprising calculation means for determining modulation index data (J(t)) that changes as a function of time, and first multiplication means for multiplying the frequency data (ωc) of the fundamental wave and the modulation index data, 1st
The multiplication result of the multiplication means is given to the first storage means as a read address, thereby changing the read speed of this first storage means, and further converting the digital value read from the first storage means into an analog comprising a D/A conversion means for converting into a signal and outputting an audio signal (e);
This is a sound source device for electronic equipment.

(Operation) Waveform data of, for example, a fundamental wave of a sine wave is stored in the first storage means. The arithmetic means calculates the modulation index (J(t)) based on the modulation envelope data (B(t)). The first multiplication means has frequency data of the fundamental wave (
ωc) and the modulation index data to obtain data “J (t
) ・ωct”.This data “J(t)ω
ct" determines the read address of the first storage means. Therefore, the read speed in the first storage means is changed by the data "J (t) . The fundamental wave is frequency modulated by

The digital value read from the first storage means is D/A
It is converted into a final audio signal (e) by a converter.

In this invention, an audio signal (e) according to the following equation (t) is obtained.

e = As inJ (t) ・ωct --
11) However, A is the amplitude of the fundamental wave, sinωct is the fundamental wave, and the modulation index (J(t)) is given by the following equation (2).

J (t)=B (t) (C+s inωmt)
...(2) Here, B (t) represents a modulation envelope, C represents a constant, and sinωmt represents a modulation wave.

(Effects of the Invention) According to the present invention, the frequency of the audio signal changes as a function of time due to frequency modulation, and even if the modulation component is integrated, it does not become "0", which could not be done with the prior art. In addition, it is possible to generate a "sweep sound" that is more effective as a sound effect for, for example, an electronic game machine.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

(Embodiment) FIG. 2 is a block diagram showing an example of a video game system to which the present invention is applied. Below, a case will be described in which the present invention is applied to a video game system. However, it should be pointed out in advance that this invention can be used as a sound source device for all other electronic devices.

Commercial power is supplied to the main body 12 of the game device through an AC adapter (not shown). . . Two controllers 14 are connected to the main body 12 by appropriate connection cables. Further, an adapter 16 is connected to the main body 12, and a data input device 20 is connected to the adapter 16. This data input device 20 is formed with an insertion slot 22 into which a floppy disk 24 is inserted.

Note that as the main body 12, for example, "Family Computer" (trademark) manufactured by the applicant of the present invention can be used.

Various data for the game is provided from the data input device 20 to the main body 12 through the adapter 16, depending on the data previously written on the floppy disk 24. Therefore, from the main body 12, the floppy disk 24
A TV signal is output for playing a game according to the content of the game. This TV signal is given to an antenna terminal (not shown) of the TV receiver 26.

Therefore, the operator can operate the controller 14 to arbitrarily control the game characters on the display screen of the TV receiver 26, thereby enjoying the video game.

FIG. 3 is a block diagram showing the system configuration of FIG. 2. As mentioned above, the controller 14 is connected to the main body 12, and the signal from the controller 1-roller 14 is transmitted to the I10
It is provided to the CPU 30 through the interface 28.

A RAM 32 is connected to the CPU 30 and stores data for controlling transfers.
A PPU 34 that receives image data from 0 is connected.

Note that as the CPU 30, for example, a microprocessor such as an integrated circuit "Z80A" manufactured by Zilog Corporation can be used. The PPU 34 is for generating image signals for the game based on image data from the CP tJ 30. As this PPU 34, for example, an integrated circuit "2C03" manufactured by Nintendo Co., Ltd. can be used.

The image signal from the PPtJ 34 is converted into, for example, an NTSC TV signal by the RF modulation circuit 36, and this TV signal is applied to the mantenna terminal of the 1.V receiver 2G through a coaxial cable.

The main body 12 is provided with a core lid 38 for connecting the adapter 16. Therefore, the CPU 30 can exchange various data with the adapter 16, that is, the data input device 20, through the I10 interface 28 through the respective connector 38.

Data input device 20 is connected to adapter 16
0 interface 40. In addition, the data input position 20 has an insertion slot 22 (second slot) for the floppy disk 24.
A disk drive 44 is provided, and a head 46 is provided in connection with the disk drive 44. A mounting detection signal indicating that the floppy disk 24 has been inserted is sent from the disk drive device 44 to I10.
CPU included in main body 12 through interface 40
given to 30. In addition, this disk drive device 44
Various command signals are given from the CPU 30 to the CPU 30.

The data read by the head 46 is transmitted to the CPTJ included in the main body 12 through the I10 interface 40.
given to 30.

The I10 interface 40 of the data input device 20 includes:
A first RAM 48 and a second RAM 50 are connected. These first and second RAMs 48 and 50 store various data read by the head 46 from the floppy disk 24 under the control of the CP tl 30 of the main body 12, respectively, as shown in FIG. It is written according to the memory map shown below. That is, the floppy disk 24 contains an audio control program 24a and sound source data 24b.

A game control program 24c and game display data 24d are written in advance according to the game content. Then, the contents of this floppy disk 24 are read out, and the audio control program 24a and sound source data 24b are read out.
, the game control professional gamer 24e is stored in the first RAM 48
is written to a predetermined address. In addition, the second RAM 5
Game display data 24d is written in 0.

The data input device 20 is provided with a sound source circuit 52 connected to the I10 interface 40 and to which the present invention is directed. This sound source circuit 52 mainly includes the first RAM 4
This is for generating an audio signal (e) based on the sound source data written in 8, as will be explained in more detail later with reference to FIG. The audio signal from this sound source circuit 52 is amplified by an audio amplification circuit 54 and is applied to the RF modulation circuit 36 of the main body 12 through the adapter 16 and connector 38. Therefore, the RF modulation circuit 36
Then, the game image signal from the PPU 34 and the audio signal from the audio amplifier circuit 54 are processed to generate a normal TV signal of, for example, the NTSC system.

To simply explain the operation of the system shown in FIG. 3, first, the floppy disk 24 is loaded into the data input device 20. In response, disk drive 44 detects this and this detection signal is transmitted to I10 interface 40.
Adapter 16. It is provided to CPU 30 through connector 38 and I10 interface 28. CPU30
accordingly, in the reverse path to the disk drive 44.
Give drive commands to. In response to the command, the floppy disk 24 is driven by the disk drive device 44. The head 46 reads programs and data 24a to 24d as shown in FIG. 4 from the floppy disk 24. The read programs and data are transferred to the RAM of the main body 12 through the CPU 30 through the same route as before.
He was temporarily suspended in 32. Then, the CPU 30 writes the programs and data stored in the RAM 32 to predetermined addresses in the RAMs 48 and 50 of the data input bag ff20, as described above. That is, at this point, the first and second RAM4
8 and 50 store game programs and data specific to the floppy disk 24 from the floppy disk 24.

The player or operator then uses the controller 14.
When operated, the operation signal is sent to I10 interface 2.
8 to the CPU 30. With CPU30,
Based on the signal from the controller 14, the RAM 3
2, the first and second RAMs 48 and 50
The CPU 34 processes the data stored in the CPU 34 and provides the PPU 34 with image data corresponding to the current state of the game. P
P U , 34 converts the image data into an image signal.

On the other hand, the sound source circuit 52 generates an audio signal based on the above-described sound source data from the first RAM 48 provided through the I10 interface 40, and this audio signal is amplified and provided to the RF modulation circuit 36.

An NTSC TV signal is output from the RF modulation circuit 36, and as a result, on the display screen of the TV receiver 26,
The background, game characters, score, etc. for playing the game are displayed. And controller 14
, the game character on the display screen does not move or change arbitrarily.

In this way, the sound effects necessary for the game system are
It is generated by the sound source circuit 52.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This sound source circuit 52 includes a fundamental wave waveform data storage RAM 56 as a first storage means for storing waveform data of a modulated wave or a fundamental wave. Fundamental wave waveform data, such as sine data (sin), is written into the fundamental wave waveform data storage means RAM 56 from the CPU 30 in accordance with the write (W) address. The fundamental waveform data, for example, divides one cycle of a sine wave into 64 T/
64) is 6-bit data representing the amplitude value sampled at each timing. Therefore, this waveform data storage RAM 56 has a 64×6 bit star area.

Note that as the waveform of the fundamental wave, in addition to a sine wave, arbitrary waveforms such as a cosine wave, a triangular wave, a sawtooth wave, etc. can be considered.

A fundamental wave frequency data register 58 is provided to receive the frequency data of the fundamental wave from the CPU 30, and the fundamental wave frequency data register 58 outputs 12-bit fundamental wave frequency (ωc) data. Data from the fundamental frequency data register 58 is provided to a 19-bit shift register 60, for example. This shift register 60 receives, for example, a 1 μsec signal from the clock generator 62.
A clock signal CL of C is provided as a shift signal, and an output from a frequency divider 64 for frequency-dividing this clock signal by 1/8 is provided as a load signal. Therefore, when the load signal is applied to the shift register 60, the 12-bit data from the fundamental wave frequency data register 58 is loaded into its lower 12 bits. At this time, 10' is loaded into the upper 7 bits of the shift register 60. Thereafter, it is shifted to the left by 1 bit every clock, and at the n-th clock, the data of the fundamental frequency (ωc
) will be loaded into the shift register 60. However, since the load command signal is given from the frequency divider 64 every 8 clocks, n is 0 to 7.

The 19 bits from shift register 60 are sent to full adder 66.
is given to the lower 19 bits of one input. The upper five bits of the full adder 66 are given "0", and the other input is given the 24 bits of the output of the latch circuit 68. Therefore, full adder 66 is a 24-bit full adder.

The 24 bits of the output of the full adder 66 are applied to a launch circuit 68 with the same number of bits. This latch circuit 68 has
1 of the clock generator 62 from an AND gate 90 to be described later.
A signal indicating whether a latch operation is necessary is applied to each clock. That is, the above-mentioned shift register 60. A first multiplication means that multiplies the frequency of the fundamental wave (ωc) and the modulation index (J(t)) by the full adder 66 and the latch circuit 68 and outputs data “J(t)・ωct”. Configure. The upper 6 bits of the launch circuit 68 are given as a read address of the fundamental waveform data storage RAM 56.

In this manner, waveform conversion (sine conversion in the embodiment) is performed in the fundamental waveform data storage RAM 56, and fundamental waveform data, for example (sinωct), is output from the modulated waveform data storage RAM 56. However,
U, 7chi circuit 68. ) for (sinωct
-J(t)) is output.

The circuit portion that generates the modulation index (J(t)) will be described below. A RAM 70 for storing modulated waveform data is provided as a second storage means, and this RAM 70 includes a
Waveform data of a modulated wave, such as sine data (sin), is written from U30 according to the write (W) address. The modulation waveform data, like the fundamental waveform data,
For example, one cycle of a sine wave is divided into 64 parts (T/64)
, is 6-bit data representing the amplitude value sampled at each timing. Therefore, the modulated waveform data storage RAM 70 has a storage area of 64×6 bits. Note that the modulated wave is not necessarily limited to a sine wave. For example, triangular waves, sawtooth waves, cosine waves, etc. can also be considered.

A modulation frequency data register 72 is provided that receives data on the modulation frequency (ωm) from the CPU 30. The 12-bit modulation frequency data from the modulation frequency data register 72 is applied to the lower 12 bits of one input of a 17-bit full adder 74, and "O" is applied to the upper 5 bits. The other input of this full adder 74 is connected to a frequency divider 64.
17 bits are provided from a latch circuit 76 which receives a latch signal from. The addition result by full adder 74 is applied to launch circuit 76 as 17-bit data.

The upper six bits of the launch circuit 76 are given as a read address of the above-mentioned modulated waveform data storage RAM 70.

In this manner, waveform conversion (sine conversion in the embodiment) is performed in the modulated waveform data storage RAM 20, and modulated waveform data, for example (sinωmt), is output from the modulated waveform data storage RAM 70.

On the other hand, a modulation amplitude data register 78 is provided to which amplitude data (B) of a modulated wave is given from the CPU 30. This modulated wave amplitude data (B) represents the amplitude of the modulated wave using 6-bit data. Modulation amplitude data register 7
Data from 8 is provided to U/D counter 80.

The U/D counter 80 is supplied with a signal (U/D) from the CPU 30 instructing up-counting or down-counting, and is also supplied with a count input from the programmable frequency divider 82 . The programmable frequency divider 82 divides the clock from the lmsec clock source 84 by an appropriate frequency division ratio given by the CPU 30. Therefore, by appropriately changing the modulation amplitude data (B)9 frequency division ratio and the U/D signal by the CPU 30, the U/D counter 80 outputs the modulation envelope data (B) whose amplitude changes arbitrarily. t)
) is output.

The modulated waveform data (sinωm t ) converted in the modulated waveform data storage RAM 70 and the U/D counter 8
Modulation envelope data (B(t)) starting from 0 is given to the multiplier 8602 as input. This multiplier 86 is
Multiply those inputs and use the previous (2) as the output.
The modulation index data (J(t)) expressed by the formula is output.

Modulation index data (J(t)) is provided to an 8-bit shift register 88. A 1 μsec clock from the clock generator 62 is applied to the shift register 88 as a right shift clock, and a signal from the frequency divider 64 is applied as a load signal. shift register 8
The least significant bit of 8 is applied to one input of the aforementioned AND gate 90. The other input of this AND gate 90 has
A clock of 1 μsec is given. Then, the output of the AND gate 90 is output to the latch circuit 68 as described above.
is given as a latch command to

That is, the lowest bit node of the shift register 88 is 1''.
When , from the AND gate 90, according to the clock, “
1'' is output, and the latch circuit 68 performs a latching operation accordingly.

A fundamental wave amplitude data register 92 is provided to receive fundamental wave amplitude data (A) from the CPU 30. This fundamental wave amplitude data (A) represents the amplitude of the fundamental wave as 6-bit data, and this data is input to the U/D counter 94.
given to. Like the U/D counter 80, the U/D counter 94 receives the output of a programmable frequency divider 98, which receives a clock from a 1,1m5ec clock source 96, as an increment or decrement signal. The programmable frequency divider 98 includes a CPU 30
An appropriate frequency division ratio is set from . This U/D counter 9
From 8 onwards, the fundamental wave envelope data whose amplitude changes over time, just like the modulation envelope before (
A(t)) is output.

The 6-bit fundamental wave envelope data from the U/D counter 94 is applied to one input of the comparator 102. The other input of the comparator 102 is given the 6-bit output of the counter 100, which is incremented every 0.5 μsec. The comparator 102 then converts the U/D counter 9
4, that is, the fundamental wave envelope data (A
(t)) is larger than the data from the counter 100, it becomes a high level, and conversely, when the data from the counter 100 is larger, it outputs a pulse signal that becomes a low level.

The pulse output from the comparator 102 is connected to the AND gate 104a.
-104g are commonly given to one input of each. The other input of each of these AND gates 1o4a to 104g is connected to the aforementioned fundamental waveform data storage RAM 5.
The data of the corresponding bits from 6 are given. and,
These AND gates 104a to 104g are connected to the comparator 10.
When the output of U/D counter 2 is high level, that is, U/D counter 9
When the data of 4 is greater than the data of counter 100,
The output of the fundamental wave waveform data storage RAM 56 is given to the D/A converter 106. In this way, and gate 10
RA for storing fundamental wave waveform data by 43 to 104g.
5 inJ(t)·ωct” given from M56 is pulse width modulated.

The operation of the embodiment shown in FIG. 1 will be explained. In this embodiment, the final audio signal is obtained from the D/A converter 106,
This is given by the above equation (t). The envelope (A(t)) of the fundamental wave is given from the U/D counter 94, and the modulation index (J(t)) is given from the multiplier 86. Further, the frequency data ωct of the fundamental wave is given from the shift register 60. From the latch circuit 68,
As mentioned above, "J (t) ωct" is outputted, and the read address is determined by the RAM 5.
6, therefore, "5inJ (t)-ωct" is output. And and gate 1043~104g
The final audio signal (e) given by equation (t) above is obtained by pulse width modulation.

To explain in more detail, in the shift register 60 related to the fundamental wave, the load signal from the frequency divider 64 loads the fundamental wave frequency data (ωc) into the lower 12 bits and “0” into the upper 5 bits. . Then, the left shift is repeated every 1 μsec clock from the clock generator 62. In other words, in this shift register 60, the frequency data (ωc) of the fundamental wave is changed by 2 at each rising edge of the clock.
It is multiplied by 0 times, 21 times, ..., 27 times. On the other hand, the latch signal from the AND gate 90 is output at the frequency of the fundamental wave at the rising edge of the first clock CL output at the falling edge of each clock, depending on the contents of the least significant bit of the shift register 88, "0" or 1. Data (ωc) is transferred to shift register 60
Then, at the first falling edge of the clock, if the least significant bit of the shift register 88 is “1”
”, the latch circuit 68 latches the data. Then, at the rising edge of the second clock, the shift register 68 latches the data.
0 is shifted to the left, so the least significant bit of its shift register 60 is 0'', and the previously loaded data (
ωc) is doubled. At the same time, the shift register 88
is shifted to the right, and the second bit from the bottom becomes the least significant bit. The doubled data in the shift register 60 is latched in response to the launch signal from the AND gate 90, which is output in response to the lowest bit of the shift register 88 being "1" at the falling edge of the second clock. Latched by circuit 68.

. . The upper six bits of the latch circuit 68 are used as a read address of the fundamental waveform data storage RAM 56. Then, as an initial state, the latch circuit 68 is "000".
...”, at the falling edge of the 8th clock, J (
t) - ωct is latched. Therefore, this R
The change in the read address of AM56 is a maximum of 8μsecC.
/2, that is, changes to "1" in a little over 4 μsec.

The modulation frequency data (ωm) is processed by the full adder 74 as follows:
Every 8 μsec, in the latch circuit 76, ωm, 2ω
m, 3ωm, . . . The upper six bits of the latch circuit 76 are used as a read address of the RAM 70 for storing modulated waveform data. Therefore, the amount of change in the upper 6 bits of the latch circuit 76 (read address of the RAM 70 for storing modulated waveform data) acts as modulation frequency data (ωmt) that determines the change period of the modulated wave, that is, the vibrato period. When the amount of change (Δωmt) in the latch circuit 76 is small, the vibrato period becomes thick.

A modulation amplitude data register 78 and a U/D counter 80 output sine wave data (sinωmt) converted by the modulation frequency data that changes in this way from the modulation waveform data storage RAM 70. Data (B (t)) is obtained. Therefore, multiplier 86 obtains the modulation index (J(t)) given by equation (2) above.

On the other hand, as shown in FIG. 5 (Δ), the fundamental wave waveform data storage RAM 56 outputs a sine wave component [5 inJ → ·ωct). As shown in FIG. 5(B), the comparator 102 outputs a pulse signal depending on the magnitude of the data of the two counters 94 and 100. The pulse signal shown in FIG. 5(B) causes the AND gates 104a to 104g to control the RAM shown in FIG. 5<A).
56, as shown in FIG. 5(C).
An audio signal (e) having a waveform as shown in FIG. 5(C) is obtained from the /A converter 106. Then, this audio signal passes through the audio amplification circuit 54 (FIG. 3) and then passes through the audio amplification circuit 54 (FIG. 3) as shown in FIG.
The waveform is integrated as follows, and is expressed by the following equation (3).

e=A sin Σ(B(n)(C+sin ωmn) ω
c + ωc)...(3) In the above equation (3), the modulation frequency data (ωm) is
0″, sinωm t = O, and this (
Equation 3) is transformed by the following equation (4).

e=AstnΣ(B(n)・C・ωc+ωc)...(
4) By setting the modulation envelope as a simple increasing function (or simple decreasing function) in the state a of , : as shown in FIG. 6(A), as shown in FIG. 6(B), It is possible to create a "sweep sound" in which the frequency of the audio signal, that is, the pitch of the sound, increases (or decreases) continuously.

Furthermore, if the constant C=0 in the above equation (3), the equation is transformed as shown in the following equation (5).

e=A sin Σ (B (n) (sin ωmn)
ωc+ωc)...(5) In this way, as shown in FIG. 7(A), the modulation index J(t) changes in the positive and negative directions around "0". Therefore, as shown in FIG. 7(B), the obtained audio signal has a frequency centered around fc-ωc/2π, fm=
The result is a so-called vibrato effect that changes finely at a frequency of ωm/2π.

Then, both the constant C and the modulation frequency data (ωm) in equation (t) above are set to non-zero values, and the modulation envelope data (B(t)) is set as a simple increasing function (or simple decreasing function). As a result, the modulation index becomes a combination of FIG. 6(A) and FIG. 7(A). Therefore, in this case, as shown in FIG. 8(A), a very unique audio signal is obtained in which vibrato is applied and the center frequency also changes. Such an audio signal cannot be created using the prior art 1:i cited above.

In addition, in the above-mentioned embodiment, as the sound source data setting means,
A flombi disc 24 (Fig. 2) was used. However, for such sound source data setting means, another recording means such as a ROM cartridge may be used, and instead of such a replaceable floppy disk or ROM cartridge, the sound source data setting means may be set fixedly in the internal ROM. Any storage means may be used.

Furthermore, in the embodiment shown in FIG. 1, discrete circuits are connected together and used. However, it goes without saying that the processing other than the D/A converter 106 in FIG. 1 can also be performed by software processing by one or more CPUs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing an example of a video game system to which the present invention can be applied. FIG. 3 is a block diagram showing the system of FIG. 2. FIG. 4 is an illustrative diagram showing a memory map. FIG. 5 is a waveform diagram for explaining part of the operation of the embodiment of FIG. 1. 6, 7 and 8 are waveform diagrams for explaining different operations of the embodiment in FIG. 1, in which (A) shows the modulation index and (B) is obtained. Indicates an audio signal. In the figure, 12 is the main body, 20 is a data input device, and 24
is a flonbi disk, 30 is a CPU, 52 is a sound source circuit,
56 is a RAM for storing fundamental waveform data, 60.88 is a shift register, 66.74 is a full adder, 68.76 is a latch circuit, 70 is a RAM for storing modulation waveform data, 86 is a multiplier, and 102 is a comparator. , IQ4a to 104g are AND gates, and 106 is a D/A converter. Patent Applicant Nintendo Co., Ltd. Agent Patent Attorney Yama 1) Yoshito (1 idiot) 2nd A Figure 4 Light Figure 5 Peerard Sound Figure 8 Person Ede + Loprato Procedural Procedure NeiTt Original Book ( Spontaneous) September 9, 1985 Patent Office District Office Uga Michibe 1, Indication of the case 1985 Patent side No. 172575 V2, Name of the invention Sound source device for electronic equipment 3, ? Lii Interaction with the case of a person who commits rectification Patent applicant address 60 Fukuinakami Takamatsu-cho, Higashiyama-ku, Kyoto-shi, Kyoto
Name: Nintendo Co., Ltd. Representative Hiroshi Yamauchi 4, Agent [Stocks] 540 g! Osaka (06) 7
64-5443 (Main) Address: 5-30-7 Tanimachi, Higashi-ku, Osaka Contents of amendment (t) "Star area" on page 16, line 13 of the specification is corrected to "storage area." (2) "When the data is large" on page 23, lines 19 and 20 of the specification is corrected to "when the data is the same as the data or the data on the counter 100 is large." (3) Figure 1 is corrected as shown in the attached sheet. that's all

Claims (1)

[Claims] 1. A first storage means for storing waveform data of a fundamental wave as a digital value, based on modulation envelope data (B(t)), modulation index data (J (t)), and a first multiplication means for multiplying the frequency data (ωc) of the fundamental wave by the modulation index data, and the multiplication result of the first multiplication means is the read address. The data is applied to the first storage means, thereby changing the reading speed of the first storage means, and converting the digital value read from the first storage means into an analog signal to generate an audio signal. D/A that outputs (e)
A sound source device for an electronic device, comprising a conversion means. 2. A patent claim, wherein the calculation means includes a second multiplication means for determining the modulation index data (J(t)) based on waveform data of a modulated wave having a frequency (ωm) and the modulation envelope data. A sound source device for an electronic device according to item 1. 3. The calculation means includes a second storage means for storing waveform data of the modulated wave as a digital value, and the waveform data of the modulated wave is read from the second storage means based on the modulation frequency data. 3. The sound source device for an electronic device according to claim 2, wherein the sound source device is provided to the second multiplication means. 4 Further, fundamental wave envelope data (A(t)) is given, and includes changing means for changing the output time from the first storage means based on the fundamental wave envelope data (A(t)). The sound source device for an electronic device according to any one of claims 1 to 3, wherein the amplitude of the audio signal from the D/A conversion means is changed according to the output time. 5. The changing means comprises means for outputting a pulse signal based on the fundamental wave envelope data and having a duration correlated thereto, and gating means for gating the output of the first storage means by the pulse signal. Claim 4, including:
A sound source device for an electronic device as described in Section 1. 6. A housing that houses at least the first storage means, the calculation means, the first multiplication means, and the D/A conversion means, and the means for setting the various data is detachably attached to the housing. A sound source device for an electronic device according to claim 1, comprising an external storage means.