CA1271845A - Electronic sound synthesizer - Google Patents
Electronic sound synthesizerInfo
- Publication number
- CA1271845A CA1271845A CA000515352A CA515352A CA1271845A CA 1271845 A CA1271845 A CA 1271845A CA 000515352 A CA000515352 A CA 000515352A CA 515352 A CA515352 A CA 515352A CA 1271845 A CA1271845 A CA 1271845A
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- modulation
- signal
- sound source
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Abstract
ABSTRACT
A sound source apparatus of electronic equipment employs a frequency modulation. Wave-form data of a fundamental wave and a modulation wave are both stored in a RAM as the 6-bit digital data. A sine wave signal is produced by a modulation wave frequency data and the wave-form data from the RAM, the sine wave signal is multiplied with an amplitude data of the modulation wave to obtain the modulation index data (J(t)).
The frequency data(.omega.c) of the fundamental wave and the modulation index data are multiplied, and a result of the multiplication is given as a read out address of the RAM for storing the wave-form data of the fundamental wave, thereby the read out speed of the RAM is changed. The digital data read out from the RAM is converted as a sound signal of an analog signal by a D/A converter. An amplitude data (A) of the fundamental wave is further pulse-width modulated, and the digital data from the RAM is gated by the modulated pulse, thus the output of the D/A converter is activated and, therefore, the output of the D/A converter becomes to a sound signal represented by the equation e = A sin J (t) .omega.ct.
A sound source apparatus of electronic equipment employs a frequency modulation. Wave-form data of a fundamental wave and a modulation wave are both stored in a RAM as the 6-bit digital data. A sine wave signal is produced by a modulation wave frequency data and the wave-form data from the RAM, the sine wave signal is multiplied with an amplitude data of the modulation wave to obtain the modulation index data (J(t)).
The frequency data(.omega.c) of the fundamental wave and the modulation index data are multiplied, and a result of the multiplication is given as a read out address of the RAM for storing the wave-form data of the fundamental wave, thereby the read out speed of the RAM is changed. The digital data read out from the RAM is converted as a sound signal of an analog signal by a D/A converter. An amplitude data (A) of the fundamental wave is further pulse-width modulated, and the digital data from the RAM is gated by the modulated pulse, thus the output of the D/A converter is activated and, therefore, the output of the D/A converter becomes to a sound signal represented by the equation e = A sin J (t) .omega.ct.
Description
12~i84~
BA~KGROUND OF THE INVENTION
Field of the Invention The present invention relates to a sound source appara-tus of electronic equipment. More specifically, the present invention relates to the sound source apparatus suitable for producing an effect sound of an electronic game machine, for example, such as a television game machine.
10 Description of the Prior Art The interesting prior art of the present invention is disclosed in Japanese Patent Publication No. 33525/1979 issued October 22, 1979. The prior art is a so-called digi-tal synthesizer, which synthesizes a musical sound closely 15 resembled to the tone of musical instruments digitally by using a frequency modulation (FM) so as to give the time variation to the spectrum component of the musical sound according to the kindq of musical instruments such as a brass or the wood.
The prior art may be utilized efficaciously in keyed instruments required to produce the musical sound of the tone responsive to the kinds of musical instruments.
~d~
12~84~i While, for example, in the electronic game machine such as the television game machine, it is necessary to produce the effect sound efficacious to enhance the game content and to interest the players. As one exampIe of such effect 5 sound, for example, a continuous changing sound, hereinafter referred to as a sweep sound, increasing -or reducing the frequency continuously may be considered.
However, in the abovementioned prior art, such sweep sound could not be produced, the reason for which is as 10 follows;
The musical sound signal (e) in the prior art may be given by the following equation.
e = A sin [ ~c t + I (t) sin ~m t ]
In the above equation, if the term I(t) sin ~m t is 15 integrated, the result will be ,Oo J'I(t) sin ~m t d t which oscillates within the range of I(t) as the maximum and -I(t) as the minimum, resulting in a mean value of "0", thus a mean value of the musical sound signal (e) may be given as, 20 e = A si~ ~c t.
Thus, in the prior art, the mean frequency becomes constant, so that the "sweep sound" described above is not produced.
SUMMARY OF THE INVENTION
BA~KGROUND OF THE INVENTION
Field of the Invention The present invention relates to a sound source appara-tus of electronic equipment. More specifically, the present invention relates to the sound source apparatus suitable for producing an effect sound of an electronic game machine, for example, such as a television game machine.
10 Description of the Prior Art The interesting prior art of the present invention is disclosed in Japanese Patent Publication No. 33525/1979 issued October 22, 1979. The prior art is a so-called digi-tal synthesizer, which synthesizes a musical sound closely 15 resembled to the tone of musical instruments digitally by using a frequency modulation (FM) so as to give the time variation to the spectrum component of the musical sound according to the kindq of musical instruments such as a brass or the wood.
The prior art may be utilized efficaciously in keyed instruments required to produce the musical sound of the tone responsive to the kinds of musical instruments.
~d~
12~84~i While, for example, in the electronic game machine such as the television game machine, it is necessary to produce the effect sound efficacious to enhance the game content and to interest the players. As one exampIe of such effect 5 sound, for example, a continuous changing sound, hereinafter referred to as a sweep sound, increasing -or reducing the frequency continuously may be considered.
However, in the abovementioned prior art, such sweep sound could not be produced, the reason for which is as 10 follows;
The musical sound signal (e) in the prior art may be given by the following equation.
e = A sin [ ~c t + I (t) sin ~m t ]
In the above equation, if the term I(t) sin ~m t is 15 integrated, the result will be ,Oo J'I(t) sin ~m t d t which oscillates within the range of I(t) as the maximum and -I(t) as the minimum, resulting in a mean value of "0", thus a mean value of the musical sound signal (e) may be given as, 20 e = A si~ ~c t.
Thus, in the prior art, the mean frequency becomes constant, so that the "sweep sound" described above is not produced.
SUMMARY OF THE INVENTION
- 2 -~271 845 It is, therefore, a principal object of the present invention to provide a sound source apparatus of electronic equipment, which is capable of producing a sweep sound.
It is another object of the present invention to provide 5 a sound source apparatus, which is applicable usefully for producing an effect sound of an electronic gàme machine.
It is a further object of the present invention to provide a sound source apparatus of electronic equipment, which is capable of simplifying the circuit configuration lO considerably and very low in cost.
The present invention, in brief, involves the sound source apparatus of electronic equipment comprising, a first memory means for storing a wave-form data of a fundamental wave in a digital value, an operation means for operation to 15 obtain the modulation index data (J(t)) changing at the time function based upon the modulation envelop data (B(t)), and a first multiplying means for multiplying the frequency data (~c) of the fundamental wave and the modulation index data (J(t)), the multiplied result of the first multiplying means 20 is given to said first memory means as the read out address, thereby changing the read out speed of the first memory means, and further comprising a D/A converter means convert-ing the digital value read out from the first memory means into an analog signal to output a sound signal (e).
In the first memory means, the wave-form data of the .j
It is another object of the present invention to provide 5 a sound source apparatus, which is applicable usefully for producing an effect sound of an electronic gàme machine.
It is a further object of the present invention to provide a sound source apparatus of electronic equipment, which is capable of simplifying the circuit configuration lO considerably and very low in cost.
The present invention, in brief, involves the sound source apparatus of electronic equipment comprising, a first memory means for storing a wave-form data of a fundamental wave in a digital value, an operation means for operation to 15 obtain the modulation index data (J(t)) changing at the time function based upon the modulation envelop data (B(t)), and a first multiplying means for multiplying the frequency data (~c) of the fundamental wave and the modulation index data (J(t)), the multiplied result of the first multiplying means 20 is given to said first memory means as the read out address, thereby changing the read out speed of the first memory means, and further comprising a D/A converter means convert-ing the digital value read out from the first memory means into an analog signal to output a sound signal (e).
In the first memory means, the wave-form data of the .j
- 3 -fundamental wave of, for example, the sine wave is stored.
The modulation index data (J(t)) is obtained by the operating means on the basis of the modulation envelop data (B(t)).
The first multiplying means multiplies the frequency data 5 (~c) of the fundamental wave and the modulatlon index data to output the data "J(t) ~c t", by which the read out address of the first memory means is determined. Accordingly, the read out speed from the first memory means is changed by the data "J(t) ~ct''. That is, the frequency modulation of the 10 fundamental wave is effected by the modulation index data changing with the time. The digital value read out from the first memory means is converted into the final sound signal (e) by the D/A converter.
In the present invention, the sound signal (e) according 15 to the following equation (1) is obtained.
e = A sin J (t) ~ c t ................... (1) In the equation (1), A indicates an amplitude of the funda-mental wave, sin ~c t indicates the fundamental wave, and the modulation index (J(t)) is given by the following equation 20 (2).
J (t) = B (t) (C + sin~ m t) ............ (2) Here, B(t) represents the modulation envelop, C is the con-stant, and sin ~m t represents the modulation wave.
According to the present invention, the frequency of the 25 sound signal is changed at the time function by the frequency
The modulation index data (J(t)) is obtained by the operating means on the basis of the modulation envelop data (B(t)).
The first multiplying means multiplies the frequency data 5 (~c) of the fundamental wave and the modulatlon index data to output the data "J(t) ~c t", by which the read out address of the first memory means is determined. Accordingly, the read out speed from the first memory means is changed by the data "J(t) ~ct''. That is, the frequency modulation of the 10 fundamental wave is effected by the modulation index data changing with the time. The digital value read out from the first memory means is converted into the final sound signal (e) by the D/A converter.
In the present invention, the sound signal (e) according 15 to the following equation (1) is obtained.
e = A sin J (t) ~ c t ................... (1) In the equation (1), A indicates an amplitude of the funda-mental wave, sin ~c t indicates the fundamental wave, and the modulation index (J(t)) is given by the following equation 20 (2).
J (t) = B (t) (C + sin~ m t) ............ (2) Here, B(t) represents the modulation envelop, C is the con-stant, and sin ~m t represents the modulation wave.
According to the present invention, the frequency of the 25 sound signal is changed at the time function by the frequency
- 4 -lZ7~
modulation, and the integration of its modulated component will not result in "0", so that the "sweep sound" efficacious as the effect sound, for example, in the electronic game machine may be produced, which was impossible in the prior
modulation, and the integration of its modulated component will not result in "0", so that the "sweep sound" efficacious as the effect sound, for example, in the electronic game machine may be produced, which was impossible in the prior
5 art.
In the embodiment of the present invention, there are provided means for producing a certain instantaneous ampli-tude data of the envelop signal of the fundamental wave, means for outputting the time-width signal having the time 10 width corresponding to the instantaneous amplitude, and an activating means for activating the output of the D/A con-verter responsive to the time-width signal.
For example, the wave-form data is outputted in sequence from a wave-form data producing means such as an RAM or ROM, 15 and the time-width signal is outputted as the signal having the time-width corresponding to the respective instantaneous envelop amplitudes. The wave-form data is converted into the analog signal by the D/A converter.
The activating means, in one embodiment, gates the 20 wave-form data from the wave-form data producing means by the time-width signal to apply to the D/A converter, the output of which is thereby activated during the time-width signal and smoothed into the musical sound signal.
In another embodiment, the fundamental wave data from 25 the wave-form producing means is given to the D/A converter i27~845 as is, and the DC voltage applied to the D/A converter is turned on and off by the activating means.
In a further embodiment, the fundamental wave data from the wave-form data producing means is given to the D/A con-5 verter as is, whose output is then applied to an analogswitch, the output of which is smoothed into the musical sound signal.
These objects and other objects, features, aspects and features of the present invention will become more apparent 10 from the following detailed description of the embodiments of the present invention when taken in conjunction with accom-panying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic construction view showing one 15 example of a video game system, to which the present inven-tion may be applied.
Fig. 2 i~ a block diagram showing the system of Fig. 1.
Fig. 3 is a block diagram showing one embodiment in accordance with the present invention.
Fig. 4 ls a schematic view showing a memory map of the embodiment of Fig. 2.
Figs. 5A through 5D are wave-form diagrams showing a part of operation of the embodiment of Fig. 3.
Figs. 6A, 6B, 7A, 7B, 8A and 8B are wave-form diagrams
In the embodiment of the present invention, there are provided means for producing a certain instantaneous ampli-tude data of the envelop signal of the fundamental wave, means for outputting the time-width signal having the time 10 width corresponding to the instantaneous amplitude, and an activating means for activating the output of the D/A con-verter responsive to the time-width signal.
For example, the wave-form data is outputted in sequence from a wave-form data producing means such as an RAM or ROM, 15 and the time-width signal is outputted as the signal having the time-width corresponding to the respective instantaneous envelop amplitudes. The wave-form data is converted into the analog signal by the D/A converter.
The activating means, in one embodiment, gates the 20 wave-form data from the wave-form data producing means by the time-width signal to apply to the D/A converter, the output of which is thereby activated during the time-width signal and smoothed into the musical sound signal.
In another embodiment, the fundamental wave data from 25 the wave-form producing means is given to the D/A converter i27~845 as is, and the DC voltage applied to the D/A converter is turned on and off by the activating means.
In a further embodiment, the fundamental wave data from the wave-form data producing means is given to the D/A con-5 verter as is, whose output is then applied to an analogswitch, the output of which is smoothed into the musical sound signal.
These objects and other objects, features, aspects and features of the present invention will become more apparent 10 from the following detailed description of the embodiments of the present invention when taken in conjunction with accom-panying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic construction view showing one 15 example of a video game system, to which the present inven-tion may be applied.
Fig. 2 i~ a block diagram showing the system of Fig. 1.
Fig. 3 is a block diagram showing one embodiment in accordance with the present invention.
Fig. 4 ls a schematic view showing a memory map of the embodiment of Fig. 2.
Figs. 5A through 5D are wave-form diagrams showing a part of operation of the embodiment of Fig. 3.
Figs. 6A, 6B, 7A, 7B, 8A and 8B are wave-form diagrams
- 6 -127~84~i showing respectively the difference operations of the embodi-ment of Fig. 3, in which (A) show a modulation index, while (B) show a sound signal being obtained.
Fig. 9 is a block diagram showing a major portion of 5 another embodiment in accordance with the present invention.
Fig. 10 is a block diagram showing a major portion o~ a further embodiment in accordance with the present invention.
Fig. ll is a block diagram showing a major portion of the other embodiment in accordance with the present inven-10 tion.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. l is a schematic construction view showing oneexample of a video game system to which the present invention may be applied. In the following, the case where the present 15 invention is applied to a video game system will be explain-ed. It will be appreciated, however, that the present invention may be used as a sound source apparatus for all other electronic equipments.
A commercial power source is applied through an AC
20 adapter, not shown, to a main unit 12 of the game machine.
Two controllers 14 are connected through to the main unit 12 the suitable connecting cables. To the main unit 12 there is connected an adapter 16 to which a data input device 20 is connected. An inserting mouth 22 for inserting a floppy disk i2~84~
24 is formed on the data input device 20.
AS the main unit 12, for example, a "family computer"
(trademark) manufactured and marketed by the assignee of the present invention may be utilized.
Responsive to the data written into the floppy disk 24 in advance, various data for the game are given to the main unit 12 from the data input device 20 via the adapter 16.
Thus, from the main unit 12, a TV signal for executing the game corresponding to the content of the floppy disk 24 is 10 outputted to an antenna terminal, not shown, of a TV receiver 26.
In such a video game system, the operator can enjoy the video game by operating the controller 14 to control the game character on the display screen of the TV receiver 26 15 optionally.
Fig. 2 is a block diagram showing a system configuration of Fig. l. As previously described, to the main unit 12 there is connected the controller 14, the signal from which is given to a CPU 30 through the I/O interface 28. To the 20 CPU 30, a RAM 32 for storing various controlling data as well as a PPU 34 receiving the image data from the CPU 30 are connected. As the CPU 30, for example, a microprocessor such as an integrated circuit "2A02" by Nintendo may be used. The PPU 34 is designed to produce the image signal for the game 25 on the basis of the image data from the CPU 30. As the PPU
~27~845 34, for example, an integrated circuit "2c03'~ by Nintendo may be utilized.
The image signal from the PPu 34 is converted into a TV signal of NTSC system, for example, by an RF
modulation circuit 36, and fed to the antenna terminal of the TV receiver 26 via a coaxial cable.
On the main unit 12, a connector 38 for connecting the adapter 16 is provided. Therefore, the CPU
30, through the connector 38, gives and receives various data to and from the adapter 16 and thus the data input device 20 via the I/O interface 28.
The data input device 20 incudes an I/O interface 40 connected to the adapter 16. On the data input device 20, associating with the inserting mouth 22 (Fig. 1) of the floppy disk 24, there is provided a disk dri~e 44 and a head 46 associating therewith. From the disk drive 44, the insertion detecting signal indicating an insertion of the floppy disk 24, is given through the I/O interface 40 to the CPU 30 incorporated in the main unit 12. To the disk drive 44, various command signals are given from the CPU
30. The data read by the head 46 is fed to the CPU 30 included in the main unit 12 via the I/O interface 40 to which a first RAM 48 and a second RAM 50 are connected. To these first and second _ g _ ~271845 RAMs 48 and 50, under the control of CPU 30 of the main unit 12, various data, read respectively from the floppy disk 24 by the head 46 are written according to the memory map shown in Fig. 4. That is, a sound control program 24a, sound 5 source data 24b, game control program 24c and game display data 24d are written into the floppy disk 24 in advance according to the contents of the game, which are then read out and the sound control program 24a, sound source data 24b and game control program 24c are written into a fixed address 10 of the first RAM 48, while the game display data 24d is written into the second RA~ 50.
In the data input device 20, a sound source circuit 52 connected to the I/O interface 40 and to the main unit of the present invention is provided. The sound source circuit 52 15 is designed to produce the sound signal (e) on the basis, i mainly of the sound source data written in the first RAM 48 as particularly described later with reference to Fig. 3.
The sound signal from the sound source circuit 52 is ampli-fied by an audio amplifying circuit 54, and given to the RF
20 modulation circuit 36 of the main unit 12 through the adapter 16 and the connector 38. Thus, in the RF modulation circuit 36, the image signal for the game and the sound signal from the audio amplifying circuit 54 are processed to produce the usual TV signal, for example, such as the NTSC system.
Referring to the operation of the system shown in Fig. 2 ,, , - ~Z7~845 in brief, firstly the floppy disk 24 is inserted into the data input device 20. Accordingly, the disk drive 44 detects the insertion, and the detection signal is given vla the I/O
interface, adapter 16, connector 38 and I/O interface 28 to 5 the CPU 30. The CPU 30, in turn, gives the drive command to the disk drive 44 through the reverse path. Responsive to the command, the floppy disk 24 is driven by the disk drive 44. The head 46 reads the program and the data 24a - 24d as shown in Fig. 4 from the floppy disk. The read program and 10 data are stored temporarily in the RAM 32 of the main unit 12 via the CPU 30 through the same previously path. Then, by the CPU 30, the program and data stored in the RAM 32 are written into the fixed address of the respective RAM 48 and 50 of the data input device 20 as previously explained. That 15 is, at this point, the game program and data from the floppy dis~ 24 and peculiar thereto are stored in the first and second RAMs 48 and 50.
When the controller 14 is operated by the player or operator, the operation signal is given through the I/O
20 interface 28 to the CPU 30. On the basis of the signal from the controller 14 and utilizing the RAM, the data stored in the first and second RAMs 48 and 50 are processed by the CPU
30, and the CPU 30 gives to the PPU 34 the image data cor-responding to the game condition of that moment. The PPU 34 25 converts the image data into the image signal.
~271845 While, in the sound source circuit 52, on the basis of the abovementioned sound source data 24b from the first RAM
48 given through the I/O interface 40, the sound signal is produced and amplified before fed to the RF modulation cir-5 cuit 36.
The TV signal of NTSC system is outputted from the RF
modulation circuit 36, thereby a background and game characters for executing the game or scores and the like are displayed on the display screen of the TV receiver 26. Then, 10 the game characters on the display screen may be freely moved or changed by operating the controller 14.
Thus, the effect neces~ary for the game system is pro-duced by the sound source circuit 52.
Fig. 3 is a block diagram showing one embodiment in 15 accordance with the present invention. The sound source circuit 52 includes a RAM 56 as a first memory means for storing the wave-form data of a wave to be modulated, funda-mental wave. Into the RAM 56, the wave-form data of the fundamental wave such as the sine data (sin) is written from 20 the CPU 30, according to a write address WAD. The wave-form data of the fundamental wave is the 6-bit data indicating the amplitude value sampled at every timings by dividing, for example, one cycle of the sine wave into 64(T/64). Therefore, the RAM 56 includes the area of 64 by 6 bits.
As the wave form of the fundamental wave, any wave form ~Z~8~;
such as the cosine wave, triangular wave, saw-tooth wave or the like may be considered besides the sine wave.
A fundamental wave frequency data register 58 receiving a frequency data of the fundamental wave from the CPU 30 is 5 disposed, from which the data of fundamental wave frequency (~c) of 12-bit is outputted. The data from the fundamental wave frequency register 58 is given to a shift register 60 of l9-bit, for example. To the shift register 60, together with a clock signal C~, for example, of l~sec. given as the 10 shift signal from the clock source 62, the output from a frequency divider 64 dividing the clock signal into 1/8 is fed as a load signal. When the load signal is given, the 12-bit data from the fundamental wave frequency data register 58 is loaded into the shift register 60 at its lower 12 bits.
15 Simultaneously, the upper seven bits of the shift register 60 are loaded with "0". Thereafter, each bit is shifted to the left at every one clock, so that at the n-th clock, the data of fundamental wave frequency data (~c) multiplied by 2n are loaded on the shift register 60. However, since the load 20 command signal from the fre~uency divider 64 is given at every eight clocks, "n" is the value of "0 to 7".
The l9-bit data from th.e shift register 60 are given to the lower 19 bits of one input of a full adder 66. To the upper 5 bits of the full adder 66 are fed with "0", and the 25 24-bit output of a latch circuit 68 is given to the other 12'71845 input of the full adder 66. Thus, the full adder 66 is constructed as the 24-bit full adder.
The output of 24 bits of the full adder 66 is given to the latch circuit 68 having a same number of bits, to which 5 the signal instructing the latching operation is given at every one clock of the clock source 62 from an AND gate 90 to be described later. That is, a first multiplying means for multiplying the fundamental wave frequency (~c) and the modulation index (J(t)) to output the data J(t) ~c t" is 10 constructed by the shift register 60, full adder 66 and latch circuit 68. The upper six bits of the latch circuit 66 is given as a read out address RAD of the RAM 56.
Thu~, in the RAM 56 for storing the wave-form data of the fundamental wave, the wave form is converted (in the 15 embodiment sine conversion) to output the fundamental wave wave-form data, for example, sin ~c t. However, in practice, due to the latch circuit 68 forming the first multiplying means, (sin ~c t ~ J(t)) is outputted.
The circuit producing the modulation index (J (t)) will 20 be explained as follows. A RAM 70 for storing the modulation wave-form data iB disposed as a second memory means, into which the wave-form data of the modulation wave such as the sine data (sin), is written from the CPU 30 according to the write address WAD. As same as the fundamental wave-form 25 data, the modulation wave-form data is the 6-bit data indi-~Z718A~
cating the amplitude value sampled at every timings by dividing, for example, one cycle of the sine wave into 64 (T/64). Therefore, the RAM 70 includes the area of 64 by 6 bits. The modulation wave is not necessarily limited to the 5 sine wave, it may be, for example, the triangular wave, saw-tooth wave, cosine wave or the like.
For receiving the data of modulation frequency (~m) from the CPU 30, a modulation frequency data register 72 is pro-vided The 12-bit modulatiop frequency data from the register 10 72 is given to the lower 12 bits of one input of a 17-bit full adder 74, while the upper 5 bits are fed with "0". To the other input of the full adder 74, 17-bit data from the latch circuit 76 receiving the latch signal from the latch circuit 76 receiving the latch signal from the frequency 15 divider 64 are given. The added result from the full adder 74 is given to the latch circuit 76 as the 17-bit data. The upper 6 bits of the latch circuit 76 are given as the read out address RAD of the RAM 70 for storing the modulation wave-form data previously described.
Thus, in the RAM 70 for storing the modulation wave-form data, the wave form is converted (in the embodiment sine conversion) to output the modulation wave-form data, for example, sin ~m t.
A modulation amplitude data register 78 is provided to 25 receive the modulation wave amplitude data (B) representing ~2~8A5 the modulation wave amplitude in 6-bit data, from the cPu 30.
The data from the modulation amplitude data register 78 is given to a reversible counter 80. To the I/D signal indi-cating the increment or decrement is given from the CPU 30, 5 and the count input from a programmable frequency divider 82 is applied. The programmable frequency divider 82 divides the clock from a 1 msec. clock source 84 by a suitable fre-quency division ratio given from the CPU 30. Therefore, by changing the modulation amplitude data (B), frequency divi-10 sion ratio and I/D signal suitably by the CPU 30, the modu-lation envelop data (B(t)) changing its amplitude optionally from the reversible counter 80.
The modulation wave-form data (sin ~m t) converted in the RAM 70 and the modulation envelop data (B(t)) from the 15 reversible counter 80 are given as the two inputs of a multi-plier 86. The multiplier 86 multiplies the two inputs and outputs the modulation index data (J(t)) represented by the previous equation (2) as its output.
The modulation index data (J(t)) is given to an 8-bit 20 shift register 88. To the shift register 88, the 1 ~sec.
clock from the clock oscillator 62 is given as the right ~hifting clock, and the signal from the frequency divider 64 is fed as the load signal. The least significant bit of the shift register 88 is given to one input of the AND gate 90 25 previously described and the 1 Psec. clock is given to the lZ7~8~
other input thereof. The output of the AND gate 90 is given as the latch command to the latch circuit 68 as heretofore described. That is, when the significant bit of the shift register 88 is "1", "1" is outputted from the AND gate 5 90 in response to the clock, thus the latch circuit 68 is operated to latch.
A fundamental wave amplitude data register 92 receiving the amplitude data (A) of the fundamental wave from the CPU
30 $s provided. The amplitude data (a) represented the 10 fundamental wave amplitude in 6-bit data which is given to a reversible counter 94. The reversible counter 94, as same as the previous reversible counter 80 receives the output of a programmable frequency divider 98 receiving the clock from a 1 msec. clock source 96 as its count input, and from the CPU
15 30, the I/D signal commanding the increment or decrement is given thereto. A suitable frequency division ratio is set in the programmable frequency divider 98 from the CPU 30. From the reversible counter 94, the fundamental wave envelope data (A(t)) changing its amplitude with time, as same as the 20 previous modulation envelop data, is outputted.
The 6-bit fundamental wave envelop data from the rever-sible counter 94 is given to one input of a comparator 102.
To the other input of the comparator 102, 6-bit output of a counter 100 incremented at every 0.5 ~sec. is given. The 25 comparator 102 outputs the pulse signal which becomes at a 127~845 high level when the data from the reversible counter 94, i.e., or the fundamental envelop data (A(t)) is larger or same as the data from the counter 100, and at a low level when the data from the counter 100 is larger inversely.
The pulse output from the comparator 102 is commonly given to one input of respective AND gates 104a - 104g. To each other input of these AND gateslO4a - 104g, the data of bit corresponding thereto from the abovementioned RAM 56 is given. The AND gates 104a - 104g give the output of the RAM
10 56 to a D/A converter 106 when the output from the comparator 102 is at a high level, that is, the data of the reversible counter 94 is larger or same as the data of the counter 100.
Thus, by the AND gates 104a - 104g, the signal "sin J(t) w t" given from the RAM 56 is pulse-width modulated.
Now, description of the operation of the embodiment of Fig. 3 is made. In the embodiment, a final sound signal is obtained from the D/A converter 106, which is represented by the equation (1) previously described. The fundamental wave envelop (A(t)) is given from the reversible counter 94, the 20modulation index (J(t)) is given from the multiplier 86. The fundamental wave frequency data (~c t) is obtained from the ~hift register 60. From the latch circuit 68, as described above, the data "J(t) ' ~c t" is outputted, thereby the read out address of the RAM 56 is determined and, thus from which 2sthe signal "sin J(t) ~ ~c t" is outputted. Then, the lZ7i845 pulse-width modulation is performed by the AND gates 104a -104g, the final sound signal (e) represented by the equation (1) described above is obtained.
More specifically, in the shift register 60 associated S with the fundamental wave, the fundamental wave frequency data (~c) is loaded to its lower 12 bits and the "0" is loaded to its upper 5 bits by the load signal from the frequency divider 64, and shifting to the left repeatedly at every 1 ~sec. clock from the clock generator 62. That is, in 10 the shift register 60, the fundamental wave frequency data ~c) is multiplied by 2, 21, ---27 at every rising edge of clock. While, the latch signal from the AND gate 90 is outputted at each falling edge of clock in accordance with the content of theleast significant bit of the shift register 15 88, "0" or "1".
The fundamental wave frequency data (~c) is loaded to the shift register 60 at the rising edge of the first clock CL. If theleast significant bit of the shift register 88 is "1" at the falling edge of the first clock, the data is 20 latched by the latch circuit 68. Then the left shift is effected in the shift register 60 at the rising edge of the second clock, thus the least significant bit of the shift register 60 is turned to "0" and the data (~c) previously loaded is doubled. At the same time, the shift register 88 25 is shifted to right and the second last bit data is sent to 127184~;
the least significant bit. The doubled data of the shift register 60 is latched by the latch circuit 68 in response to latch signal from the A~D gate 90 outputted at the falling edge of the second clock in accordance with 5 "1" of theleast significant bit of the shift register 88.
The upper 6 bits of the latch circuit 68 are utilized as the read out address of the RAM 56. If the content of the latch circuit 68 is "000 ---" at the first state, "J(t) ~ ct'' is latched at the falling edge of the 8-th clock. Thus, 1~ the read out address of the RAM 56 is changed by "1" at every 8 ~sec./2 or about 4 ~sec. at maximum.
The modulation frequency data (~m) is changed in such as ~ m' 2Wm, 3~m' ---by the full adder 74 at every 8 ~sec. in the latch circuit 76, whose upper 6 bits are used as the read out 15 address of the RAM 70. Therefore, the changing amount of the upper 6 bits of the latch circuit 76 (read out address of RAM 70 for storing the modulation wave-form data) serves as the modulation frequency data (~m t) which determines the modulation wave changing period, i.e., vibrato period. The 20 vibrato period becomes larger when the changing amount (~ ~m t) of the latch circuit 76 is smaller.
The sine wave data ~sin ~m t) converted by the modula-tion frequency data changing in such a manner, is outputted from the RAM 70 for storing the modulation wave-form data.
The modulation wave envelop data (B(t) is obtained by the modulation amplitude data register 78 and the reversiDle counter 80. Therefore, the modulation index (J(t) given in the equation (2) previously described is obtained from the multiplier 86.
On the other hand, as is shown in Fig. 5A, the sine wave component (sin J(t) ~ ~c t) is outputted from the RAM 56 for storing the fundamental wave-form data. And as is shown in Fig. 5B, from the comparator 102, the pulse signal is out-putted according to the comparison of the two counters 94 and 10 100. The output from the RAM 56 shown in Fig. 5A is gated by AND gates 104a - 104f with the pulse signal shown in Fig. 5B, and from the D/A converter 106! the sound signal (e) having the wave form shown in Fig. 5C is obtained. The sound signal i5 then turned into the integrated wave form as is shown in 15 Fig. 5D,. and represented in the following equation by pass-ing through the audio amplitude circuit 54 (Fig. 2).
e = A sin ~,B (n) (C + sin ~mn) ~c + ~c~ (3) In the above equation (3), if the modulation frequency data (~m) is "O", sin ~mt = O, thus the eauation (3) may be 20 deformed into the following equation (4), e = A sin ~{B(n)C ~c + ~c}' (4) By setting the modulation envelop as the simple increasing or decreasing function in this condition as is shown in Fig. 6A, the "sweep sound" increasing or decreasing 25 the sound signal frequency or the sound pitch continuously ~27~84~ii may be produced as is shown in Fig. 6B.
In the previous equation (3), if the constant C = 0, the equation may be deformed as following equation (5).
e A sin { B (n) ( m ) c c Thus, as is shown in Fig. 7A, the modulation inde~ J(t) changes to the positive and negative directions about "0".
Accordingly, as is shown in Fig. 7B, the sound signal obtained changes its frequency delicately at fm = wm/2 t about the frequency of fc = wc/2~l showing a so-called vibrato 10 effect.
~ ow, by determining both the constant C and the modula-tion frequency data (wm) in the aforementioned equation (l) at the vaLue other than "0", and setting the modulation envelop data (B(t)) as the simple increasing or decreasing 15 function, the modulation indexes of Fig. 6A and Fig. 7A tend to be synthesized. Thus, in this case, as is shown in Fig.
8B, a very peculiar sound signal vibrating and changing its center frequency is obtained as the sound signal , which is impossible to produce by the prior art.
Fig. 9 is' a block diagram showing a major portion of another embodiment in accordance with the present invention.
This embodiment is believe to be the modification of the circuit portion comprising the circuit components 56, 92 through 102, 104a - 104g and 106. A ROM 156 for storing the 25 wave-form data is provided. The ROM 156 corresponds to the ~2718A5 RAM 56 in the embodiment of Fig. 3, for example, an address having 64 by 6 bits is included, in which, one cycle of the data indicating the sine-wave wave form, for example, or the wave-form component data is written into respective address 5 in advance as 6-bit data representing the amplitude value sampled at every timings when one cycle is divided into 64.
As the wave-form data, as same as the previous embodi-ment, besides such sine wave, any wave form, such as a cosine wave, triangular wave, saw-tooth wave or the like may be used 10 responcive to the necessary sound.
The ROM ]56 for storing the wave-form data is addressed in sequence by an addressing circuit 168 including an address counter. The addressing circuit 168 corresponds to the latch circuit 68 in the previous embodiment, to which the clock 15 having the frequency of, for example, 50 KHz from a clock source 110 is given. Therefore, the address in the address-ing circuit 168 is incremented or decremented at every 0.02m sec. (= 1/50 X 103). Responsive to such successive address-ing by the addressing circuit 168, the wave-form data is read 20 out in sequence from the ROM 156 as the 6-bit data. The outputs of the respective bits of the ROM 156 represent the sine-wave form data sin ~c as a whole. The frequency of the wave-form component read out in such a manner is 0.781 KHz (=50 KHz/64) in the embodiment.
In the embodiment of Fig. 3, the AND gates 104a - 104g " ' `~' lZ7~84~i are utilized to activate the output of the D/A converter 106 responsive to the time-width signal, that is, the pulse signal from the comparator 102. On the contrary, in the embodiment of Fig. 9, the DC voltage applied to the D/A
5 converter 106 is turned on or of responsive to the output of the comparator 102. Thus in the embodiment, the respective bit outputs of the ROM 156 are given to the D/A converter 106 as is, and the pulse signal from the comparator 102 is given to the DC power supply 112. The DC power supply 112 applies 10 the DC voltage to the D/A converter 106 when the pulse signal received is at a high level, and turns off the DC voltage when at a low level. Thus, for example, the sine wave sound signal (e) is obtained from a smoothing circuit 114 as same as the previous embodiment, even by turning the DC voltage 15 112 on and off responsive to the output from the comparator 102.
Fig. 10 is a block diagram showing a major portion of a further embodiment in accordance with the present invention.
In the embodiment, the respective bit outputs of the ROM 156 20 are given to the D/A converter 106 as is, the output of which is given to the input of an analog switch 116. To the analog switch 116, the time-width signal or the pulse signal is given from the comparator 102. Therefore, the analog switch 116 gives the analog output from the D/A converter 106 25 to the smoothing circuit 114 responsive to the pulse signal ~z7~845 received. That is, in the embodiment, the analog switch 116 activates to the output of the D/A converter 106 responsive to the pulse signal from the comparator 102.
In the embodiments of Figs. 9 and 10, the frequency of 5 the clock source 110 and thus the frequency of the sound signal obtained from the smoothing circuit 114 has been described as the fixed frequency. Such frequency, however, may be changed suitably according to the embodiment of Fig. 3 previously described responsive to the necessary sound pitch.
Fig 11 is bloc~ diagram showing another configuration 'I .
for changing such frequency. In the embodiment, the clock source 110 includes a 50 MHZ oscillator llOa and a program-mable frequency divider llOb receiving the output therefrom.
~rom the CPU 30 (Fig. 2), a suitable frequency division ratio 15 is set in the programmable frequency divider llOb according to the necessary sound pitch, Corresponding to the frequency division ratio set, the 50 MHz signal from the oscillator llOa is divided and given to the addressing cir-cuit 168. The addressing circuit 168, therefore, selects the 20 address of the ROM 156 in sequence at the speed responsive to the frequency division ratio set in the programmable fre-quency divider llOb. Therefore, the wave-form component read out from the ROM 156 or the sound signal frequency (sound pitch1 obtained from the smoothing circuit 114 may be 25 changed.
127~84~
It will be appreciated that, as same as the embodiment of Fig. 3, a memory means capable of read out or read in such as a RAM may be used as the ROM 156 for storing wave-form data in the embodiments of Figs. 9 and 10.
In the above embodiment, the floppy disk 24 (Fig. 1) was used as a sound source data setting means, for which, how-ever, another memory means such as a ROM cartridge may be used, or instead of such exchangeable floppy disk or ROM
cartridge, a memory means set in the inner ROM fixedly may be 10 used.
Further, in the embodiment described above, circuits which are respectively discrete are interconnected and used, however, it will be appreciated that the software processing by one or two or more CPU is possible except the processing 15 of the D/A converter 106.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same i5 by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the 20 present invention being limited only by the terms of the appended claims.
Fig. 9 is a block diagram showing a major portion of 5 another embodiment in accordance with the present invention.
Fig. 10 is a block diagram showing a major portion o~ a further embodiment in accordance with the present invention.
Fig. ll is a block diagram showing a major portion of the other embodiment in accordance with the present inven-10 tion.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. l is a schematic construction view showing oneexample of a video game system to which the present invention may be applied. In the following, the case where the present 15 invention is applied to a video game system will be explain-ed. It will be appreciated, however, that the present invention may be used as a sound source apparatus for all other electronic equipments.
A commercial power source is applied through an AC
20 adapter, not shown, to a main unit 12 of the game machine.
Two controllers 14 are connected through to the main unit 12 the suitable connecting cables. To the main unit 12 there is connected an adapter 16 to which a data input device 20 is connected. An inserting mouth 22 for inserting a floppy disk i2~84~
24 is formed on the data input device 20.
AS the main unit 12, for example, a "family computer"
(trademark) manufactured and marketed by the assignee of the present invention may be utilized.
Responsive to the data written into the floppy disk 24 in advance, various data for the game are given to the main unit 12 from the data input device 20 via the adapter 16.
Thus, from the main unit 12, a TV signal for executing the game corresponding to the content of the floppy disk 24 is 10 outputted to an antenna terminal, not shown, of a TV receiver 26.
In such a video game system, the operator can enjoy the video game by operating the controller 14 to control the game character on the display screen of the TV receiver 26 15 optionally.
Fig. 2 is a block diagram showing a system configuration of Fig. l. As previously described, to the main unit 12 there is connected the controller 14, the signal from which is given to a CPU 30 through the I/O interface 28. To the 20 CPU 30, a RAM 32 for storing various controlling data as well as a PPU 34 receiving the image data from the CPU 30 are connected. As the CPU 30, for example, a microprocessor such as an integrated circuit "2A02" by Nintendo may be used. The PPU 34 is designed to produce the image signal for the game 25 on the basis of the image data from the CPU 30. As the PPU
~27~845 34, for example, an integrated circuit "2c03'~ by Nintendo may be utilized.
The image signal from the PPu 34 is converted into a TV signal of NTSC system, for example, by an RF
modulation circuit 36, and fed to the antenna terminal of the TV receiver 26 via a coaxial cable.
On the main unit 12, a connector 38 for connecting the adapter 16 is provided. Therefore, the CPU
30, through the connector 38, gives and receives various data to and from the adapter 16 and thus the data input device 20 via the I/O interface 28.
The data input device 20 incudes an I/O interface 40 connected to the adapter 16. On the data input device 20, associating with the inserting mouth 22 (Fig. 1) of the floppy disk 24, there is provided a disk dri~e 44 and a head 46 associating therewith. From the disk drive 44, the insertion detecting signal indicating an insertion of the floppy disk 24, is given through the I/O interface 40 to the CPU 30 incorporated in the main unit 12. To the disk drive 44, various command signals are given from the CPU
30. The data read by the head 46 is fed to the CPU 30 included in the main unit 12 via the I/O interface 40 to which a first RAM 48 and a second RAM 50 are connected. To these first and second _ g _ ~271845 RAMs 48 and 50, under the control of CPU 30 of the main unit 12, various data, read respectively from the floppy disk 24 by the head 46 are written according to the memory map shown in Fig. 4. That is, a sound control program 24a, sound 5 source data 24b, game control program 24c and game display data 24d are written into the floppy disk 24 in advance according to the contents of the game, which are then read out and the sound control program 24a, sound source data 24b and game control program 24c are written into a fixed address 10 of the first RAM 48, while the game display data 24d is written into the second RA~ 50.
In the data input device 20, a sound source circuit 52 connected to the I/O interface 40 and to the main unit of the present invention is provided. The sound source circuit 52 15 is designed to produce the sound signal (e) on the basis, i mainly of the sound source data written in the first RAM 48 as particularly described later with reference to Fig. 3.
The sound signal from the sound source circuit 52 is ampli-fied by an audio amplifying circuit 54, and given to the RF
20 modulation circuit 36 of the main unit 12 through the adapter 16 and the connector 38. Thus, in the RF modulation circuit 36, the image signal for the game and the sound signal from the audio amplifying circuit 54 are processed to produce the usual TV signal, for example, such as the NTSC system.
Referring to the operation of the system shown in Fig. 2 ,, , - ~Z7~845 in brief, firstly the floppy disk 24 is inserted into the data input device 20. Accordingly, the disk drive 44 detects the insertion, and the detection signal is given vla the I/O
interface, adapter 16, connector 38 and I/O interface 28 to 5 the CPU 30. The CPU 30, in turn, gives the drive command to the disk drive 44 through the reverse path. Responsive to the command, the floppy disk 24 is driven by the disk drive 44. The head 46 reads the program and the data 24a - 24d as shown in Fig. 4 from the floppy disk. The read program and 10 data are stored temporarily in the RAM 32 of the main unit 12 via the CPU 30 through the same previously path. Then, by the CPU 30, the program and data stored in the RAM 32 are written into the fixed address of the respective RAM 48 and 50 of the data input device 20 as previously explained. That 15 is, at this point, the game program and data from the floppy dis~ 24 and peculiar thereto are stored in the first and second RAMs 48 and 50.
When the controller 14 is operated by the player or operator, the operation signal is given through the I/O
20 interface 28 to the CPU 30. On the basis of the signal from the controller 14 and utilizing the RAM, the data stored in the first and second RAMs 48 and 50 are processed by the CPU
30, and the CPU 30 gives to the PPU 34 the image data cor-responding to the game condition of that moment. The PPU 34 25 converts the image data into the image signal.
~271845 While, in the sound source circuit 52, on the basis of the abovementioned sound source data 24b from the first RAM
48 given through the I/O interface 40, the sound signal is produced and amplified before fed to the RF modulation cir-5 cuit 36.
The TV signal of NTSC system is outputted from the RF
modulation circuit 36, thereby a background and game characters for executing the game or scores and the like are displayed on the display screen of the TV receiver 26. Then, 10 the game characters on the display screen may be freely moved or changed by operating the controller 14.
Thus, the effect neces~ary for the game system is pro-duced by the sound source circuit 52.
Fig. 3 is a block diagram showing one embodiment in 15 accordance with the present invention. The sound source circuit 52 includes a RAM 56 as a first memory means for storing the wave-form data of a wave to be modulated, funda-mental wave. Into the RAM 56, the wave-form data of the fundamental wave such as the sine data (sin) is written from 20 the CPU 30, according to a write address WAD. The wave-form data of the fundamental wave is the 6-bit data indicating the amplitude value sampled at every timings by dividing, for example, one cycle of the sine wave into 64(T/64). Therefore, the RAM 56 includes the area of 64 by 6 bits.
As the wave form of the fundamental wave, any wave form ~Z~8~;
such as the cosine wave, triangular wave, saw-tooth wave or the like may be considered besides the sine wave.
A fundamental wave frequency data register 58 receiving a frequency data of the fundamental wave from the CPU 30 is 5 disposed, from which the data of fundamental wave frequency (~c) of 12-bit is outputted. The data from the fundamental wave frequency register 58 is given to a shift register 60 of l9-bit, for example. To the shift register 60, together with a clock signal C~, for example, of l~sec. given as the 10 shift signal from the clock source 62, the output from a frequency divider 64 dividing the clock signal into 1/8 is fed as a load signal. When the load signal is given, the 12-bit data from the fundamental wave frequency data register 58 is loaded into the shift register 60 at its lower 12 bits.
15 Simultaneously, the upper seven bits of the shift register 60 are loaded with "0". Thereafter, each bit is shifted to the left at every one clock, so that at the n-th clock, the data of fundamental wave frequency data (~c) multiplied by 2n are loaded on the shift register 60. However, since the load 20 command signal from the fre~uency divider 64 is given at every eight clocks, "n" is the value of "0 to 7".
The l9-bit data from th.e shift register 60 are given to the lower 19 bits of one input of a full adder 66. To the upper 5 bits of the full adder 66 are fed with "0", and the 25 24-bit output of a latch circuit 68 is given to the other 12'71845 input of the full adder 66. Thus, the full adder 66 is constructed as the 24-bit full adder.
The output of 24 bits of the full adder 66 is given to the latch circuit 68 having a same number of bits, to which 5 the signal instructing the latching operation is given at every one clock of the clock source 62 from an AND gate 90 to be described later. That is, a first multiplying means for multiplying the fundamental wave frequency (~c) and the modulation index (J(t)) to output the data J(t) ~c t" is 10 constructed by the shift register 60, full adder 66 and latch circuit 68. The upper six bits of the latch circuit 66 is given as a read out address RAD of the RAM 56.
Thu~, in the RAM 56 for storing the wave-form data of the fundamental wave, the wave form is converted (in the 15 embodiment sine conversion) to output the fundamental wave wave-form data, for example, sin ~c t. However, in practice, due to the latch circuit 68 forming the first multiplying means, (sin ~c t ~ J(t)) is outputted.
The circuit producing the modulation index (J (t)) will 20 be explained as follows. A RAM 70 for storing the modulation wave-form data iB disposed as a second memory means, into which the wave-form data of the modulation wave such as the sine data (sin), is written from the CPU 30 according to the write address WAD. As same as the fundamental wave-form 25 data, the modulation wave-form data is the 6-bit data indi-~Z718A~
cating the amplitude value sampled at every timings by dividing, for example, one cycle of the sine wave into 64 (T/64). Therefore, the RAM 70 includes the area of 64 by 6 bits. The modulation wave is not necessarily limited to the 5 sine wave, it may be, for example, the triangular wave, saw-tooth wave, cosine wave or the like.
For receiving the data of modulation frequency (~m) from the CPU 30, a modulation frequency data register 72 is pro-vided The 12-bit modulatiop frequency data from the register 10 72 is given to the lower 12 bits of one input of a 17-bit full adder 74, while the upper 5 bits are fed with "0". To the other input of the full adder 74, 17-bit data from the latch circuit 76 receiving the latch signal from the latch circuit 76 receiving the latch signal from the frequency 15 divider 64 are given. The added result from the full adder 74 is given to the latch circuit 76 as the 17-bit data. The upper 6 bits of the latch circuit 76 are given as the read out address RAD of the RAM 70 for storing the modulation wave-form data previously described.
Thus, in the RAM 70 for storing the modulation wave-form data, the wave form is converted (in the embodiment sine conversion) to output the modulation wave-form data, for example, sin ~m t.
A modulation amplitude data register 78 is provided to 25 receive the modulation wave amplitude data (B) representing ~2~8A5 the modulation wave amplitude in 6-bit data, from the cPu 30.
The data from the modulation amplitude data register 78 is given to a reversible counter 80. To the I/D signal indi-cating the increment or decrement is given from the CPU 30, 5 and the count input from a programmable frequency divider 82 is applied. The programmable frequency divider 82 divides the clock from a 1 msec. clock source 84 by a suitable fre-quency division ratio given from the CPU 30. Therefore, by changing the modulation amplitude data (B), frequency divi-10 sion ratio and I/D signal suitably by the CPU 30, the modu-lation envelop data (B(t)) changing its amplitude optionally from the reversible counter 80.
The modulation wave-form data (sin ~m t) converted in the RAM 70 and the modulation envelop data (B(t)) from the 15 reversible counter 80 are given as the two inputs of a multi-plier 86. The multiplier 86 multiplies the two inputs and outputs the modulation index data (J(t)) represented by the previous equation (2) as its output.
The modulation index data (J(t)) is given to an 8-bit 20 shift register 88. To the shift register 88, the 1 ~sec.
clock from the clock oscillator 62 is given as the right ~hifting clock, and the signal from the frequency divider 64 is fed as the load signal. The least significant bit of the shift register 88 is given to one input of the AND gate 90 25 previously described and the 1 Psec. clock is given to the lZ7~8~
other input thereof. The output of the AND gate 90 is given as the latch command to the latch circuit 68 as heretofore described. That is, when the significant bit of the shift register 88 is "1", "1" is outputted from the AND gate 5 90 in response to the clock, thus the latch circuit 68 is operated to latch.
A fundamental wave amplitude data register 92 receiving the amplitude data (A) of the fundamental wave from the CPU
30 $s provided. The amplitude data (a) represented the 10 fundamental wave amplitude in 6-bit data which is given to a reversible counter 94. The reversible counter 94, as same as the previous reversible counter 80 receives the output of a programmable frequency divider 98 receiving the clock from a 1 msec. clock source 96 as its count input, and from the CPU
15 30, the I/D signal commanding the increment or decrement is given thereto. A suitable frequency division ratio is set in the programmable frequency divider 98 from the CPU 30. From the reversible counter 94, the fundamental wave envelope data (A(t)) changing its amplitude with time, as same as the 20 previous modulation envelop data, is outputted.
The 6-bit fundamental wave envelop data from the rever-sible counter 94 is given to one input of a comparator 102.
To the other input of the comparator 102, 6-bit output of a counter 100 incremented at every 0.5 ~sec. is given. The 25 comparator 102 outputs the pulse signal which becomes at a 127~845 high level when the data from the reversible counter 94, i.e., or the fundamental envelop data (A(t)) is larger or same as the data from the counter 100, and at a low level when the data from the counter 100 is larger inversely.
The pulse output from the comparator 102 is commonly given to one input of respective AND gates 104a - 104g. To each other input of these AND gateslO4a - 104g, the data of bit corresponding thereto from the abovementioned RAM 56 is given. The AND gates 104a - 104g give the output of the RAM
10 56 to a D/A converter 106 when the output from the comparator 102 is at a high level, that is, the data of the reversible counter 94 is larger or same as the data of the counter 100.
Thus, by the AND gates 104a - 104g, the signal "sin J(t) w t" given from the RAM 56 is pulse-width modulated.
Now, description of the operation of the embodiment of Fig. 3 is made. In the embodiment, a final sound signal is obtained from the D/A converter 106, which is represented by the equation (1) previously described. The fundamental wave envelop (A(t)) is given from the reversible counter 94, the 20modulation index (J(t)) is given from the multiplier 86. The fundamental wave frequency data (~c t) is obtained from the ~hift register 60. From the latch circuit 68, as described above, the data "J(t) ' ~c t" is outputted, thereby the read out address of the RAM 56 is determined and, thus from which 2sthe signal "sin J(t) ~ ~c t" is outputted. Then, the lZ7i845 pulse-width modulation is performed by the AND gates 104a -104g, the final sound signal (e) represented by the equation (1) described above is obtained.
More specifically, in the shift register 60 associated S with the fundamental wave, the fundamental wave frequency data (~c) is loaded to its lower 12 bits and the "0" is loaded to its upper 5 bits by the load signal from the frequency divider 64, and shifting to the left repeatedly at every 1 ~sec. clock from the clock generator 62. That is, in 10 the shift register 60, the fundamental wave frequency data ~c) is multiplied by 2, 21, ---27 at every rising edge of clock. While, the latch signal from the AND gate 90 is outputted at each falling edge of clock in accordance with the content of theleast significant bit of the shift register 15 88, "0" or "1".
The fundamental wave frequency data (~c) is loaded to the shift register 60 at the rising edge of the first clock CL. If theleast significant bit of the shift register 88 is "1" at the falling edge of the first clock, the data is 20 latched by the latch circuit 68. Then the left shift is effected in the shift register 60 at the rising edge of the second clock, thus the least significant bit of the shift register 60 is turned to "0" and the data (~c) previously loaded is doubled. At the same time, the shift register 88 25 is shifted to right and the second last bit data is sent to 127184~;
the least significant bit. The doubled data of the shift register 60 is latched by the latch circuit 68 in response to latch signal from the A~D gate 90 outputted at the falling edge of the second clock in accordance with 5 "1" of theleast significant bit of the shift register 88.
The upper 6 bits of the latch circuit 68 are utilized as the read out address of the RAM 56. If the content of the latch circuit 68 is "000 ---" at the first state, "J(t) ~ ct'' is latched at the falling edge of the 8-th clock. Thus, 1~ the read out address of the RAM 56 is changed by "1" at every 8 ~sec./2 or about 4 ~sec. at maximum.
The modulation frequency data (~m) is changed in such as ~ m' 2Wm, 3~m' ---by the full adder 74 at every 8 ~sec. in the latch circuit 76, whose upper 6 bits are used as the read out 15 address of the RAM 70. Therefore, the changing amount of the upper 6 bits of the latch circuit 76 (read out address of RAM 70 for storing the modulation wave-form data) serves as the modulation frequency data (~m t) which determines the modulation wave changing period, i.e., vibrato period. The 20 vibrato period becomes larger when the changing amount (~ ~m t) of the latch circuit 76 is smaller.
The sine wave data ~sin ~m t) converted by the modula-tion frequency data changing in such a manner, is outputted from the RAM 70 for storing the modulation wave-form data.
The modulation wave envelop data (B(t) is obtained by the modulation amplitude data register 78 and the reversiDle counter 80. Therefore, the modulation index (J(t) given in the equation (2) previously described is obtained from the multiplier 86.
On the other hand, as is shown in Fig. 5A, the sine wave component (sin J(t) ~ ~c t) is outputted from the RAM 56 for storing the fundamental wave-form data. And as is shown in Fig. 5B, from the comparator 102, the pulse signal is out-putted according to the comparison of the two counters 94 and 10 100. The output from the RAM 56 shown in Fig. 5A is gated by AND gates 104a - 104f with the pulse signal shown in Fig. 5B, and from the D/A converter 106! the sound signal (e) having the wave form shown in Fig. 5C is obtained. The sound signal i5 then turned into the integrated wave form as is shown in 15 Fig. 5D,. and represented in the following equation by pass-ing through the audio amplitude circuit 54 (Fig. 2).
e = A sin ~,B (n) (C + sin ~mn) ~c + ~c~ (3) In the above equation (3), if the modulation frequency data (~m) is "O", sin ~mt = O, thus the eauation (3) may be 20 deformed into the following equation (4), e = A sin ~{B(n)C ~c + ~c}' (4) By setting the modulation envelop as the simple increasing or decreasing function in this condition as is shown in Fig. 6A, the "sweep sound" increasing or decreasing 25 the sound signal frequency or the sound pitch continuously ~27~84~ii may be produced as is shown in Fig. 6B.
In the previous equation (3), if the constant C = 0, the equation may be deformed as following equation (5).
e A sin { B (n) ( m ) c c Thus, as is shown in Fig. 7A, the modulation inde~ J(t) changes to the positive and negative directions about "0".
Accordingly, as is shown in Fig. 7B, the sound signal obtained changes its frequency delicately at fm = wm/2 t about the frequency of fc = wc/2~l showing a so-called vibrato 10 effect.
~ ow, by determining both the constant C and the modula-tion frequency data (wm) in the aforementioned equation (l) at the vaLue other than "0", and setting the modulation envelop data (B(t)) as the simple increasing or decreasing 15 function, the modulation indexes of Fig. 6A and Fig. 7A tend to be synthesized. Thus, in this case, as is shown in Fig.
8B, a very peculiar sound signal vibrating and changing its center frequency is obtained as the sound signal , which is impossible to produce by the prior art.
Fig. 9 is' a block diagram showing a major portion of another embodiment in accordance with the present invention.
This embodiment is believe to be the modification of the circuit portion comprising the circuit components 56, 92 through 102, 104a - 104g and 106. A ROM 156 for storing the 25 wave-form data is provided. The ROM 156 corresponds to the ~2718A5 RAM 56 in the embodiment of Fig. 3, for example, an address having 64 by 6 bits is included, in which, one cycle of the data indicating the sine-wave wave form, for example, or the wave-form component data is written into respective address 5 in advance as 6-bit data representing the amplitude value sampled at every timings when one cycle is divided into 64.
As the wave-form data, as same as the previous embodi-ment, besides such sine wave, any wave form, such as a cosine wave, triangular wave, saw-tooth wave or the like may be used 10 responcive to the necessary sound.
The ROM ]56 for storing the wave-form data is addressed in sequence by an addressing circuit 168 including an address counter. The addressing circuit 168 corresponds to the latch circuit 68 in the previous embodiment, to which the clock 15 having the frequency of, for example, 50 KHz from a clock source 110 is given. Therefore, the address in the address-ing circuit 168 is incremented or decremented at every 0.02m sec. (= 1/50 X 103). Responsive to such successive address-ing by the addressing circuit 168, the wave-form data is read 20 out in sequence from the ROM 156 as the 6-bit data. The outputs of the respective bits of the ROM 156 represent the sine-wave form data sin ~c as a whole. The frequency of the wave-form component read out in such a manner is 0.781 KHz (=50 KHz/64) in the embodiment.
In the embodiment of Fig. 3, the AND gates 104a - 104g " ' `~' lZ7~84~i are utilized to activate the output of the D/A converter 106 responsive to the time-width signal, that is, the pulse signal from the comparator 102. On the contrary, in the embodiment of Fig. 9, the DC voltage applied to the D/A
5 converter 106 is turned on or of responsive to the output of the comparator 102. Thus in the embodiment, the respective bit outputs of the ROM 156 are given to the D/A converter 106 as is, and the pulse signal from the comparator 102 is given to the DC power supply 112. The DC power supply 112 applies 10 the DC voltage to the D/A converter 106 when the pulse signal received is at a high level, and turns off the DC voltage when at a low level. Thus, for example, the sine wave sound signal (e) is obtained from a smoothing circuit 114 as same as the previous embodiment, even by turning the DC voltage 15 112 on and off responsive to the output from the comparator 102.
Fig. 10 is a block diagram showing a major portion of a further embodiment in accordance with the present invention.
In the embodiment, the respective bit outputs of the ROM 156 20 are given to the D/A converter 106 as is, the output of which is given to the input of an analog switch 116. To the analog switch 116, the time-width signal or the pulse signal is given from the comparator 102. Therefore, the analog switch 116 gives the analog output from the D/A converter 106 25 to the smoothing circuit 114 responsive to the pulse signal ~z7~845 received. That is, in the embodiment, the analog switch 116 activates to the output of the D/A converter 106 responsive to the pulse signal from the comparator 102.
In the embodiments of Figs. 9 and 10, the frequency of 5 the clock source 110 and thus the frequency of the sound signal obtained from the smoothing circuit 114 has been described as the fixed frequency. Such frequency, however, may be changed suitably according to the embodiment of Fig. 3 previously described responsive to the necessary sound pitch.
Fig 11 is bloc~ diagram showing another configuration 'I .
for changing such frequency. In the embodiment, the clock source 110 includes a 50 MHZ oscillator llOa and a program-mable frequency divider llOb receiving the output therefrom.
~rom the CPU 30 (Fig. 2), a suitable frequency division ratio 15 is set in the programmable frequency divider llOb according to the necessary sound pitch, Corresponding to the frequency division ratio set, the 50 MHz signal from the oscillator llOa is divided and given to the addressing cir-cuit 168. The addressing circuit 168, therefore, selects the 20 address of the ROM 156 in sequence at the speed responsive to the frequency division ratio set in the programmable fre-quency divider llOb. Therefore, the wave-form component read out from the ROM 156 or the sound signal frequency (sound pitch1 obtained from the smoothing circuit 114 may be 25 changed.
127~84~
It will be appreciated that, as same as the embodiment of Fig. 3, a memory means capable of read out or read in such as a RAM may be used as the ROM 156 for storing wave-form data in the embodiments of Figs. 9 and 10.
In the above embodiment, the floppy disk 24 (Fig. 1) was used as a sound source data setting means, for which, how-ever, another memory means such as a ROM cartridge may be used, or instead of such exchangeable floppy disk or ROM
cartridge, a memory means set in the inner ROM fixedly may be 10 used.
Further, in the embodiment described above, circuits which are respectively discrete are interconnected and used, however, it will be appreciated that the software processing by one or two or more CPU is possible except the processing 15 of the D/A converter 106.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same i5 by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the 20 present invention being limited only by the terms of the appended claims.
Claims (10)
1. A sound source apparatus of electronic equipment com-prising;
a first memory means for storing a fundamental wave wave-form data in a digital value, an operating means for operating to obtain a modulation index data (J(t)) changing with a time function on the basis of a modulation envelop data (B(t)), and a first multiplying means for multiplying a fundamental wave frequency data (.omega.c) and said modulation index data, the multiplied result of said first multiplying means is given to said first memory means as a read out address data, thereby the read out speed of said first memory means is changed, and further comprising a D/A converting means for converting the digital value read out from said first memory means into an analog signal to output a sound signal (e).
a first memory means for storing a fundamental wave wave-form data in a digital value, an operating means for operating to obtain a modulation index data (J(t)) changing with a time function on the basis of a modulation envelop data (B(t)), and a first multiplying means for multiplying a fundamental wave frequency data (.omega.c) and said modulation index data, the multiplied result of said first multiplying means is given to said first memory means as a read out address data, thereby the read out speed of said first memory means is changed, and further comprising a D/A converting means for converting the digital value read out from said first memory means into an analog signal to output a sound signal (e).
2. A sound source apparatus of electronic equipment in accordance with claim 1, wherein said operating means includes a second multiplying means for multiplying to obtain said modulation index data (J(t)) on the basis of the modula-tion wave wave-form data having the frequency (.omega.m) and said modulation envelop data.
3. A sound source apparatus of electronic equipment in accordance with claim 2, wherein said operating means includes a second memory means for storing said modulation wave wave-form data in the digital value, said modulation wave wave-form data is read out from said second memory means on the basis of said modulation frequency data and given to said second multiplying means.
4. A sound source apparatus of electronic equipment in accordance with claim 1, which further comprises means for providing the fundamental wave envelop data (A(t)), and a changing means for changing the output time from said first memory means on the basis of said fundamental envelop data (A(t), an amplitude of the output sound signal from said D/A
converting means is changed responsive to said output time.
converting means is changed responsive to said output time.
5. A sound source apparatus of electronic equipment in accordance with claim 4, wherein said changing means includes means for outputting a pulse signal having duration cor-related with and on the basis of said fundamental wave envelop data, and a gate means for gating the output of said first memory means by said pulse signal.
6. A sound source apparatus of electronic equipment in accordance with claim 1, which further comprises means for providing the fundamental wave envelop data (A(t)), means for outputting the time-width signal having the time width cor-responding to said fundamental wave amplitude, and an activa-ting means for activating the output of said D/A converting means responsive to said time-width signal.
7. A sound source apparatus of electronic equipment in accordance with claim 6, wherein said activating means includes means for gating the fundamental wave wave-form data of said first memory means by said time-width signal.
8. A sound source apparatus of electronic equipment in accordance with claim 7, which further comprises a power supply for applying a DC voltage to said D/A converting means, wherein said activating means includes means for turning the output from said power supply on and off by said time-width signal.
9. A sound source apparatus of electronic equipment in accordance with claim 7, wherein said activating means includes an analog switch which receives the output of said D/A
converting means, and is controlled by said time-width signal.
converting means, and is controlled by said time-width signal.
10. A sound source apparatus of electronic equipment in accordance with claim 1, which further comprises a box main unit containing at least said first memory means, operating means, first multiplying means and D/A converting means, wherein means for setting said various data includes an external memory means mounted removably to said box main unit.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16637985A JPS6228479A (en) | 1985-07-26 | 1985-07-26 | Production of sheet |
| JP60172575A JPS6232497A (en) | 1985-08-05 | 1985-08-05 | Sound source unit for electronic appliance |
| JP172575/1985 | 1985-08-05 | ||
| JP166379/1985 | 1985-10-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1271845A true CA1271845A (en) | 1990-07-17 |
Family
ID=26490775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000515352A Expired - Fee Related CA1271845A (en) | 1985-07-26 | 1986-08-05 | Electronic sound synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1271845A (en) |
-
1986
- 1986-08-05 CA CA000515352A patent/CA1271845A/en not_active Expired - Fee Related
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| MKLA | Lapsed |