JPS6231892A - Bit map memory operation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention is a bitmap memory manipulation circuit that moves bit data in a rectangular area on a bitmap memory word by word, and moves bit data in a specified rectangular area for each word operation. Word address and purpose of the source rectangular area to be incremented? An operation circuit is provided that switches the word address of the il area with a read/write command, aligns the read word data with the destination word of the target area by a shift means, and writes the data while masking the write-inhibited area. do.

[Industrial application field]

The present invention relates to a bitmap memory manipulation circuit.

For display devices that output based on bitmap memory,
In order to move or copy data on the display screen, data reading/writing operations are performed on the bitmap memory.

Operations such as moving and copying are performed in units of rectangular areas, and the position, length, etc. of the source (hereinafter referred to as source) rectangular area,
Parameters such as the position of a rectangular area to which to move (hereinafter referred to as destination) are specified.

If this rectangular area data is successively read/written bit by bit, the number of operations, that is, the processing time becomes longer.If software is used to read/write data in words or bytes, word alignment processing between the source and destination will be required. Therefore, there is still a problem that the processing time becomes long.

Therefore, there is a need for a bitmap memory manipulation circuit that solves the above problems.

[Conventional technology]

An example of bitmap memory manipulation processing using software is shown below.

FIG. 3 (Al is a block diagram of the display device, 30 is a microprocessor (MPU) capable of word processing, 31 is an interface for transmitting and receiving display data etc. from the host computer, 32 is a memory for storing programs, data, etc.) , 33 is a bitmap memory, which is shown corresponding to the display screen, and 34 is a multiplexer, which is a bitmap memory 3.
3 is a drive unit that repeatedly reads the bitmap memory 33 and drives a cathode ray tube (CRT) display unit 36.

On the display screen, a word is formed in units of 16 dots in the X direction, and the word address of the bit map memory 33 is made to correspond to the word in the X-Y direction from the home position [0,0] on the display screen. .

The operation of moving the data in the rectangular area S represented by the start address SP, lengths Lx, and Ly to the area represented by the start address DP is performed as follows. [Figure 3 [b
lRefer to operation diagram] (1) Read word 1, store in memory 3, f21
Calculate S P - D P, use the value as shift a, and perform clockwise shift operation in memory 3. (3) Write the above shift data to word 3 with the M1 part masked, then mask the M2 part to word 4. and write.

(4) Perform the above operation for each word within the rectangular area S.

[Problem that the invention seeks to solve]

As explained above, the software operation of the bitmap memory requires a large number of word operations, and especially when the rectangular area is large, there is a problem that the display of the processing result becomes slow and that it affects other processing.

In view of the above problems, an object of the present invention is to provide a bitmap memory manipulation circuit using direct memory access (DMA) on a word-by-word basis.

[Means for solving problems]

For the above purpose, the bitmap memory manipulation circuit of the present invention, as shown in the principle explanatory diagram of FIG. The first and second address counters (1, 2
) and counting means (4) for counting the number of word operations for reading and writing in the X and Y directions based on the length of the rectangular area, and counting means (4) for counting the number of word operations for reading and writing in the X and Y directions based on the length of the rectangular area; address control means (3) for causing the counting means to address within the rectangular area; and switching means (5) for switching address designation to first and second address counters, respectively, in response to read commands and write commands; A shift means (7) for aligning the word data of the rectangular area with the word data of the target area, a masking means (8) for specifying a write-prohibited area of the target area, and a read command for sending the word data of the rectangular area. An operating means (6) for reading data, shifting it by the shifting means, and writing the shifted word data together with a write command while specifying a write-protected area.

[Effect]

That is, 1st. The first word address of the source and the first word of the destination are entered in the second address counter, the first address counter is switched to read the corresponding word in the bitmap memory, and the shift means is used to transfer the word to the destination. Line up.

Then, switching to the second address counter, masking the write-inhibited area and writing.

1st. The second address counter is incremented within the designated rectangular area, and the above operation is repeated.

By using the bitmap memory operation circuit, the microprocessor (MPU) only needs to set parameters specifying the source and destination of movement, and subsequent operations are performed in DM8.

〔Example〕

The details of the present invention will be explained according to the embodiment shown in FIG.

(Explanation of Word Addresses) FIG. 2 (al) is an explanatory diagram of word addresses of a bitmap memory in which the X and Y axes each consist of 4096 bits.

In other words, word addresses are assigned every 16 bits (words) in the X direction from the origin (0, O) on the display screen, and line 2
When 56 words are completed, the next line (Y=1) is proceeded to and a consecutive number is assigned.

Such a word address is obtained by combining the upper 8 bits of the 12 bits of the X coordinate address and the 12 bits of the Y coordinate address, as shown in Figure 2(a), and the lower 4 bits of the X coordinate address are the word address. Indicates internal address.

As described above, the bitmap memory is operated in correspondence with the display screen and the bitmap/knob memory.

(Configuration) FIG. 2(b) is a block diagram of the bitmap memory operation circuit of the embodiment, in which 10 is a microprocessor (MPU), 28 is a bitmap memory equipped with a mask circuit 28a. , the bitmap memory manipulation circuit of the present invention is comprised of the following circuits.

"Address Circuit" 12 is a 12-bit register SXP-Reg that stores the X-coordinate address of the starting position SP of the source area.

13 is an address counter 5XP-Cnt in which the upper 8 bits of SXP-Reg 12 are set and counted up every time a word is processed.

14 is the Y coordinate address 12 of the starting position sp of the source area
An address counter 5YP-Cnt whose bit is set and counts up each time word processing in the X direction is completed, which together with 5XP-Cnt 13 designates the word address of the source area shown in FIG. 2 ta+, 15 is the destination. A 12-bit register DχP-Re that sets the X-coordinate address of the starting position DP of
g.

16 is an address counter DXP-Cnt to which the upper 8 bits of DXP-Reg 15 are sent, and which is counted and amplified every word processing.

17 is an address counter DYP-Cnt in which 12 bits of the address of the Y coordinate of the start position DP are set and counted up together with 5YP-Cnt 14;
Together with Cnt16, the word address of the destination is set. 18 is the register DXL-Reg in which the length LX in the X direction expressed in bits is sent. 19 is DXL-Reg.
The upper bits excluding the lower 4 bits of 18 are set (X
DXL-Cnt (direction word B-1) and counted down for each word processing.

20 is the length Ly in the Y direction expressed by the number of bits, and DY is counted down each time the processing in the X direction is completed.
L-Cnt.

21 is a multiplexer which reads 5XP-Cnt 13.5YP-C according to the read/write command sent from the main control unit 11.
Source address output of nt 14 and DXP-Cnt 1
6. DYP-Cnt 17's destination address output.

“Shift circuit” 25 and 26 are registers L-Reg and R-Reg, which set read data alternately in the order of processing words.The registers L-Reg and R-Reg 24 have a width of 2 words, and are shifted to the right or left according to a command from the shift control unit 22. It consists of a shifter that performs a quantitative shift and outputs the shift result in two words in parallel, and a multiplexer 23 that selectively outputs one word to the right or left of the shifter 24.

``Mask Data Generation Circuit'' This circuit generates write-inhibited data for writing the first word and last word of the destination in the X direction.

The bitmap memory operation circuit is composed of a bitmap memory 28, 1 word (16) data lines 100, 20 address lines 101, and control lines (not shown) such as read/write signal lines. There is.

(Operation explanation) The operation will be explained below.

(1) The microprocessor (MPU) 10 stores the parameters of the source area, that is, the X and Y addresses of the starting position SP,
, the lengths L x and L y % in the Y direction and the X and Y addresses of the starting position DP of the destination are set in the respective registers, and the main control unit 11 is activated.

(2) The main control unit 11 sets the multiplexer 21 to the source side address, that is, 5XP-Cnt 13.5YP-Cnt
14 (source side) and sends a read signal to the bitmap memory 28, the data of the first word of the source area is output to the data line 100, and this data is
- Store in Reg 25.

(3) The shift control unit 22 compares and calculates the lower 4 bits of SXP-Reg 12 and fiXP-Reg 15, and transmits the right (or left) shift command and shift amount to the shifter 2.
4, and causes the multiplexer 23 to select and output one right (or left) word.

(4) Next, the main control unit 11 outputs DXP-(:nt 16 and DYP-Cnt 17 (destination side) to the address signal line 101 by the multiplexer 21, and sends the write signal and mask data to the bitmap memory 28. The above data sent to and shifted (
(output of multiplexer 23) is written.

When the above read/write operations are completed, the main control unit 11 increments the source and destination X addresses, that is, counts up 5XP-Cnt 13 and DXP-Cnt 16, counts down DXL-Cnt 19, and Repeat read/write operations.

(5) DXL-Cnt 1 when processing the final word in the X direction
A carry signal of 5XP-Cnt 13. DXP-Cnt
16. Set initial values to DXL-Cnt 19 and 5YP-Cnt 14. DYP-Cnt 1
Step 7 and perform the word operation on the next line.

(6) DYL-Cnt every time the line is updated
20 is counted down and the money operation is completed after the carry output.

Details of the above shift operation will be explained with reference to the shift operation diagram in FIG. 2 (C1). (Right shift operation) The read data of the first word is stored in the L-Reg 25,
is shifted to the right by a predetermined amount.

Multiplexer 2
3. Select and write. (Figure 2 (C)-(1)) The next word is selected and the data read is R-Reg.
26 and shifted by the shifter 24 together with the first word data stored in the L-Reg 25, and the right one word is selected and written by the multiplexer 23. (Figure 2 (cl - (21) above < L
-Reg 25. By alternately storing and shifting read data into R-Reg 26, it can be aligned with the destination word.

The mask data is D when processing the first word in the X direction.
It is generated and output from the lower 4 bits of XP-Reg 15, and during final word processing, it is generated and output from the lower 4 bits of DXP-Reg 15 and DXL-Reg 1B, and the mask circuit 28a selects the corresponding bit based on the mask data. is masked. .

As described above, read data is shifted and written word by word while the source and destination word addresses are stepped in the X and Y directions within the rectangular area.

As mentioned above, <MPU10 only sends the parameters, and thereafter is processed at high speed by DMA by the main control unit 11.

〔Effect of the invention〕

As described above, the present invention provides a bitmap memory operation circuit that generates source and destination word addresses, calculates shift amounts, and performs read/write operations, thereby achieving high-speed arithmetic processing. This has the effect of reducing the processing required by a microprocessor, etc.

[Brief explanation of drawings]

Figure 1 is a diagram explaining the principle of the present invention, Figure 2 (a) is a diagram explaining the word address, Figure 2 (b) is a block diagram of the bitmap memory operation circuit of the embodiment, and Figure 2 (C) is a shift operation. 3(a) is a block diagram of a conventional display device, and FIG. 3(b) is a block diagram of a conventional display device.
l is an operation explanatory diagram. In the figure, 1 is a first address counter, 2 is a second address counter, 3 is an address control means, 4 is a counting means, 5 is a switching means, 6 is an operation means, 7 is a shift means, 8 is a masking means, 10 is a microprocessor (MPU), 11 is a main control unit, 12
is SXP-Reg, 13 is 5XP-Cnt,
14 is 5YP-Cnt. 15 is DXP-Reg, 16 is DXP-C
nt. 17 is DYP-Cnt, 18 is DXL-R
eg. 19 is DXL-Cnt, 20 is DYL-C
nt. 21 is a multiplexer, 22 is a shift control section, 23 is a multiplexer, 24 is a shifter, 25 is L-Reg, 26
is R-Reg. 27 is a mask data generator, 28 is a bitmap memory, 28a is a mask circuit, 30 is a microprocessor (MPU), 31 is an interface, 32 is a memory, 33 is a bitmap memory, 34 is a multiplexer, 35 is a drive unit, 36 is a CRT display section; Oζ4 month (〃Ya, 4 ri 50 month record 1)
2] (α) (+, 1
(2) Shift operation diagram Fig. 2 (C) Shift operation diagram Fig. 2

Claims (1)

[Claims] A bitmap memory manipulation circuit that moves data in a rectangular area specified by a start address and length information in the X and Y directions to a target area in units of words, the bitmap memory being specified by words. At the same time, first and second address counters (1, 2) each designating a word address within the rectangular area and a corresponding word address of the target area, and a counter in the X and Y directions based on the length of the rectangular area. Counting means (4) for counting the number of word operations for reading and writing are provided, the first and second address counters are incremented for each word operation, and the addresses within the rectangular area are addressed by the counting means. a control means (3); a switching means (5) for switching the address designation to the first and second address counters, respectively, in response to a read command and a write command; and a switching means (5) for aligning the word data of the rectangular area with the word data of the target area. a shift means (7); a mask means (8) for specifying a write-protected area in the target area; and a read command is sent to read the word data in the rectangular area, and the shifted word is shifted by the shift means. A bitmap memory operation circuit comprising: operation means (6) for specifying and writing data in a write-prohibited area along with a write command;