JPH0310957B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The present invention is a bit map memory operation circuit that moves bit data within a rectangular area on a bit map memory word by word. The word address of the source rectangular area to be incremented and the word address of the destination area are switched by a read/write command, and the read word data is aligned with the destination word of the destination area by a shift means, and the write-prohibited area is An operation circuit for writing the above data with masking is provided.

[Industrial application field]

The present invention relates to a bitmap memory manipulation circuit.

In display devices that output data based on bitmap memory, data can be read/written on the bitmap memory in order to move or copy data on the display screen.
A write operation is performed.

These operations such as movement and copying are performed in units of rectangular areas, and the position, length, etc. of the rectangular area from which to move (hereinafter referred to as source) and the position of the rectangular area to which to move (hereinafter referred to as destination) rectangular area. etc. parameters are specified.

If this rectangular area data is read/written in units of bits, the number of operations, that is, the processing time will be longer, and if the software is used to read/write in units of words or bytes, it will be difficult to align the words between the source and destination. Therefore, there is still a problem that the processing time becomes long.

Therefore, there is a need for a bitmap memory manipulation circuit that solves the above problems.

[Conventional technology]

An example of bitmap memory operation processing using software is shown below.

FIG. 3a is a block diagram of the display device, in which 30 is a microprocessor (MPU) capable of word processing, 31 is an interface for transmitting and receiving display data, etc. from the host computer, and 32 is for storing programs, data, etc. Memory: 33 is a bitmap memory, which is shown corresponding to the display screen; 34 is a multiplexer, which switches the operation of the bitmap memory 33 between the MPU 30 and the drive unit 35; 35 is a drive unit; , bit map memory 3
Repeat reading 3 and Cathode Ray Tube (CRT)
This is what drives the display section 36.

On the display screen, a word is formed in units of 16 dots in the X direction, and the word address of the bitmap memory 33 is made to correspond to the word in the X→Y direction from the home position [0,0] on the display screen. There is.

The operation of moving the data in the rectangular area S represented by the start address SP and the lengths Lx and Ly to the area D represented by the start address DP is performed as follows. [Refer to the operation diagram in Figure 3b] (1) Read word 1 and store it in memory 3. (2) Calculate SP-DP and use the value as the shift amount to perform clockwise shift operation in memory 3. (3) Above Shift data is written into word 3 with the M1 part masked, and then written into word 4 with the M2 part masked.

(4) Perform the above operation for each word in the rectangular area S.

[Problem that the invention seeks to solve]

As explained above, the software operation of the bitmap memory requires a large number of word operations, and especially when the rectangular area is large, the display of the processing result becomes slow and there is a problem in that it affects other processing.

In view of the above problems, it is an object of the present invention to provide a bitmap memory manipulation circuit using direct memory access (DMA) on a word-by-word basis.

[Means for solving problems]

For the above purpose, the bit map memory operation circuit of the present invention, as shown in the principle explanatory diagram of FIG. first and second address counters 1 and 2 for specifying the length of the rectangular area, respectively; and counting means 4 for counting the number of word operations for reading and writing in the X and Y directions based on the length of the rectangular area; and address control means 3 which increments a second address counter for each word operation and causes the counting means to address within the rectangular area; A switching means 5 for switching to a counter, a shifting means 7 for aligning word data in the rectangular area with word data in a target area, a masking means 8 for specifying a write-prohibited area in the target area, and a masking means 8 for specifying a write-prohibited area in the target area; Operating means 6 for reading word data in a rectangular area, shifting it by the shifting means, and writing the shifted word data together with a write command while specifying a write-prohibited area;
and .

[Effect]

That is, the first and second address counters are set with the first word address of the source and the first word address of the destination, respectively, the first address counter is switched to read the corresponding word in the bitmap memory, and the shift means to align it to the destination word.

Then, switching to the second address counter, masking the write-inhibited area and writing.

The first and second address counters are incremented within the designated rectangular area, and the above operation is repeated.

By using the bitmap memory manipulation circuit described above, the microprocessor MPU only needs to set parameters specifying the migration source and migration destination, and subsequent operations are performed using DMA.

〔Example〕

The details of the present invention will be explained according to the embodiment shown in FIG.

(Explanation of Word Addresses) FIG. 2a is an explanatory diagram of word addresses of a bitmap memory in which the X and Y axes each consist of 4096 bits.

In other words, the display screen is 16 in the X direction from the origin (0,0).
A word address is assigned to each bit (word), and when one line of 256 words is completed, the next line (Y=1) is assigned a consecutive number.

Such a word address is obtained by combining the upper 8 bits of the 12 bits of the address of the X coordinate and the 12 bits of the address of the Y coordinate, as shown in Figure 2a.
The lower 4 bits of the address of the X coordinate indicate the intra-word address.

As described above, the bitmap memory is operated in correspondence with the display screen and the bitmap memory.

(Configuration) FIG. 2b is a block diagram of the bitmap memory operation circuit of the embodiment, in which 10 is a microprocessor MPU, 28 is a bitmap memory, and a mask circuit 28a is shown.
The bitmap memory operation circuit of the present invention is comprised of the following circuits.

"Address circuit" 12 is a 12-bit register SXP- which sets the X coordinate address of the starting position SP of the source area.
Reg, 13 is an address counter SXP-Cnt in which the upper 8 bits of SXP-Reg12 are set, and is incremented each time a word is processed; 14 is an address counter 12 bits of the Y coordinate address of the starting position SP of the source area is set; The address counter SYP-Cnt is incremented each time word processing is completed, and together with SXP-Cnt13, it specifies the word address of the source area shown in Figure 2a. 15 is the X coordinate of the start position DP of the destination. 12-bit register to set address
DXP-Reg, 16 is an address counter DXP-Cnt in which the upper 8 bits of DXP-Reg15 are set and counted up every time a word is processed, 17 is an address counter 12 bits of the Y coordinate of the start position DP is set, and SYP-Cnt14 The address counter DYP-Cnt is counted up with the
Together with DXP-Cnt16, the word address of the destination is set. 18 is the register DXL-Reg where the length Lx in the X direction expressed in bits is set. 19 excludes the lower 4 bits of DXL-Reg18. The upper bits are set (the number of words in the X direction -
1) DXL-Cnt, which is counted down each time word processing is performed; 20 is DYL-Cnt, in which the length Ly in the Y direction expressed in bits is set, and which is counted down each time processing in the X direction is completed; 21 is a multiplexer; Then, according to the read/write command sent by the main control unit 11, the SXP-Cnt13,
SYP-Cnt14 source address output and DXP-
It consists of a device that switches between Cnt16 and DYP-Cnt17 destination address output.

"Shift circuit" 25 and 26 are registers L-Reg and R-Reg, which set read data alternately in the order of processing words; 24 has a width of 2 words, and is shifted by a predetermined amount to the right or left according to a command from the shift control section 22. The shifter 23 outputs two words of the shift result in parallel, and the multiplexer 23 selectively outputs one word to the right or left of the shifter 24.

``Mask Data Generation Circuit'' This circuit generates write-inhibited data for writing the first word and last word of destination in the X direction.

The bitmap memory operation circuit has a bitmap memory 28 and a data line 10 of one word (16).
In addition to 0 and 20 address lines 101, the control line includes control lines (not shown) such as read/write signal lines.

(Operation explanation) The operation will be explained below.

(1) The microprocessor MPU 10 inputs the parameters of the source area, that is, the X and Y addresses of the start position SP, the lengths Lx and Ly in the X and Y directions, and the X and Y addresses of the start position DP of the destination. At the same time, the main control section 11 is activated.

(2) The main control unit 11 sets the multiplexer 21 to the source side address, that is, SXP-Cnt13, SYP-Cnt
14 (source side) and sends a read signal to the bitmap memory 28, data of the first word of the source area is output to the data line 100, and this data is stored in the L-Reg 25.

(3) The shift control unit 22 has SXP-Reg12 and
Compare and calculate the lower 4 bits of DXP-Reg15,
A right (or left) shift command and a shift amount are sent to the shifter 24, and the multiplexer 23 is made to selectively output one right (or left) word.

(4) Next, the main control unit 11 outputs DXP-Cnt16 and DYP-Cnt17 (destination side) to the address signal line 101 using the multiplexer 21, and also sends the write signal and mask data to the bitmap memory 28. death,
The shifted data (output of multiplexer 23) is written.

When the above read/write operations are completed, the main control unit 11 increments the source and destination X addresses, that is, SXP-Cnt13 and DXP
-Cnt16 and DXL-Cnt
Count down to 19 and repeat the read/write operation.

(5) DXL-Cnt19 when processing the final word in the X direction
A carry signal is generated, and after this word processing is completed, the main control unit 11
16 and DXL-Cnt19, respectively, and increments SYP-Cnt14 and DYP-Cnt17 to perform word operations on the next line.

(6) DYL-Cut20 counts down every time the line is updated, and the entire operation ends after the carry output.

The details of the above shift operation will be explained with reference to the shift operation diagram shown in FIG. 2c. (Right Shift Operation) The read data of the first word is stored in the L-Reg 25, and is shifted to the right by a predetermined amount by the shifter 24.

One word on the left side of the shifter 24 in the drawing is selected by the multiplexer 23 and written. (Figure 2 c-
(1)) The next word is selected and the data read is R-
The data is stored in Reg 26 and shifted by shifter 24 together with the first word data stored in L-Reg 25, and one word on the right is selected and written by multiplexer 23. (FIG. 2c-(2)) By alternately storing read data in the L-Reg 25 and R-Reg 26 and shifting the read data as described above, it is possible to align the data to the destination word.

When processing the first word in the X direction, mask data is generated from the lower 4 bits of DXP-Reg15.
output, and DXP-Reg during final word processing
15 and the lower four bits of DXL-Reg 18, and the corresponding bits are masked by the mask circuit 28a based on the mask data.

As mentioned above, the source and destination word addresses are X and Y within the rectangular area.
The read data is shifted and written word by word while stepping in the direction.

As described above, the MPU 10 only needs to set the parameters, and thereafter the main control section 11 performs high-speed processing using DMA.

〔Effect of the invention〕

As explained above, the present invention provides a bitmap memory operation circuit that generates source and destination word addresses, calculates shift amounts, and performs read/write operations. This has the effect of reducing the amount of processing required by a microprocessor, etc.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2a is a diagram explaining the word address, FIG. 2b is a block diagram of the bitmap memory operation circuit of the embodiment, FIG. 2c is a shift operation diagram, and FIG. 3a 3 is a block diagram of a conventional display device, and FIG. 3b is an operation explanatory diagram. In the figure, 1 is the first address counter and 2 is the second address counter.
3 is an address control means; 4 is an address counter;
5 is a counting means, 5 is a switching means, 6 is an operation means, 7 is a shift means, 8 is a masking means, 10 is a microprocessor MPU, 11 is a main control section, 12 is an SXP-
Reg, 13 is SXP-Cnt, 14 is SYP-Cnt, 1
5 is DXP-Reg, 16 is DXP-Cnt, 17 is
DYP-Cnt, 18 is DXL-Reg, 19 is DXL-
Cnt, 20 is DYL-Cnt, 21 is multiplexer,
22 is a shift control unit, 23 is a multiplexer, 2
4 is shifter, 25 is L-Reg, 26 is R-Reg,
27 is a mask data generation section, 28 is a bitmap memory, 28a is a mask circuit, 30 is a microprocessor MPU, 31 is an interface, 32 is a memory, 33 is a bitmap memory, 34 is a multiplexer, 35 is a drive section, 36 is the CRT display section,
It is.

Claims (1)

[Scope of Claims] 1. A bitmap memory operation circuit that moves data in a rectangular area specified by a start address and length information in the X and Y directions to a target area in units of words, first and second address counters 1 and 2 for specifying a word address within the rectangular area and a corresponding word address of the target area, respectively; Address control means 3 includes a counting means 4 for counting the number of word operations for reading and writing, increments first and second address counters for each word operation, and causes the counting means to address within the rectangular area. a switching means 5 for switching the address designation to the first and second address counters, respectively, in response to a read command and a write command; a shifting means 7 for aligning the word data of the rectangular area with the word data of the target area; and a target area. a masking means 8 for specifying a write-prohibited area of the rectangular area; a read command is sent to read the word data of the rectangular area; the shift means shifts the word data; Operation means 6 for specifying and writing
A bit map memory operation circuit comprising: and.