JPS6231516B2 - - Google Patents

Info

Publication number
JPS6231516B2
JPS6231516B2 JP53120555A JP12055578A JPS6231516B2 JP S6231516 B2 JPS6231516 B2 JP S6231516B2 JP 53120555 A JP53120555 A JP 53120555A JP 12055578 A JP12055578 A JP 12055578A JP S6231516 B2 JPS6231516 B2 JP S6231516B2
Authority
JP
Japan
Prior art keywords
guide
intermediate circuit
marks
hole
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53120555A
Other languages
Japanese (ja)
Other versions
JPS5546563A (en
Inventor
Shinichi Tamura
Tetsuo Kunitomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP12055578A priority Critical patent/JPS5546563A/en
Publication of JPS5546563A publication Critical patent/JPS5546563A/en
Publication of JPS6231516B2 publication Critical patent/JPS6231516B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】 本発明は多層プリント配線板の孔あけ用ガイド
マークに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a guide mark for drilling holes in a multilayer printed wiring board.

回路がすでにエツチング加工された中間回路用
基板を有する多層プリント配線板にスルーホール
作成用あるいはその他の孔あけを行なうにあたつ
ては、中間回路用基板の回路の位置を知るために
ガイドホールを設けておき、このガイドホールと
穿孔機の位置決めピンとを合わせて孔あけを行な
つている。穿孔時の位置の基準となるべきガイド
ホールを多層プリント配線板に設けるには、次の
2つの手段が考えられる。その1つは第1図に示
すように、外層回路用片面銅張積層板3、プリプ
レグ4、エツチング加工済の中間回路用基板1の
夫々に予め個別にガイドホール5を穿孔してお
き、積層成形時の成形用プレート6,6間に配置
する際に、成形用ガイドピン7を各ガイドホール
5に挿通し、そして加圧成形を行なう。他の1つ
は第2図に示すように、エツチング加工済の中間
回路用基板1の所定位置に第3図に示すような
円、また同心円のガイドマーク2を付しておき、
そしてプリプレグ4及び外層回路用片面銅張積層
板3(又は銅箔)を積層成形する。その後、同図
Aに示す部分の外層回路用片面銅張積層板3とプ
リプレグ4とをけずる等の手段によつて中間回路
用基板1のガイドマーク2を露出させ、露出され
たガイドマーク2の部分にガイドホール5を穿孔
し、後工程の穿孔の基準とするものである。前者
においてはガイドピンを有する専用プレート金型
を必要とする上に中間回路用基板、プリプレグ等
に個別に予めガイドホールをあける必要がある。
これに対して後者では、このような専用プレート
金型も個別にガイドホールをあける必要もなく大
量生産に向き、また製造コストも安価になしうる
わけであるが、ガイドピンで固定して成形をする
ものでないため、ガイドマーク間の寸法ピツチに
ずれを生じることがある。このガイドマークに従
いガイドホールをあけて穿孔機にかけるならば、
穿孔機の位置決めピンとガイドホールとが合わ
ず、挿入不可能となるおそれがあり、このピツチ
のずれたものを無理に挿入して穿孔すると、孔の
位置ずれを起こし、中間回路と合わなくなつてし
まう。
When making through-holes or other holes in a multilayer printed wiring board that has an intermediate circuit board on which circuits have already been etched, guide holes are used to locate the circuits on the intermediate circuit board. A hole is drilled by aligning this guide hole with a positioning pin of a drilling machine. The following two methods are conceivable for providing a guide hole in a multilayer printed wiring board, which serves as a reference for the position at the time of drilling. One method is to drill guide holes 5 individually in advance in each of the single-sided copper-clad laminate 3 for the outer layer circuit, the prepreg 4, and the etched intermediate circuit board 1, as shown in FIG. When disposed between the molding plates 6, 6 during molding, a molding guide pin 7 is inserted into each guide hole 5, and pressure molding is performed. The other method is to attach circular or concentric guide marks 2 as shown in FIG. 3 to predetermined positions on the etched intermediate circuit board 1, as shown in FIG.
Then, the prepreg 4 and the single-sided copper-clad laminate 3 for outer layer circuits (or copper foil) are laminated and molded. Thereafter, the guide mark 2 of the intermediate circuit board 1 is exposed by means such as scraping the single-sided copper-clad laminate 3 and the prepreg 4 for the outer layer circuit in the portion shown in FIG. A guide hole 5 is drilled in the portion to serve as a reference for drilling in the subsequent process. In the former case, a special plate mold having guide pins is required, and it is also necessary to individually drill guide holes in the intermediate circuit board, prepreg, etc. in advance.
On the other hand, with the latter, such a dedicated plate mold does not require individual guide holes and is suitable for mass production, and the manufacturing cost can be reduced, but molding can be done by fixing it with guide pins. Therefore, the dimensional pitch between the guide marks may be misaligned. If you drill a guide hole according to this guide mark and put it on the drilling machine,
There is a risk that the positioning pin of the drilling machine and the guide hole will not match, making it impossible to insert the hole. If you forcefully insert a hole with a misaligned pitch into the hole, the hole will become misaligned and may not match the intermediate circuit. Put it away.

本発明はこの後者における欠点をおぎなうため
に為されたものであつて、その目的とするところ
はガイドホールの穿孔時にその孔あけ位置を成形
時のピツチずれに応じて微調整を行なえる形状と
した多層プリント配線板の孔あけ用ガイドマーク
を提供するにある。
The present invention has been made to overcome this latter drawback, and its purpose is to create a shape that allows fine adjustment of the position of the guide hole in accordance with the pitch deviation during molding. To provide a guide mark for drilling holes in a multilayer printed wiring board.

第4図に本発明にかかる中間回路用基板1に付
されるべきガイドマーク2の形状を示す。同図a
は径のことなる円を数個、その中心を一方向へ径
の大きさに順じてずらせたものである。同図bは
aにおいて示したものに十字線を加えてずれの方
向を明確にしたものであり、同図cは十字線に目
盛をつけたものである。このように予想されるず
れの方向において、許容範囲内で穿孔円心をずら
せた複数個のマークを付与してこれを孔あけ用ガ
イドマーク2としたものであつて、ガイドホール
5の孔あけにあたつては、比較的ピツチの良くあ
つているマークを使用して行なう。中間回路とガ
イドホール5の相互位置のずれが許容できる範囲
内で行なうのはもちろんである。こうして作成さ
れたガイドホール5を基準として位置決めピンに
合わせ、穿孔機にかけるのである。
FIG. 4 shows the shape of the guide mark 2 to be attached to the intermediate circuit board 1 according to the present invention. Figure a
is made up of several circles with different diameters whose centers are shifted in one direction according to the size of the diameter. Figure b shows the crosshairs shown in figure a to clarify the direction of deviation, and figure c shows the crosshairs with scales. In this way, a plurality of marks are provided with the drilling center shifted within an allowable range in the direction of the expected deviation, and these marks are used as the guide mark 2 for drilling. When doing so, use relatively well-pitched marks. It goes without saying that the positional deviation between the intermediate circuit and the guide hole 5 should be within an allowable range. The guide hole 5 thus created is used as a reference to align with the positioning pin and then placed on a drilling machine.

上述のように本発明においては、積層成形時に
ずれが生じたとしても、ガイドホールの孔あけ時
にガイドマーク中比較的ピツチのよくあつたマー
クを使用して行なうことでずれの吸収のための微
調整を行なえ、ガイドホール間の寸法ピツチを正
確に保ち得て後工程にずれの影響を与えることが
なく、従つて専用プレート金型も個別にガイドホ
ールをあける必要もなく大量生産に向き且つ製造
コストも安価である多層プリント配線板の製造法
における欠点をなくすことができるものである。
As mentioned above, in the present invention, even if misalignment occurs during laminated molding, by using relatively well-pitched guide marks among the guide marks when drilling guide holes, slight deviations can be absorbed to absorb the misalignment. Adjustments can be made, and the dimensional pitch between guide holes can be maintained accurately, so that deviations do not affect subsequent processes.Therefore, there is no need to drill guide holes individually in a dedicated plate mold, making it suitable for mass production. This method can eliminate the drawbacks of the method of manufacturing multilayer printed wiring boards, which is inexpensive.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は多層プリント配線板の一製造法を示す
断面図、第2図は他の製造法を示す断面図、第3
図a,b,cは夫々同上におけるガイドマークの
正面図、第4図a,b,cは本発明におけるガイ
ドマークの各実施例を示す正面図であつて、1は
中間回路用基板、2はガイドマークを示す。
Figure 1 is a cross-sectional view showing one manufacturing method for a multilayer printed wiring board, Figure 2 is a cross-sectional view showing another manufacturing method, and Figure 3 is a cross-sectional view showing another manufacturing method.
Figures a, b, and c are front views of the guide marks in the above, respectively, and Figures 4 a, b, and c are front views showing respective embodiments of the guide marks in the present invention, in which 1 is an intermediate circuit board, 2 indicates a guide mark.

Claims (1)

【特許請求の範囲】[Claims] 1 予想されるずれの方向において複数個の中心
をずらせたマークを中間回路用基板に付与して成
ることを特徴とする多層プリント配線板の孔あけ
用ガイドマーク。
1. A guide mark for drilling holes in a multilayer printed wiring board, characterized in that a plurality of marks are provided on an intermediate circuit board, the center of which is shifted in the direction of expected deviation.
JP12055578A 1978-09-30 1978-09-30 Guide mark for perforating multilayer printed circuit board Granted JPS5546563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12055578A JPS5546563A (en) 1978-09-30 1978-09-30 Guide mark for perforating multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12055578A JPS5546563A (en) 1978-09-30 1978-09-30 Guide mark for perforating multilayer printed circuit board

Publications (2)

Publication Number Publication Date
JPS5546563A JPS5546563A (en) 1980-04-01
JPS6231516B2 true JPS6231516B2 (en) 1987-07-08

Family

ID=14789194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12055578A Granted JPS5546563A (en) 1978-09-30 1978-09-30 Guide mark for perforating multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS5546563A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225893A (en) * 1985-03-29 1986-10-07 日立化成工業株式会社 Manufacture of multilayer printed interconnection board
JPS61225894A (en) * 1985-03-29 1986-10-07 日立化成工業株式会社 Manufacture of multilayer printed interconnection board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5098666A (en) * 1973-12-29 1975-08-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5098666A (en) * 1973-12-29 1975-08-05

Also Published As

Publication number Publication date
JPS5546563A (en) 1980-04-01

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