TWI442857B - Embedded circuit structure and method for making the same - Google Patents

Description

Buried line structure and forming method thereof

The present invention relates to a buried wiring structure and a method of forming the same. In particular, the present invention relates to a buried wiring structure having extremely small holes and a method of fabricating the same.

A circuit board is an important component in an electronic device. In order to pursue thinner finished thickness, meet the needs of thin wires, and overcome the shortcomings of etching and reliability, embedded structures have gradually emerged. Since the embedded structure completely embeds the line pattern in the substrate, it is also called a buried line structure, which helps to reduce the thickness of the packaged product.

As electronic products move toward light and thin, in a variety of different applications, such as wireless communications, portable electronics, automotive dashboards, etc., boards are often placed in limited product interior space. Drilling is usually required on the circuit board. On the one hand, it can be used as a tooling hole for component alignment, and on the other hand, it can be a medium through hole when the circuit between the different surfaces is turned on. The location and aperture size of these holes directly affect the integration of the circuit on the board and the quality of the finished product.

As far as current technology is concerned, a method of forming a buried wiring structure is known. Referring to Figures 1-4, a prior art process for forming a buried line structure is illustrated. As shown in Fig. 1, first, an upper plate 110 and a lower plate 120 are provided. The upper plate 110 includes a removable loading plate 111 and an upper patterned metal layer 112. Similarly, the lower plate 120 includes a removable downloading plate 121 and a lower patterned metal layer 122, and preforming a jig hole (not shown), respectively. Thereafter, as shown in FIG. 2, the upper patterned metal layer 112 and the lower patterned metal layer 122 of the upper plate 110 and the lower plate 120 are respectively pressed into the semi-solid substrate 130 to form the pressed substrate 130. . Continuing, as shown in FIG. 3, the uploading plate 111 and the downloading plate 121 can be removed to expose the upper patterned metal layer 112 and the lower patterned metal layer 122, respectively. At this point, the drilling step can be performed to drill the required holes. As shown in FIG. 4, for example, using a burr, the respective patterning metal layer 112, the substrate 130, and the lower patterned metal layer 122 are sequentially drilled according to the respective fixture holes, thereby forming the required Drill hole 140.

The jig holes, which are typically used on the upper plate 110 and the lower plate 120 for alignment of the components, may be formed earlier than the holes 140. The jig holes are randomly placed two sheets of the same sheet, which are first defined by the drill pins before the upper patterned metal layer 112 and the lower patterned metal layer 122 are formed. Considering the positioning error of the burring machine, although each batch of sheets will drill substantially corresponding jig holes, there will still be non-negligible alignment errors in the jig holes between different batches of sheets.

If the upper plate 110 and the lower plate 120 used in the subsequent drilling step are not the original pair of sheets, the alignment error of the hole 140 may be due to the alignment error of the jig hole between the plates and the alignment when pressing. The error is further amplified, which will seriously affect the yield of the finished product.

Additionally, the aperture size of the bore 140 is of course directly related to the size of the bur. Although the smaller the drill needle can drill the drill hole 140 with smaller aperture, and the smaller the positioning pad for positioning the drill hole 140, the arrangement of other components on the circuit board can be increased, but the smaller the diameter of the drill needle, the easier it is. Damaged. Therefore, in the mass production scale, it is necessary to sacrifice the drilling design of the small aperture in exchange for greater benefits in the process consideration. However, boreholes with smaller apertures have a dominant advantage in both error tolerance and component integration. It can be seen that the existing technical level of forming a buried line structure cannot meet the market trend that has been pursued with high density and high precision.

Thus, there is a real need for a novel buried circuit structure and method of manufacture. These manufacturing methods can minimize the alignment error of the upper plate, the lower plate and the drill hole, and can be drilled smoothly by using a smaller size positioning pad to obtain an embedded circuit structure with an ultra-small aperture.

The present invention is directed to a novel buried circuit structure and a method of fabricating the same. The method of manufacturing the novel buried circuit structure can not only minimize the alignment error between the upper plate, the lower plate and the drilling hole in each step, but also can be smoothly formed by using a smaller size positioning pad. Due to the buried circuit structure of the present invention, an ultra-small aperture drilling hole can be produced, which is advantageous for improving the design density of the circuit, and can fully meet the needs of customers and the market. As a result, the yield or yield of the finished product can be greatly improved. In addition, the embedded circuit structure with ultra-small aperture drilling can make the related products stand out in the technical level and continue to maintain the leading position in the industry.

The invention firstly provides a buried circuit structure, comprising a substrate having a first surface and a second surface opposite to the first surface, a first buried line, located in the first side of the substrate, A buried circuit, located in the second side of the substrate, and a hole in at least one of the first side and the second side of the substrate. The holes are filled with a conductive material and further have a pore size ranging between 100 μm and 5 μm. In an embodiment of the invention, the pores may have a pore size ranging between 75 μm and 5 μm.

The present invention further provides a method of forming a buried line structure. First, a first carrier and a second carrier are provided. The first carrier includes a first substrate and a first circuit layer, and the second carrier includes a second substrate and a second circuit layer. Next, a drilling process is performed to form a first hole in the first carrier and a second hole in the second carrier. Then, a patterning process is performed to form a first patterned circuit layer in the first carrier and a second patterned circuit layer in the second carrier. Then, a substrate is provided, so that the first patterned circuit layer of the first carrier and the second patterned circuit layer of the second carrier are respectively buried in the substrate to become a first buried circuit and a first The second buried circuit, while the substrate will close the first hole and the second hole. Next, the first bottom plate and the second bottom plate are removed. Continuing, a clearing process is performed to remove portions of the substrate to expose the first and second holes. The first and second cavities respectively have a pore size ranging between 100 μm and 5 μm. Then, a conductive material is filled in the first cavity and the second cavity, respectively, to form a desired buried wiring structure. In an embodiment of the invention, the apertures may also have a pore size ranging between 75 μm and 5 μm.

SUMMARY OF THE INVENTION The present invention is directed to a novel buried circuit structure and methods of forming such a buried circuit structure. The present invention first provides a novel buried line structure. Fig. 5 illustrates an embodiment of the buried wiring structure of the present invention. Referring to FIG. 5, the buried circuit structure 200 of the present invention includes a first buried line 212, a second buried line 222, a substrate 230, and a hole 240. The buried line structure 200 of the present invention, as the case may be, may be a single-sided buried line structure or a double-sided buried line structure.

If the buried wiring structure 200 of the present invention is a double-sided buried wiring structure, the substrate 230 has a first surface 201 and a second surface 202. For example, the first face 201 is opposite the second face 202. At the same time, the first buried line 212 is located in the first side 201 of the substrate 230. Additionally, the second buried line 222 is located in the second side 202 of the substrate 230.

The first buried line 212 and the second buried line 222 are typically patterned and embedded in the substrate 230 to form the buried line of the buried line structure 200 of the present invention. The first buried wiring 212 and the second buried wiring 222 may respectively comprise a conductive material such as aluminum or a metal of copper. The substrate 230 may comprise an insulating material such as a pre-preg.

The aperture 240 is located in the first side 201 of the substrate 230 or in the second side 202. In an embodiment of the invention, the cavity 240 communicates with the first side 201 and the second side 202 of the substrate 230, for example, electrically connecting the first buried line 212 and the second buried line 222. Thus, the aperture 240 can be a blind aperture, as desired. Alternatively, the aperture 240 is a through hole that connects the first buried line 212 of the first surface 201 with the second buried line 222 of the second surface 202.

The cavity 240 is filled with a conductive material 241 such as a metal of aluminum, tin or copper. The drill hole is used to define the borehole compared to the prior art, so the bore size of the borehole is difficult to be less than 100 μm. The aperture 240 of the present invention may have a pore size of less than 100 μm, for example, a pore size range between 100 μm and 5 μm. In an embodiment of the invention, the apertures 240 have a pore size ranging between 75 [mu]m and 5 [mu]m. The smaller holes 240 can use a smaller positioning pad 242, which helps to increase the design density of the circuit, and can fully meet the needs of customers and the market.

The buried wiring structure 200 of the present invention may additionally include a solder resist layer 250 and/or an oxidation resistant layer 260 as occasion demands. The solder resist layer 250 may cover one or both of the first buried line 212 and the second buried line 222 and expose the holes 240. The conductive material 241 in the cavity 240 may be covered with the oxidation resistant layer 260 such that the oxidation resistant layer 260 covers one or both of the first side 201 and the second side 202. The oxidation resistant layer 260 may comprise an organic protective film layer or an inert conductive material such as gold, nickel/gold, silver or tin metal.

If the buried wiring structure 200 of the invention comprises a solder mask layer 250, the total thickness of the buried wiring structure 200 may range between approximately 350 μm and 8 μm. Due to the buried circuit structure of the present invention, an ultra-small aperture drilling hole can be produced, so that the yield or yield of the finished product can be greatly improved. In addition, the embedded circuit structure with ultra-small aperture drilling can make the related products stand out in the technical level and continue to maintain the leading position in the industry.

The present invention continues to provide a method of forming a buried wiring structure having ultra-small holes. Figures 6-13 illustrate an embodiment of a buried circuit structure having ultra-small holes of the present invention. Referring to FIG. 6, first, the first carrier 210 and the second carrier 220 are provided to form a pair of carriers. The first carrier 210 includes a first substrate 211 and a first line 212, and the second carrier 220 includes a second substrate 221 and a second wiring layer 222. The carrier may be a composite sheet such as a copper-aluminum-copper laminate, a copper-nickel-copper laminate or an aluminum-glass-copper laminate. The thickness of each layer is as the case may be, for example, the thickness of the aluminum layer is between 40 μm and 100 μm, and the thickness of the copper layer is between 2 μm and 6 μm. The carrier may also have a surface roughness Ra ranging between 0.3 μm and 1.0 μm.

Next, as shown in FIG. 7, a drilling process is performed, and then a first group of jig holes 215 and a second group corresponding to each other are formed in the first carrier 210 and the second carrier 220. With holes 225. At the same time as forming the jig hole, the position of the hole in the future is defined in advance. A first hole 240' may be formed in the first carrier 210 and a second hole 240" may be formed in the second carrier 220 by forming a jig hole. The first hole 240' is The second cavities 240" may correspond to each other. If the first hole 240' and the second hole 240' correspond to each other, it will become a through hole. If the first hole 240' and the second hole 240' do not correspond to each other, each of them will be a blind hole.

In an embodiment of the invention, each pair of carrier plates is simultaneously drilled to ensure alignment. Depending on the design of the tool, more than one pair of carrier plates can be drilled each time the drilling process is performed, for example two pairs, three pairs, four pairs, and so on. Then each pair of carrier plates obtained has a correct alignment relationship.

Then, as shown in Fig. 8, a patterning process is performed. The patterning process forms a predetermined first patterned wiring layer 212 in the first carrier 210, and a predetermined second patterned wiring layer 222 is formed in the second carrier 220. For example, the first patterned wiring layer 212 and the second patterned wiring layer 222 are formed using lithography and etching to perform a patterning process. Such patterned processes are well known to those skilled in the art and will not be described here.

Then, as shown in FIG. 9, a substrate 230 is provided, and the first patterned circuit layer 212 of the first carrier 210 and the second patterned circuit layer 222 of the second carrier 220 are buried in the substrate 230, respectively. To become a first buried line 212 and a second buried line 222, respectively. In an embodiment of the invention, the substrate 230 may be a semi-solid material, such as a glass substrate, so that the substrate 230 is temporarily closed and partially filled into the first cavity 240' and the second cavity 240", even The first patterned circuit layer 212 and the second patterned circuit layer 222 are slightly protruded.

Next, as shown in FIG. 10, the first bottom plate 211 and the second bottom plate 221 are removed, thereby exposing the first patterned circuit layer 212 and the second patterned circuit layer 222. There is also a substrate 230 that protrudes from the first patterned wiring layer 212 and the second patterned wiring layer 222 through the first holes 240' and the second holes 240".

Continuing, as shown in FIG. 11, a hole forming process is performed to remove the substrate 230 in the first cavity 240' and the second cavity 240" to open and expose the first cavity 240' and the second cavity 240". After the first cavity 240' and the second cavity 240" are formally formed, there are holes having a pore diameter ranging between 100 μm and 5 μm , respectively.

Since the first hole 240' and the second hole 240" are only filled with the substrate 230, if the substrate 230 comprises a glass substrate, a laser, such as a carbon dioxide laser, can be used to selectively and specifically remove the substrate in the hole. 230. Since the carbon dioxide laser can only remove the glass fiber substrate, but the first patterned circuit layer 212 and the second patterned circuit layer 222 made of a metal material cannot be removed, the hole forming process can be regarded as a self. The alignment process does not affect the original alignment error of the first aperture 240' and the second aperture 240" relative to the fixture aperture.

The first drilling required after the completion of the substrate cutting does not cause a relative variation of the misalignment, and the through hole fabrication after the pressing does not cause another variation, so the size and the alignment level can be achieved. The relative improvement in the acquisition is an important feature of the technology in this case.

In other words, the apertures of the first aperture 240' and the second aperture 240" can be adjusted not only in accordance with product specifications, but also the first aperture 240' and the second aperture 240" are positioned in the buried wiring structure with great precision. If the previous first hole 240' and the second hole 240' correspond to each other, the clearing process together empties the first hole 240' and the second hole 240" to become a through hole. If the previous first hole 240' and the second hole 240' do not correspond to each other, the clearing process cleans at least one of the first hole 240' and the second hole 240", and each becomes a blind hole.

Then, as shown in FIG. 12, a conductive material 241 is filled in the first cavity 240' and the second cavity 240", respectively, for example, by electroplating or electroless plating to form the desired buried wiring structure 200. In an embodiment of the invention, the apertures may also have a pore size ranging between 75 μm and 5 μm.

As needed, as shown in FIG. 13, the buried wiring structure 200 of the present invention may additionally be formed with a solder resist layer 250 and/or an oxidation resistant layer 260. The solder resist layer 250 may cover one or both of the first buried line 212 and the second buried line 222 and expose the holes 240. The conductive material 241 in the cavity 240 may be covered with the oxidation resistant layer 260 such that the oxidation resistant layer 260 covers one or both of the first side 201 and the second side 202. The oxidation resistant layer 260 may comprise an organic protective film layer or an inert conductive material such as gold, nickel/gold, silver or tin metal.

The above is only one embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

200. . . Buried line structure

201. . . First side

202. . . Second side

210. . . First carrier

211. . . First bottom plate

212. . . First buried line

215. . . First set of fixture holes

220. . . Second carrier

221. . . Second bottom plate

222. . . Second buried line

225. . . The second group of holes

230. . . Substrate

240. . . hole

241. . . Conductive material

242. . . Positioning pad

250. . . Solder mask

260. . . Antioxidant layer

Figures 1-4 illustrate the process by which conventional techniques form a buried line structure.

Fig. 5 illustrates an embodiment of the buried wiring structure of the present invention.

Figures 6-13 illustrate an embodiment of a buried circuit structure having ultra-small holes of the present invention.

200. . . Buried line structure

212. . . First buried line

222. . . Second buried line

230. . . Substrate

240. . . hole

241. . . Conductive material

242. . . Positioning pad

250. . . Solder mask

260. . . Antioxidant layer

Claims (9)

A method for forming a buried circuit structure includes: providing a first carrier and a second carrier, wherein the first carrier includes a first substrate and a first circuit layer, and the second carrier includes a a second substrate and a second circuit layer; performing a drilling process to form a first hole in the first carrier and a second hole in the second carrier; performing a patterning process Forming a first patterned circuit layer in the first carrier, and forming a second patterned circuit layer in the second carrier; providing a fiberglass substrate such that the first patterned circuit layer Separating the second patterned circuit layer into the glass fiber substrate to form a first buried circuit and a second buried circuit, respectively, and the glass substrate closes the first hole and the second a hole; removing the first bottom plate and the second bottom plate; performing a clearing process, removing a portion of the fiberglass substrate to expose the first hole and the second hole, wherein the first hole and the second hole Having a pore size ranging between 100 μm and 5 μm, respectively; The first cavity and the second cavity are filled with a conductive material to form the buried circuit structure. The method of forming a buried circuit structure according to claim 1, wherein the performing the patterning process further comprises: forming a first group of jig holes corresponding to each other in the first carrier and the second carrier With a second set of fixture holes. A method of forming a buried wiring structure according to claim 1, wherein a lithography method is used to perform the patterning process to form the first hole and the second hole. A method of forming a buried wiring structure according to claim 1, wherein the substrate comprises a glass substrate. A method of forming a buried wiring structure according to claim 1, wherein the substrate portion is filled in the first cavity and the second cavity. The method of forming a buried circuit structure according to claim 1, wherein after removing the first bottom plate and the second bottom plate, the substrate protrudes from the first hole and the second hole to protrude from the first buried line And the second buried line. A method of forming a buried circuit structure according to claim 1, wherein the hole forming process forms the first hole and the second hole together to form a through hole. A method of forming a buried circuit structure according to claim 1, wherein the hole forming process forms at least one of the first hole and the second hole to form a blind hole. The method of forming a buried line structure of claim 1, further comprising: forming a solder resist layer covering at least one of the first buried line and the second buried line and exposing the first hole With the second hole; An anti-oxidation layer is formed to cover the conductive material in the first cavity and the second cavity.