JPS6231314B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique effective for alarm detection circuits in digital watches, electronic clocks, and the like.

It is well known that digital watches have the function of generating an alarm at predetermined times depending on the purpose of use. It is necessary to indicate whether the As such an alarm coincidence detection circuit, a circuit as shown in FIG. 1 is used.

FIG. 1 is a block diagram showing an example of the alarm coincidence detection circuit, which includes a time counter 1 that counts the current time, and n alarm counters that count the set time for each of the n set channels. Alarm counter group 2, comparison circuit group 3 having n comparison circuits that compare the output of time counter 1 and the output of the alarm counter, and whenever any of the outputs of comparison circuit group 3 conflict, It consists of a priority order determining circuit 4 which produces one output, and a display circuit 5 which displays the set number of channels based on the output of the priority order determining circuit 4. Note that 6 is an alarm circuit, which generates an alarm based on the output obtained through the OR circuit _OR0 to which the output of the comparison circuit is applied.

The above-mentioned time counter and alarm counter are composed of a plurality of flip-flop circuits, and the comparison circuit group 3 converts the outputs of the time counter and alarm counter into two as shown in FIG. 2A.
It consists of exclusive OR circuits G ₁ to G _o as inputs.
This exclusive OR circuit, for example, as shown in FIG. 2B, consists of two AND NOT circuits NAN ₁ and NAN ₂ and an OR circuit OR ₁ .

The above alarm coincidence detection circuit has a problem in that when the number of channels increases, the number of comparison circuits increases accordingly, and the number of wires also increases. Furthermore, since the number of gates in the comparator circuit increases, there is a problem in that the chip area becomes large when integrated into a semiconductor circuit.

The present invention was made to solve the above problems, and its purpose is to simplify the circuit, reduce the number of wiring lines, and reduce the chip size.

The gist of the present invention to achieve the above object is to provide a holding means having a plurality of channels for holding a first digital signal as an alarm time signal, and to sequentially select the plurality of channels of the holding means. and a comparison means for comparing the first digital signal selected by the selection means with a second digital signal as a reference time signal, and generates an alarm in response to the output of the comparison means. a digital signal processing device, characterized in that it comprises channel designation means for forming a channel display signal based on a signal for the selection operation of the selection means and an output of the comparison means; Located in the processing unit.
In this application, "time" refers to seconds, hours, days,
The date, month, year, etc. shall be broadly indicated.

The present invention will be specifically described below with reference to embodiments and drawings.

FIG. 3 is a block diagram showing one embodiment of the alarm coincidence detection circuit according to the present invention.

In the figure, 1 is a time counter that counts the current time and converts it into a digital signal, 2 is an alarm counter group having n alarm counters that counts the time set by n setting channels and converts it into a digital signal, and 7 is, for example, 1 A time division circuit that time-divides and outputs the signal of the alarm counter in relation to timing pulses arriving every second; 8 compares the digital signal V _B of the time counter with the output V _T of the time division circuit 7; 9 is a channel designation circuit that designates a set channel based on the output V _C of the comparison circuit; and 5 is a display circuit that displays a predetermined channel based on the output of this channel designation circuit. It is. Note that 6 is an alarm circuit that generates an alarm based on the output V _C of the comparison circuit.

Here, an example of the configuration of the time division circuit 7, which is one of the features of the present invention, is shown in FIG. That is,
Timing pulse T ₁ that arrives at a timing that deviates from the alarm counter output V _A1 to V _Ao by 1 second
An AND circuit L ₁ ~ _{L o} with ~T _o as two inputs, and an OR circuit with multiple inputs as the output of this AND circuit
Consists of OR ₂ . In this way, the alarm counter signal can be made into a time-division signal.

Furthermore, as shown in _FIG .
An exclusive OR circuit E _X1 with two inputs is the output V _T of
Composed by.

Further, the channel designation circuit 9 is constituted by a circuit as shown in FIG. That is, flip-flop circuits NOR ₁ , NOR ₂ each have a reset terminal R and a terminal to which the output V _C of the comparator circuit is input.
11, an AND circuit AN ₁ which has two inputs: the inverted output of this flip-flop circuit (inverted by inverter IN ₁ ), and the clock pulse φ that arrives every second.
and a ring counter 10 consisting of a plurality of flip-flop circuits FF ₁ to FF _o and an OR/NOR circuit NOR ₃ . The operation of the channel designation circuit 9 is as follows.

FIG. 7 is a timing chart for explaining the operation of the channel designation circuit 9.

The clock pulse φ arrives every second in synchronization with the timing pulse of the time division circuit 7. If the flip-flop 11 is reset by the reset signal R, the ring counter 10 will be in one-to-one correspondence with the alarm counter selected by the time division circuit 7 of the alarm counter group 2. The count value is updated sequentially. That is, if the flip-flop 11 is in the reset state, the output of the inverter _IN1 is set to the "1" level (high level) accordingly. The AND circuit _AN1 outputs the same clock pulse as the clock pulse φ in response to the output of the inverter _IN1 being at the "1" level. Ring counter 10 counts clock pulses supplied from AND circuit _AN1 . As a result of counting, the outputs V _F1 , V F2 , etc. of the flip-flops FF ₁ , FF _{2 ,} etc. constituting the ring counter 10 are selectively and sequentially set to the "1" level.

The counting operation of the ring counter 11 is stopped in response to the flip-flop 11 being set to the set state by the output V _C of the comparator circuit 8.
The counting state of the ring counter 11 in the counting stopped state is in one-to-one correspondence with the alarm counter that formed the output V _C among the plurality of alarm counters in the alarm counter group 2. When multiple alarms conflict, one alarm takes priority as follows. For example, if the first and third channels (Ch ₁ and Ch ₃ ) are specified among the alarm channels, the output V _c of the comparator circuit 8
is the first channel as shown in the timing chart
Ch ₁ and the third channel Ch ₃ are at the “1” level. The outputs V _F1 to V _Fo of each flip-flop of the ring counter 10 can rise every second, but since the first channel Ch1 is specified, the operation of the ring counter stops and only V _F1 becomes the “1” level, and based on this, Ch ₁ will be displayed.

As described above, the present invention converts the alarm counter signal into a time-division signal, matches the time-division signal with the time counter signal, and specifies a predetermined channel based on this coincidence.
An alarm can be generated and a channel display can be performed.

In other words, in the conventional system, a matching circuit is provided for each counter, and the outputs thereof are taken out in parallel, thereby outputting a matching channel signal.However, in the present invention, by using a time division signal, the matching circuit can be omitted. Therefore, the comparison circuit can be simplified and the number of gates and wiring can be reduced. Therefore, the chip size can also be reduced. Also, taking advantage of the fact that it is time-division, it is necessary to prioritize when returning to the normal signal by time-division (i.e., the ring counter is stopped by a coincidence signal, and the time at which the ring counter is stopped is used to determine which channel matches the signal). (as a signal), there is no need to use a conventional priority determining circuit.

The present invention is not limited to the above embodiments, and various modifications can be made.

For example, the channel designation circuit 9 shown in the above embodiment may be a circuit as shown in FIG.
That is, as shown in the figure, a plurality of AND circuits AN ₂₁ to AN _2o each having two inputs are the timing pulses T ₁ to _{T o} shifted every second and the output of the comparison circuit.
Even if configured as above, it is possible to specify a predetermined channel in the same way as described above. According to this configuration, the number of gates is smaller than that of the embodiment shown in FIG. 3, and the device is more effective.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional alarm coincidence detection circuit, Fig. 2A is a circuit diagram showing an example of a comparison circuit used therein, and Fig. 2B is a circuit diagram showing an example of an exclusive OR circuit used therein. A circuit diagram showing an example; FIG. 3 is a block diagram showing an embodiment of the alarm coincidence detection circuit according to the present invention; FIG. 4 is a circuit diagram showing an example of a time division circuit used therein;
FIG. 5 is a circuit diagram showing an example of the comparison circuit in FIG. 3, FIG. 6 is a circuit diagram showing an example of the channel designation circuit in FIG. 3, and FIG. 7 is a timing chart for explaining its operation. FIG. 8 is a circuit diagram showing another example of the above channel designation circuit. 1: Time counter, 2: Alarm counter group, 3: Comparison circuit group, 4: Priority determining circuit,
5: Display circuit, 6: Alarm circuit, 7: Time division circuit, 8: Comparison circuit, 9: Channel specification circuit, 1
0: Ring counter, 11: Flip-flop circuit, G ₁ ~ _o , L ₁ ~ _Lo , Ex ₁ , OR ₀ ~ OR ₂ , NAN ₁ ,
NAN ₂ , NOR ₁ ~ NOR ₃ , AN ₁ , AN ₂₁ ~ _{AN 2o} : Gate circuit, FF ₁ ~ _{FF o} flip-flop circuit,
IN ₁ : Inverter.

Claims (1)

[Claims] 1 Holding means each having a plurality of channels for holding a first digital signal as an alarm time signal, a selection means for sequentially selecting the plurality of channels of the holding means, and a first digital signal selected by the selection means. a comparison means for comparing a first digital signal as a reference time signal with a second digital signal as a reference time signal, the digital signal processing device generating an alarm according to an output of the comparison means, the selection means A channel specifying means for forming a channel display signal based on a signal for a selection operation and an output of the comparison means, and a channel display means for displaying a channel based on the channel display signal. Features of digital signal processing equipment.