JPS62298227A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To obtain a simple and inexpensive digital PLL circuit not requiring any oscillator by employing an integration device acting like a pure logic circuitry digital signal processing type local oscillating function. CONSTITUTION:A Q output of a D flip-flop 40 used as a phase comparator is fed to a selector 80, which selects either binary-coded numeral m1=1228 or a numeral m2=1230 and supplies an output to a phase ingegration device acting like a function of a VCO. The phase integration device is a complete integration device comprising a 16-bit full adder 70 and a 16-bit register 60, and an output of the full adder 70 is supplied to a D input of the register 60 and the Q output of the register 60 and the output of the selector 80 are fed to the full adder 70. An input clock f1 is fed to a clock input of the register 60, and a Q output, i.e., the output clock f0 is fed to a frequency divider 50 and outputted at an output terminal 90.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a phase-locked oscillator (hereinafter referred to as PLL) that generates a frequency synchronized with an input signal frequency. The present invention relates to a digital PLL circuit composed of processing circuits.

[Conventional technology]

f phase-locked to the input frequency fi. =(n/m
)·f, (where n and m are integers) PLL circuits that generate a frequency f0 have come to be used in many fields. The principle of PLL will be explained with reference to FIG.

When a sine wave signal or a rectangular wave signal with frequency f1 is input to input terminal 1, that is, input terminal 1 has an angular frequency of 2πf, = ω.
When a phase amount of i (22777 seconds) is input, the input phase is divided by the frequency divider 2, and is applied to the phase comparator 6 at a phase increase rate of 07m. The phase comparator 3 and the phase ω of the local oscillator (VCO) 4. ω with frequency divider 5. The difference between the phase increase rate set to /n and the above-mentioned ωi/m is taken, and the difference is added as an input to the local oscillator 4. That is, the local oscillator 4 integrates the difference to increase the output phase increase rate ω. /n
It has a negative feedback configuration so that it is automatically tilted to the side so as to follow the input phase increasing speed ωi/m.

A logic circuit type digital PLL in which such a PLL is constructed from a digital logic circuit is disclosed in the following document. B-Nice-T-J.

Analysis and Synthesis or Digital PLL for FM Demodulation (BSTJ), December 1968, pp. 2207-2237.

DEC, 1968, Analysis and 5y
nthesis of aDigital Phase
-Locked Loop for FM Demod
ula-tion). The PLL configuration according to the same document is described in the sixth section.
As shown in the figure.

In FIG. 6, the input phase (actually a square wave) is applied to terminal 7. Exclusive OR gate 8 performs a phase comparison operation. This output controls selector 9 and outputs 2
phase (actually frequency f,

Select the rectangular wave of f2 * f, < f2 ). The selected clock f1 or f2 is regarded as a phase difference per unit time, and this is integrated by a counter 1o to obtain an output phase. In reality, the output frequency f is phase-synchronized.

is obtained at terminal 11. In addition, in the circuit of FIG. 6, compared to the basic configuration of FIG. 5, the frequency divider is 1/m.

It is a simplified form in which 1//rI is omitted.

[Problem that the invention seeks to solve]

As described with reference to FIG. 6, the conventional technology requires two clock signals that express the phase difference per unit time. Tsumashi, f, and f2. Also, this f.

and f2 are f, (f
', ·2N<f2 (where N is the number of bits of the counter 10).

Moreover, fl and f2 are (fl
It is also desirable that the balance be such that "f2)/2"; f,·2N. As a practical matter, such fl and f2 have the disadvantage of being difficult to cultivate. There is no problem if two oscillators are prepared from the beginning to obtain f and f2, but using two expensive oscillators is not economically practical.

Using one oscillator (output frequency f,), from this f,.

To create f2, f, =f,/(t+1)
, f2=f,/l (where t is an integer). However, due to the balance condition described above, it is necessary to make f sufficiently large and also make t+1 large at t. In other words, it is necessary to use a high frequency oscillator and increase the capacity of the frequency division counter to increase the frequency division number.

An object of the present invention is to provide a digital PLL circuit that uses only an oscillator and has a simple configuration.

[Means for solving problems]

The above object is to provide an N-bit binary full adder and an N-bit binary full adder in a digital PLL circuit equipped with a phase comparator and a phase integrator.
It is configured using a bit register, and the output signal of the phase comparator selects and switches two numerical data and inputs it to the phase integrator, and any 1-bit signal from the N-bit register is input to the phase comparator. This is achieved by outputting it as a feedback signal.

[Effect]

The phase integrator composed of an adder and a register is the VC of the PLL.
Functions as O. The phase comparator operates at a clock frequency or sampling frequency f8 rate, and its output signal frequency f. becomes . Here, the clock frequency f8. Focus number N.

An arbitrary output fo can be obtained by appropriately selecting the input numerical data mi, and by negative feedback of an arbitrary 1 of the output signal of the register and the node to switch the input numerical data m1.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 4.

FIG. 1 is a configuration diagram of a digital PLL circuit according to an embodiment of the present invention. In this embodiment, the input clock signal f
,=8192KHz to output clock signal fo=153
．． The case where 6KHz is obtained will be described. That is, 8192
KHz 15i6KHz-=
= 51.2 KHz, so the input signal f3.
Divide the output signal f0 by 160 and 3 to obtain 51.2K.
The configuration is such that a Hz signal is created and phase comparison is performed using this signal.

In FIG. 1, an input clock f1 input to an input terminal 10 is frequency-divided by 160 by a frequency divider 20.

The output signal of the frequency divider 20, which outputs the 160th input clock f1, is input to the D terminal of the D-type flip-flop 30, and the input clock f is input to the clock terminal CP. The Q output of the D-type clip flop 30 is input to a set terminal of a D-type flip-flop 40 used as a phase comparator. The clock terminal of the D flip-flop 40 receives an output clock f, which will be described later. The output clock of the divider 50, which divides the frequency by 3, is 51.2K in this embodiment.
A Hz clock is input. D flip flop 40
The Q output of is applied to the selector 80. This selector 8
0 depends on the Q output of the D7 lip 7og 40, and the two binary encoded numbers m1=1228 or m2=1
230 is selected and output to a phase integrator that functions as a vCO.

The phase integrator is a complete integration type consisting of a 16-pin full adder 7o and a 16-bit register 60.
The output of the register 60 is input to the D input of the register 60, and the Q output of the register 60 and the output of the selector 80 are input to the full adder 70. The input clock fi is input to the clock input of this register 60, and the Q output section outputs the output clock f. is output to the frequency divider 50 and output terminal 90
is output to.

The complete integration type phase integrator (60, 70) has a fourth
As shown in the figure, the integral operation is performed modulo 2NK.

In this example, since N=16, modulo 6553
It works on 6. In addition, the phase integrator operates at a clock frequency (sampling frequency) f9 (f, = fi in this embodiment), and the phase integrator (2π/2N) m at time 1/f.
get l. This increases the phase integrator's phase increase rate ω.

hair That is, fo=;f.

An output frequency of

That is, if m2 == 1230 continues to be input to the phase integrator by the selector 80, the output frequency f. 2. If υ, m, = 1228 continues to be input, the output frequency f. , Hato becomes. The desired logical signal waveform is outputted from any bit of the register 60, for example, the most significant bit, through the Q terminal.

In the circuit of FIG. 1, the input clock f1 shown in FIG.
is input to the input terminal 10, the D7 lip 70 knob 40 is set every 160th clock. When the D flip-flop 40 is set, the selector 80 becomes m2 =
Outputs 1230. As a result, the phase output of the phase integrator rotates faster than when the input is m, = 1228, and as a result, the output from the register 60 becomes faster and -
! D flip-flop 40 by the output of 9 frequency divider 50
The timing to reset becomes faster.

When the D flip-flop 40 is reset, the selector 80 now selects ml-1228 and outputs it to the phase integrator. As a result, the phase output of the phase integrator is delayed.

After that, when the D flip-flop 30 sets the D flip-flop 40, the selector 80 again sets m2=126.
Select 0. In this way, the circuit shown in FIG. 1 forms a negative stagnation loop. When the above operations are repeated, m,
The selection ratio of and m2 is f. Equilibrium occurs when 15 muro KH2 is obtained, and phase locking occurs when the phase comparison becomes 51.2 KHz and the phase relationship is almost opposite.

As described above, a clock of 155.6 KHz synchronized with the clock of 8192 KHz is generated. In this example, both the input clock and the calculation clock of vCO are 819.
2 KHz and the whole operates completely synchronously, although this is not necessarily a requirement.

Note that K, which inputs two numerical values to the integrator using the selector 80, may be determined as follows. ψ1] For example, 1230
Figure 2 (
It will look like a) and (b). Here, compare the two and check each code! Digits whose numbers correspond and match can be fixedly inputted as they are, and digits where 1 and 0 are inverted can be controlled by an inverter using a control signal from the flip-flop 40.

Therefore, the actual hardware configuration can be made up of one inverter, which simplifies the configuration.

〔Effect of the invention〕

According to the present invention, since an integrator is introduced which performs the VCO function of a pure logic circuit type digital signal processing type, it is possible to obtain a simple and inexpensive digital PLL circuit that does not require an oscillator.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital PLL circuit according to an embodiment of the present invention, and FIGS. 2(a) and (b) are respectively "123
0" and "1228" in binary numbers, Figure 6 is an operation timing chart of the digital PLL circuit shown in Figure 1, Figure 4 is an explanatory diagram of the operation of the integrator, and Figure 5 is a diagram of the PL circuit.
A diagram explaining the principle of the L circuit, Figure 6 is a conventional digital PLL
It is a block diagram of a circuit. 20.50... Frequency divider 30.40... D flip 70 Tub 60... Register 70... Adder

Claims (1)

[Claims] 1. Digital PLL with phase comparator and phase integrator
In the circuit, a phase integrator is configured using an N-bit binary full adder and an N-bit register, and two numerical data are selectively switched and inputted to the phase integrator by the output signal of the phase comparator, and the A digital PLL circuit characterized in that it is configured to output any one bit signal of an N-bit register to the phase comparator as a feedback signal.