JPH01238220A - Variable frequency dividing circuit - Google Patents

Abstract

PURPOSE:To attain a frequency division by a non integer by inverting the lowest position bit of a binary code constituting a frequency dividing ratio setting value for every generation of an output clock signal. CONSTITUTION:An input clock signal is inputted to a counter circuit 1, the counted value is compared with the setting value of a frequency dividing ratio setting means 2 in a comparing means 3. When the counted value coincides with the setting value, a coinciding pulse is outputted from the comparing means 3, this pulse train goes to an output clock signal, the coinciding pulse resets the counter circuit 1 and further is supplied to an inverting circuit 4. The output signal of the inverting circuit 4 is supplied to the comparing means 3 as the least significant bit of the setting value to the comparing means 3. Accordingly, the least significant bit of the setting value goes to a signal in which '1' and '0' are alternately inverted for every generation of the coinciding pulse to alternately repent a N frequency division and a N+1 frequency division. Therefore, the output clock signal goes to a signal obtained by dividing the frequency into N.5 in view of of long period.

Description

[Detailed Description of the Invention] [Summary] Regarding a variable frequency divider circuit that divides an input clock signal to generate a clock signal of a predetermined frequency, the present invention relates to a variable frequency divider circuit that divides an input clock signal to generate a clock signal of a predetermined frequency. It has a counter circuit that counts input clock signals, and comparison means that compares the count value of this counter circuit and the setting value of the division ratio setting means and generates an output signal when they match. , the set value is composed of a plurality of bits of binary code, and the least significant bit of the binary code is configured to be an output signal of an inverting circuit that is inverted every time the output signal is generated.

[Industrial application field]

The present invention relates to a variable frequency divider circuit that divides an input clock signal to generate a clock signal of a predetermined frequency.

[Conventional technology]

Figure 3 shows DPL L (Digital Pha
2 is a block diagram of the se-LockedLoop) circuit, which is composed of a phase comparator 10, a main oscillator 11, a clock switch 12, and a frequency divider 13. Now, the entrance signal s1
When a clock signal with a predetermined frequency is supplied to the phase comparator 10, the phase comparator 10 converts the level to "1" or "0" by a logical operation between the input signal S1 and the feedback signal S2 from the frequency dividing circuit 13. The clock switch 12 generates an output signal S3.
C is divided by two to generate two signals whose phases are shifted by 180 degrees, and one of the signals is taken out as the signal S4 depending on the level "1° or °0" of the signal S3. Signal S
4 is frequency-divided by a frequency divider 13 consisting of an M-stage counter and fed back to the phase comparator 10.

Therefore, the ratio between the level "1'" and the level "0°" of the signal S3 changes depending on the phase relationship between the input signal Sl and the feedback signal S2, and the frequency and phase of the feedback signal S2 match those of the input signal S1. controlled to do so.

[Problem to be solved by the invention]

By the way, in such a conventional example, since the frequency division ratio of the frequency divider 13 is an integer value, there is no problem as long as the ratio between the frequency of the master clock MC and the frequency of the input signal S1 is an integer value. However, when the value is a non-integer value, the master clock is divided by the nearest integer value, so the phases of the input signal S1 and feedback signal S2 do not match, and the amount of jitter in the output signal S3 of the phase comparator 10 increases. There was a problem.

An object of the present invention is to generate a clock signal having a frequency that cannot be obtained by integer frequency division of an input clock signal.

[Means to solve the problem]

As shown in the principle diagram in Figure 1, a counter circuit 1 that counts an input clock signal is compared with the count value of this counter circuit 1 and the set value of the frequency division ratio setting means 2, and when they match, an output signal is generated. The setting value is composed of a plurality of bits of binary code, and the least significant bit of this binary code is the output signal of the inverting circuit 4, which is inverted at each generation timing of the output signal. Configure it so that

[For production]

The input clock signal is input to the counter circuit 1, and its counted value is compared with the set value of the frequency division ratio setting means 2 by the comparison means 3. When the count value and the set value match, the comparison means 3 outputs a matching pulse, and this pulse train becomes the output clock signal. The coincidence pulse resets the counter circuit l,
Furthermore, it is supplied to the inversion circuit 4.

The inversion circuit 4 is composed of a T-type flip-flop that alternately inverts the level "0" and the level "1" each time a coincidence pulse arrives, and its output signal is supplied to the comparison means 3 as the least significant bit of the set value. be done. Therefore, the least significant bit of the set value becomes a signal in which the level "1" and the level "0" are alternately inverted every time a coincidence pulse occurs, and the signal is divided by N and N+1.
Frequency division (N is an integer) is repeated alternately. For this reason,
In the long term, the output clock signal becomes a signal obtained by dividing the input clock signal by N and 5.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of the variable frequency divider circuit according to the present invention, and shows an example in which the present invention is applied to a DPLL circuit. Note that parts corresponding to those in FIGS. 1 and 3 will be described with the same reference numerals.

In FIG. 2, the DPLL circuit detects the phase difference between the input signal s1 and the feedback signal S2 and outputs a binary signal with a level "0".
A phase comparator 1o that outputs a phase difference detection signal S3 with a level of ``1'' or a level of ``1'' and a master clocker MC output from the main oscillator 11 are divided by two to generate two clock signals whose phases are shifted by 180 degrees. However, it is constituted by a closed loop circuit consisting of a clock switch 12 which switches and outputs a signal S4 according to the level of the phase difference detection signal S3, a variable frequency divider circuit 2o according to the present invention, and a fixed frequency divider circuit 13.

The variable frequency divider circuit 20 includes a counter circuit 1 that counts the clock signal s4, and a frequency division ratio setter 2 that sets the frequency division ratio.
, a comparator 3 which compares the counted value of the counter circuit 1 and the set value of the frequency division ratio setter 2 and outputs an output signal S5 when they match, and a T-type filter that is inverted every time this matching pulse S5 arrives. An inverting circuit 4 having a Jyp-flop configuration, and a selector 5 for selecting one of three signals: the output signal of the inverting circuit 4, a fixed signal at level "0", or a fixed signal at level "1". It consists of

In such a configuration, if a signal whose frequency ratio with the master clock MC is a non-integer is input as the input signal S1, the master clock MC is input to the frequency dividing circuit 13.
If the frequency is divided by an integer by 20, the phase comparator 10 outputs a detection signal S3 with a large amount of jitter. At this time, when the selector 5 of the variable frequency divider circuit 20 selects the output signal of the inversion circuit 4, the frequency division ratio setting value input to the comparator 3 is a signal whose least significant bit is inverted every time the one-loss pulse S5 occurs. becomes. For this reason, the variable frequency dividing circuit 20 alternately repeats N frequency division and N+4 frequency division (N is an integer) for each frequency division, and in the long term, performs frequency division by N and 5.

Therefore, as the input signal S1, the master clock MC
Even if a signal with a non-integer frequency ratio is input, a detection signal with a small amount of jitter can be obtained.

In the above embodiment, an example was described in which the present invention is applied to a DPLL circuit, but it is of course possible to apply the present invention not only to this but also to a circuit that divides an input clock signal by a non-integer frequency.

[Effects of the Invention] According to the variable frequency divider circuit of the present invention, the least significant bit of the frequency division ratio setting value is inverted every time an output clock signal is generated, so that N frequency division and N+1 frequency division are alternately performed. In the long term, it becomes possible to perform non-integer frequency division by N5.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of a variable frequency divider circuit according to the present invention, FIG. 2 is a block diagram showing an embodiment in which the variable frequency divider circuit according to the present invention is applied to a DPLL circuit, and FIG. 3 is a diagram showing a conventional DPLL circuit. It is a block diagram. 1... Counter circuit, 2... Frequency division ratio setter, 3...
・Comparator, 4...inverting circuit. Patent applicant Fujitsu Enoki Co., Ltd./IiI Kiri 6 I2-1 Figure 3

Claims (1)

[Claims] In a variable frequency divider circuit comprising a counter circuit that counts input clock signals, and a comparison means that compares the count value of this counter circuit and a setting value of a frequency division ratio setting means and generates an output signal when they match, the setting The value is a multi-bit 2
1. A variable frequency dividing circuit comprising a binary code, wherein the least significant bit of the binary code is an output signal of an inverting circuit that is inverted every time the output signal is generated.