JPS62298147A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To use two kinds of transistors in the same integrated circuit separately, by constituting two kinds of vertical type n-p-n transistors having different depths of collector and base junctions together with complementary MOS transistors. CONSTITUTION:On a p-type semiconductor substrate 101, n-type regions 103, 104 and 105, which are insulated and isolated with a p-type region 102, are formed. Then, a p-type well region 106 of an n-channel MOS transistor (Tr) 121 end a base region 107 of a high withstanding voltage n-p-n Tr 123 are simultaneously formed. After a gate oxide film 108 of a CMOS Tr is grown, a base region 109 of the first kind of a high performance n-p-n Tr is formed. Thereafter source and drain regions and the like are formed. Together with the complementary MOS Trs 120 and 121, a high performance n-p-n Tr 122 having a shallow collector-base junction and the high breakdown strength n-p-n Tr 123 having a deep collector-base junction are formed.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit in which a complementary MOS transistor (hereinafter abbreviated as CMOS transistor) and a vertical NPN are provided on the same semiconductor chip. transistor (hereinafter referred to as NPN)
The so-called bipolar
Regarding CMO8 integrated circuits.

[Conventional technology]

Conventionally, this type of integrated circuit has had a structure as shown in FIG. 4, which is a cross-sectional view. N-type regions 403 and 404 are formed in a P-type semiconductor substrate 401 and are insulated and separated by a P-type region 402 . These n-type regions 403, 4041! Although n-type impurities may be formed by diffusion from the surface or by ion implantation, in high-performance bipolar CMO8 integrated circuits, it is common to grow an n-type epimexial layer on a P-type substrate and remove it from the surface. In some cases, they are formed insulated and separated from each other by diffusion of P-type impurities. P-type well region 4 of next KN channel MOS transistor
05. 0MOS transistor gate oxide film 406.
NPN transistor base region 407. CMOS transistor gate electrode 408. P-type source drain region 409 of P-channel MOS transistor. NPN transistor base contact region 410. N-type source drain region 41) of an N-channel MOS transistor,
NPN transistor n-type contact region 412. NP
1) An emitter region 413 of an N transistor is formed in p-order. Finally, an opening is made in the surface oxide film and the metal electrode 4
14 is provided with F, P channel MO8) run raster 415. N channel MO8) Ranji ball Yu 41
6. NPN) Langimeta 41ft-Bipolar
The element section of the CMO8 integrated circuit is completed.

[Problems that the invention aims to solve]

The conventional bipolar CMO explained above using Fig. 4
In an integrated circuit, in order to improve the performance of an NPN transistor, it is common to make the collector, base junction, and base, emitter junction as shallow as possible to obtain a high /T and hFl t -.

For example, /T of about 4 GHz and h yxk of about 100
In order to obtain a collector of about 0.3μ, base junction and 0.
．． Emitter and base junctions of approximately 15μ grooves are required.

NPN transistors having such shallow collector, base junctions, and base/emitter junctions are indispensable for circuit parts that require high-speed operation, such as logic operation parts, but they have a low emitter-base breakdown voltage (about -60,000 mm). BVzno
) and a low collector-base breakdown voltage of around 8V (BY.,.

). In addition, because of its high speed and high amplification properties, it responds excessively to external surge voltages.
Another drawback is that the transistor itself is easily destroyed by the large current flowing in a short period of time. The fact that the bond is shallow also contributes to its tendency to break due to alloy spikes and the like.

[Means for solving problems]

A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit comprising a complementary MOS transistor and a vertical NPN transistor, in which two types of vertical NPN transistors having different collector and base junction depths are configured. It is characterized by

Further, in one embodiment of the present invention, the base regions of the two types of vertical NPN transistors are formed simultaneously with the P type region of the N-channel MOS transistor, and each of the two types of vertical NPN transistors is The emitter region of is formed simultaneously with the N-type source and drain regions of the N-channel MOS transistor.

〔Example〕

Next, the present invention will be explained with reference to all the drawings.

FIG. 1 is a sectional view of an element portion of a semiconductor integrated circuit according to an embodiment of the present invention. P type semiconductor substrate 101 VCP type region 1
N-type region 103°104.105 isolated by 02
Next, the P-type well region 106 of the 1cN-channel MOS transistor and the base region 107' of the second type of high-voltage NPN transistor are formed at the same time. Next, after growing a gate oxide film 108 of a CMOS transistor, a base region 109 of a first type of high performance NPN transistor is formed. From now on, the gate L gate of the CMO3 transistor z4x 10. P-type source and drain regions of p-channel MOS transistor 1)1. After forming the base contact regions 1) 2, 1) 3 of the NPN transistor, the N-type source of the N-channel MOS transistor,
Drain region 1)4. First type and second type of NP
The emitter regions 1) 5, 1) 6 and the collector contact regions 1) 7, 1) 8 of the N transistor are formed at the same time. Finally, an opening is made in the surface oxide film, and the metal electrode 1)
9, P channel MOS transistors 120. N-channel MOS transistor 121
, a fourth type of high performance NPN transistor 122. with a shallow collector-base junction. A second type of high-voltage NPN transistor 123 with a deep collector-base junction
is composed of.

In the structure described above using FIG. 1, the first type of high-performance NPN transistor has an emitter-base junction depth of 0.15 μm and a collector-base junction depth of 0.3 μm.
The second type of high-voltage NPN transistor has an emitter of 3t, h-x.
The depth of the junction is 0.16 μm The depth of the collector base junction is 10/Jm, /? is 500 MHz.

It becomes possible to form the film so that hFl is approximately 2c. - Regarding the emitter-base breakdown voltage BV0°, in the first type of high-performance NPN transistor, the emitter,
Since the base junction k is formed in a concentration region of about 10 atms/-, the voltage is about 5V, but the second type of high breakdown voltage N
In a PN transistor, the collector-base junction f
Since it is formed in a concentration region of about 1017 a jm%/i-, it is possible to set the voltage to about 10V.

Next, as a first application example of the integrated circuit according to the present invention, a case where the integrated circuit is applied to a three-state TTL output circuit will be explained using the second diagram. Figure 2 is a circuit diagram of the final stage of the frame TTL output circuit, and the input terminal 2 is connected from other circuits of the chip circle.
01, 202 and output terminal 2o3 output to the outside of the chip
．． The resistor 204, the first type of high-performance NPN transistor 205 and the second type of high-voltage NPN explained in FIG.
It consists of a transistor 206. In Fig. 2, the input terminal 201) has the hjgh level, and the input terminal 202 has the L level.
When ow level is input, NPN transistor 2
05 is the operating state, and the NPN) range inverter 206 enters the cut-off state and outputs a Low level to the output terminal 203. In addition, the input terminal 201 has a low level, and the input terminal 202
When a high level is input to NPN transistor 2
05 is in the cut-off state, the NPN transistor 206 is in the operating state, and a high level is output to the output terminal 203. In addition, both input terminals 201 and 202 (7) are VcL.
When the OW level is input, any number of NPN transistors will be in the cutoff state, and the output terminal 203Hhigh
h impedance state. Here, it is expected that the output terminal 203 is connected to the output terminal of another chip with the pass line fully open, and that the output terminal 203 maintains a high impedance state even if the power supply VDD of the own chip becomes the GND level. There may be cases.

However, at this time, when the output terminal 203 is at high level, 3V is applied to the emitter and collector of the NPN transistor 206.
A voltage of ~4■ will be applied. Emitter-collector breakdown voltage BVi+ool of NPN transistor (This is the voltage determined by hPl in the opposite direction to the base-emitter breakdown voltage BYIBO of the transistor, and usually shows the lowest value among the breakdown voltages of transistors, in the case of the first type of high-performance NPN transistor. The base emitter breakdown voltage BVIIBO is about 5■,
Emitter collector breakdown voltage BVioot'j1. even lower 3
In the above condition, the H level of the output terminal is approximately V.
i g h impedance state cannot be maintained. -1 The base-emitter breakdown voltage BYIBO of the second type of high-voltage NPN transistor is about IOV, so it is possible to obtain an emitter-collector breakdown voltage BVoxo t- of 5μ or more. Therefore, by using the second type of high-voltage NPN transistor having the deep collector-base junction shown in FIG. 1 only for the VcNPN transistor 206 as shown in the second section, the performance of other circuit parts can be improved without deteriorating the performance of other circuit parts. The high impedance state of the output can be maintained in any state of the integrated circuit.

Next, as a second application example of the present invention, the present invention? The case where it is applied to the input circuit section is shown. In FIG. 3, the P-channel MO8) raster 303, the N-channel MO8 transistors 304, 305, the first type of high-performance NPN transistor 306, 307, and the resistor 308 are the input terminal 3.
01t-Input terminal from outside the chip, output terminal 302'
This constitutes an input inverter circuit that serves as an output terminal to the inside of the chip. Further, the second type NPN transistor 309 having a deep base-collector junction and the resistor 310 constitute an electrostatic protection circuit based on the operating principle described below. When a negative surge voltage is applied to the external input terminal 301, a PN diode composed of an n-type collector region and a P-type substrate of the transistor 309 becomes forward-oriented, and the surge charge is discharged through this PN diode. When a positive surge voltage higher than the collector-base withstand voltage BVoao of the NPN transistor 309 is applied to the - external input terminal 301,
The leakage current flowing through the resistor 310 causes the NPN transistor 309 to operate in the forward direction Vc, and the surge 'load is discharged. Therefore, the performance of this N P N transistor 309 needs to be high enough to absorb surge charges, but if the performance is too high, it may be destroyed due to the charge energy it absorbs. There is. In fact, if the first type of high-performance transistor with a shallow junction is used as the NPN transistor 309,
It is destroyed by electrostatic energy charged with a voltage of about +200V to a capacitance of about 200PF connected to the input.

Therefore, as fc shown in FIG. 3, the junction is relatively deep as an NPN transistor for electrostatic protection, and fT, hFl
By using the second type of high-voltage NPN transistor/transistor with relaxed performance such as 1, it becomes possible to construct a power protection circuit having a high breakdown voltage.

〔Effect of the invention〕

As explained above, in an integrated circuit comprising a μ, 0 MOS transistor, an NPN transistor, and a tA according to the present invention, 29 NPN transistors having different collector and base junction depths are used.
There are two things that need to be done to configure a transistor.
−1 base region of the seed NPN transistor iN type MO
By simultaneously forming the P-well region of the S transistor, the emitter region of each of the two types of NPN transistors, and the source/drain region of the N-channel MOS transistor, a shallow junction can be achieved without increasing the number of steps. a first type of high performance NPN transistor;
High withstand voltage with deep junction, destroys against surge voltage.
This has the effect of making it possible to use the second type of high-voltage N P N transistor, which is difficult to use, in the same integrated circuit.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of an integrated circuit according to an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram showing a first application example of the invention, and Fig. 3 is an equivalent circuit diagram showing a second application example of the invention. FIG. 4 is a sectional view of a conventional integrated circuit. 101.401--P-type semiconductor substrate, 102°402--P rejection edge region, 103,104,
105°403, 404-”-n type region, IQ 6
．． 405--P-type well region, 107, 109
,407... base area, 108,406...
... Gate oxide film, 1) 0, 408 --- Gate electrode, 1) 1,409 ... P-type source, drain region, 1) 2, 1) 3° 410 --- ...Base contact region, 1)4.41)...N-type base, drain region, 1)5,1)6゜413...
Emitter region, 1) 7, 1) 8, 412... Collector contact region, 1) 9, 414... Metal electrode, 120, 303, 415... P channel MOS Transistor, 121,304,305°4
16...--N channel MOS transistor, 1
22123.205, 206, 306, 307, 309
゜417・-・・・NPN transistor, 204,3
08゜310・・・Resistance, 201,202,30
1... Input terminal, 203, 302...
Output terminal. Agent: Susumu Uchihara, patent attorney: Figure 3

Claims (2)

[Claims] (1) A semiconductor integrated circuit comprising a complementary MOS transistor and a vertical NPN transistor, characterized in that two types of vertical NPN transistors having different collector and base junction depths are configured. integrated circuit. (2) A patent characterized in that the base region of one of the two types of vertical NPN transistors, the emitter region of each of the N-channel NPN transistors, and the N-type source drain region of the N-channel MOS transistor are formed at the same time. A semiconductor integrated circuit according to claim (1).