JPS62298147A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS62298147A
JPS62298147A JP14235586A JP14235586A JPS62298147A JP S62298147 A JPS62298147 A JP S62298147A JP 14235586 A JP14235586 A JP 14235586A JP 14235586 A JP14235586 A JP 14235586A JP S62298147 A JPS62298147 A JP S62298147A
Authority
JP
Japan
Prior art keywords
type
base
transistor
region
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14235586A
Other languages
Japanese (ja)
Inventor
Hiroshi Nakashiba
中柴 洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14235586A priority Critical patent/JPS62298147A/en
Publication of JPS62298147A publication Critical patent/JPS62298147A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To use two kinds of transistors in the same integrated circuit separately, by constituting two kinds of vertical type n-p-n transistors having different depths of collector and base junctions together with complementary MOS transistors. CONSTITUTION:On a p-type semiconductor substrate 101, n-type regions 103, 104 and 105, which are insulated and isolated with a p-type region 102, are formed. Then, a p-type well region 106 of an n-channel MOS transistor (Tr) 121 end a base region 107 of a high withstanding voltage n-p-n Tr 123 are simultaneously formed. After a gate oxide film 108 of a CMOS Tr is grown, a base region 109 of the first kind of a high performance n-p-n Tr is formed. Thereafter source and drain regions and the like are formed. Together with the complementary MOS Trs 120 and 121, a high performance n-p-n Tr 122 having a shallow collector-base junction and the high breakdown strength n-p-n Tr 123 having a deep collector-base junction are formed.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔産業上の利用分野〕 本発明に半導体集積回路に関し、特に同一半導体チップ
上に相補型MOSトランジスタ(以下CMOSトランジ
スタと略す)と縦型NPN トランジスタ(以下NPN
トランジスタと略す)が共存している所謂バイポーラ・
CMO8集積回路に関する。
[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit in which a complementary MOS transistor (hereinafter abbreviated as CMOS transistor) and a vertical NPN are provided on the same semiconductor chip. transistor (hereinafter referred to as NPN)
The so-called bipolar
Regarding CMO8 integrated circuits.

〔従来の技術〕[Conventional technology]

従来、この種の集積回路に第4図にその断面図をもって
示す構造となっていた。P型半導体基板401にP型領
域402で絶縁分離さ几たn型領域403,404が形
成さ几ている。これらn型領域403,4041!n型
不純物の表面からの拡散またはイオンインプランテーク
1ンによって形成ざnる場合もあるが、高性能バイポー
ラ−CMO8集積回路においてに通常P型基板上にn型
エピメキシャル層を成長させ、表面からのP型不純物の
拡散によジ互いに絶縁分離して形成する場合もある。次
KNチャンネルMOSトランジスタのP型ウェル領域4
05. 0MOSトランジスタのゲート酸化膜406.
NPNトランジスタのベース領域407.CMOSトラ
ンジスタのゲート電極408.PチャンナルMOSトラ
ンジスタのP型ソースドレイン領域409.NPNトラ
ンジスタのベースコンタクト領域410.Nチャンネル
MOSトランジスタのN型ソースドレイン領域41)、
NPNトランジスタのn型コンタクト領域412.NP
Nトランジスタのエミッタ領域413が1)p次形成さ
れる。最後に表面酸化膜に開口部が開けられ金属電極4
14が設けらnることにエフ、PチャンネルMO8)ラ
ンラスタ415.NチヤンネルMO8)ランジ玉夕41
6.NPN)ランジメタ41フt−有するバイポーラ・
CMO8集積回路の素子部が完成する。
Conventionally, this type of integrated circuit has had a structure as shown in FIG. 4, which is a cross-sectional view. N-type regions 403 and 404 are formed in a P-type semiconductor substrate 401 and are insulated and separated by a P-type region 402 . These n-type regions 403, 4041! Although n-type impurities may be formed by diffusion from the surface or by ion implantation, in high-performance bipolar CMO8 integrated circuits, it is common to grow an n-type epimexial layer on a P-type substrate and remove it from the surface. In some cases, they are formed insulated and separated from each other by diffusion of P-type impurities. P-type well region 4 of next KN channel MOS transistor
05. 0MOS transistor gate oxide film 406.
NPN transistor base region 407. CMOS transistor gate electrode 408. P-type source drain region 409 of P-channel MOS transistor. NPN transistor base contact region 410. N-type source drain region 41) of an N-channel MOS transistor,
NPN transistor n-type contact region 412. NP
1) An emitter region 413 of an N transistor is formed in p-order. Finally, an opening is made in the surface oxide film and the metal electrode 4
14 is provided with F, P channel MO8) run raster 415. N channel MO8) Ranji ball Yu 41
6. NPN) Langimeta 41ft-Bipolar
The element section of the CMO8 integrated circuit is completed.

〔発明が解決し工すとする問題点〕[Problems that the invention aims to solve]

以上第4図を用いて説明した従来のバイポーラ・CMO
8集積回路においては、NPNトランジスタを高性能化
する為に、コレクタ、ベース接合及びベース、エミッタ
接合を可能な限り浅くし高い/TとhFl t−得工う
とするのが一般的である。
The conventional bipolar CMO explained above using Fig. 4
In an integrated circuit, in order to improve the performance of an NPN transistor, it is common to make the collector, base junction, and base, emitter junction as shallow as possible to obtain a high /T and hFl t -.

例えば4 GHz程度の/Tと100程度のh yxk
得る為には0.3μ鴬程度のコレクタ、ベース接合と0
.15μ溝程度のエミッタ、ベース接合が必要とさ几る
For example, /T of about 4 GHz and h yxk of about 100
In order to obtain a collector of about 0.3μ, base junction and 0.
.. Emitter and base junctions of approximately 15μ grooves are required.

かかる浅いコレクタ、ベース接合及びベース、エミッタ
接合を有するNPNトランジスタは論理動作部分等の高
速動作全必要とする回路部分には欠かせぬものであるが
、−万6■程度の低いエミッタベース耐圧(BVzno
)及び8v程度の低いコレクタベース耐圧(BY。、。
NPN transistors having such shallow collector, base junctions, and base/emitter junctions are indispensable for circuit parts that require high-speed operation, such as logic operation parts, but they have a low emitter-base breakdown voltage (about -60,000 mm). BVzno
) and a low collector-base breakdown voltage of around 8V (BY.,.

)となる。またその高速性、高増幅性等の性質を有する
が故に、外部からのサージ電圧に対し過度に応答して、
トランジスタ自身が短時間に流す大電流に工って破壊さ
n易いという欠点も有する。接合が浅いという点も、ア
ロイスパイク等の原因にエフ、この破壊さn易い性質を
助長している。
). In addition, because of its high speed and high amplification properties, it responds excessively to external surge voltages.
Another drawback is that the transistor itself is easily destroyed by the large current flowing in a short period of time. The fact that the bond is shallow also contributes to its tendency to break due to alloy spikes and the like.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体集積回路は、相補型MOSトランジスタ
と縦型NPN トランジスタとを具備してなる半導体集
積回路において、コレクタ、ベース接合の深さが異なる
2種の縦型NPNトランジスタが構成されていることを
特徴とする。
A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit comprising a complementary MOS transistor and a vertical NPN transistor, in which two types of vertical NPN transistors having different collector and base junction depths are configured. It is characterized by

また本発明の1つの実施態様においては前記2種の縦型
NPNトランジスタの一万のベース領域がNチャンネル
MOSトランジスタのP型りエル領域と同時に形成され
、且つ前記2種の縦型NPNトランジスタ各々のエミッ
タ領域が、NチャンネルMOSトランジスタのN型ソー
ス、ドレイン領域と同時に形成される。
Further, in one embodiment of the present invention, the base regions of the two types of vertical NPN transistors are formed simultaneously with the P type region of the N-channel MOS transistor, and each of the two types of vertical NPN transistors is The emitter region of is formed simultaneously with the N-type source and drain regions of the N-channel MOS transistor.

〔実施例〕〔Example〕

次に、本発明について図面全参照して説明する。 Next, the present invention will be explained with reference to all the drawings.

第1図は本発明の一実施例の半導体集積回路の素子部分
の断面図である。P型半導体基板101VCP型領域1
02で絶縁分離されたn型領域103゜104.105
が形成きnるゆ次1cNチャンネルMOSトランジスタ
のP型ウェル領域106と第2の種類の高耐圧NPNト
ランジスタのベース領域107’を同時に形成する。次
にCMOSトランジスタのゲート酸化膜108に成長さ
せた後、第一の種類の高性能NPNトランジスタのベー
ス領域109を形成する。以降、CMO3トランジスタ
のゲーLトz4x 10.pチャンネルMOSトランジ
スタのP型ソース、ドレイン領域1)1.NPNトラン
ジスタのベースコンタクト領域1)2,1)3を形成し
た後、NチャンネルMOSトランジスタのN型ソース、
ドレイン領域1)4.第1の種類及ヒ第2の種類のNP
Nトランジスタのエミッタ領域1)5,1)6及びコレ
クタコンタクト領域1)7.1)8が同時に形成される
。最後に表面酸化膜に開口部が開けられ、金属電極1)
9が設けられることに工り、PチャンネルMOSトラン
ジスタ120.NチャンネルMOSトランジスタ121
、浅いコレクタベース接合を有する第4の種類の高性能
NPN トランジスタ122.深いコレクタベース接合
を有する第2の種類の高耐圧NPNトランジスタ123
が構成さnる。
FIG. 1 is a sectional view of an element portion of a semiconductor integrated circuit according to an embodiment of the present invention. P type semiconductor substrate 101 VCP type region 1
N-type region 103°104.105 isolated by 02
Next, the P-type well region 106 of the 1cN-channel MOS transistor and the base region 107' of the second type of high-voltage NPN transistor are formed at the same time. Next, after growing a gate oxide film 108 of a CMOS transistor, a base region 109 of a first type of high performance NPN transistor is formed. From now on, the gate L gate of the CMO3 transistor z4x 10. P-type source and drain regions of p-channel MOS transistor 1)1. After forming the base contact regions 1) 2, 1) 3 of the NPN transistor, the N-type source of the N-channel MOS transistor,
Drain region 1)4. First type and second type of NP
The emitter regions 1) 5, 1) 6 and the collector contact regions 1) 7, 1) 8 of the N transistor are formed at the same time. Finally, an opening is made in the surface oxide film, and the metal electrode 1)
9, P channel MOS transistors 120. N-channel MOS transistor 121
, a fourth type of high performance NPN transistor 122. with a shallow collector-base junction. A second type of high-voltage NPN transistor 123 with a deep collector-base junction
is composed of.

以上第1図を用いて説明した構造において第1の種類の
高性能NPNトランジスタはエミッタベース接合の深さ
が0.15μ惟、コレクタベース接合の深さが0.3p
m、1丁が4GH2,h、1が100程度に、第2の種
類の高耐圧NPNトランジスタはエミッ3t 、ヘ−x
 接合の深さが0.16μ町 コレクタベース接合の深
さが10/Jm、  /?が500 MHz。
In the structure described above using FIG. 1, the first type of high-performance NPN transistor has an emitter-base junction depth of 0.15 μm and a collector-base junction depth of 0.3 μm.
The second type of high-voltage NPN transistor has an emitter of 3t, h-x.
The depth of the junction is 0.16 μm The depth of the collector base junction is 10/Jm, /? is 500 MHz.

hFlが2c程度になるよう形成することが可能となる
。−万エミッタベース耐圧BV0゜に関しては第1の種
類の高性能NPNトランジス掲においてに、エミッタ、
ベース接合k 10  atms/−程度の濃度領域で
形成する為に5V程度となるが、第2の種類の高耐圧N
PN トランジスタにおいてに、コレクタベース接合f
 1017 a jm%/i−程度の濃度領域で形成す
る為に10v程度にすることが可能となる。
It becomes possible to form the film so that hFl is approximately 2c. - Regarding the emitter-base breakdown voltage BV0°, in the first type of high-performance NPN transistor, the emitter,
Since the base junction k is formed in a concentration region of about 10 atms/-, the voltage is about 5V, but the second type of high breakdown voltage N
In a PN transistor, the collector-base junction f
Since it is formed in a concentration region of about 1017 a jm%/i-, it is possible to set the voltage to about 10V.

次に本発明による集積回路の第1の応用例として3ステ
ート型のTTL出力回路に応用し几場合を第2図音用い
て説明する。第2図框TTL出力回路の最終段の回路図
であり、チップ円の他の回路から接続される入力端子2
01,202とチップ外部に出力される出力端子2o3
.抵抗204及び第1図で説明した第1の種類の高性能
NPNトランジスタ205と第2の種類の高耐圧NPN
トランジスタ206とからなる。第2図において、入力
端子201)c hjghレベル、入力端子202にL
ow  レベルが入力さnた時、NPNトランジスタ2
05が動作状態、NPN)ランジンタ206がカットオ
フ状態となり出力端子203にLowレベルを出力する
。また入力端子201にLowレベル、入力端子202
にhighレベルが入力さnた時NPNトランジスタ2
05がカットオフ状態、NPN トランジスタ206が
動作状態となり出力端子203にhighレベルが出力
づ几る。また入力端子201,202(7)両方VcL
OW レベルが入力さnた場合、何nのNPNトランジ
スタもカットオフ状態となり、出力端子203Hhig
hインピーダンス状態となる。ここで出力端子203が
他チップの出力端子とパスライン全弁して接続され、且
つ自身のチップの電源VDDがGNDレベルとなっても
出力端子203がhighインピーダンス状態を保つこ
とを期待さ九ている場合がある。
Next, as a first application example of the integrated circuit according to the present invention, a case where the integrated circuit is applied to a three-state TTL output circuit will be explained using the second diagram. Figure 2 is a circuit diagram of the final stage of the frame TTL output circuit, and the input terminal 2 is connected from other circuits of the chip circle.
01, 202 and output terminal 2o3 output to the outside of the chip
.. The resistor 204, the first type of high-performance NPN transistor 205 and the second type of high-voltage NPN explained in FIG.
It consists of a transistor 206. In Fig. 2, the input terminal 201) has the hjgh level, and the input terminal 202 has the L level.
When ow level is input, NPN transistor 2
05 is the operating state, and the NPN) range inverter 206 enters the cut-off state and outputs a Low level to the output terminal 203. In addition, the input terminal 201 has a low level, and the input terminal 202
When a high level is input to NPN transistor 2
05 is in the cut-off state, the NPN transistor 206 is in the operating state, and a high level is output to the output terminal 203. In addition, both input terminals 201 and 202 (7) are VcL.
When the OW level is input, any number of NPN transistors will be in the cutoff state, and the output terminal 203Hhigh
h impedance state. Here, it is expected that the output terminal 203 is connected to the output terminal of another chip with the pass line fully open, and that the output terminal 203 maintains a high impedance state even if the power supply VDD of the own chip becomes the GND level. There may be cases.

ところがこの時、出力端子203がhighレベルの時
NPNトランジスタ206のエミッタ、コレクタに3v
〜4■の電圧が加わることになる。NPNトランジスタ
のエミッタコレクタ耐圧BVi+ool(トランジスタ
のベースエミッタ耐圧BYIBOと逆方向のhPlで決
する電圧であり、通常、トランジスタの耐圧の中で最も
低い値を示す、第1の種類の高性能NPNトランジスタ
の場合にベースエミッタ耐圧BVIIBOは5■程度、
エミッタコレクタ耐圧BVioot’j1.更に低く3
V程度となる為に、上述の状態において、出力端子のH
i g hインピーダンス状態が保てなくなる。−1第
2の種類の高耐圧NPN トランジスタのベースエミッ
タ耐圧BYIBOはIOV程度あり従って5■以上のエ
ミッタコレクタ耐圧BVoxo  t−得ることが出来
る。従って第2崗で示したようVcNPNトランジスタ
206にのみ第1図で示した深いコレクタベース接合を
有する第2の種類の高耐圧NPNトランジスタを用いる
ことにより、他の回路部分の性能を下げることなく、集
積回路の如何なる状態においても出力のHi g hイ
ンピーダンス状態を保つことが出来る。
However, at this time, when the output terminal 203 is at high level, 3V is applied to the emitter and collector of the NPN transistor 206.
A voltage of ~4■ will be applied. Emitter-collector breakdown voltage BVi+ool of NPN transistor (This is the voltage determined by hPl in the opposite direction to the base-emitter breakdown voltage BYIBO of the transistor, and usually shows the lowest value among the breakdown voltages of transistors, in the case of the first type of high-performance NPN transistor. The base emitter breakdown voltage BVIIBO is about 5■,
Emitter collector breakdown voltage BVioot'j1. even lower 3
In the above condition, the H level of the output terminal is approximately V.
i g h impedance state cannot be maintained. -1 The base-emitter breakdown voltage BYIBO of the second type of high-voltage NPN transistor is about IOV, so it is possible to obtain an emitter-collector breakdown voltage BVoxo t- of 5μ or more. Therefore, by using the second type of high-voltage NPN transistor having the deep collector-base junction shown in FIG. 1 only for the VcNPN transistor 206 as shown in the second section, the performance of other circuit parts can be improved without deteriorating the performance of other circuit parts. The high impedance state of the output can be maintained in any state of the integrated circuit.

次に本発明の第2の応用例として、本発明?入力回路部
分に応用した場合を示す。第3図においてPチャンネル
MO8)うyラスタ303と、NチャンネルMO8トラ
ンジスタ304,305と第1の種類の高性能NPNト
ランジスタ306゜307と抵抗308とは入力端子3
01t−チップ外部からの入力端子、出力端子302’
にチップ内部への出力端子とする入力インバータ回路を
構成している。また第2の種類の深いベースコレクタ接
合を有するNPNトランジスタ309と抵抗310とは
以下に述べる動作原理により静電保護回路を構成してい
る。外部入力端子301に負のサージ電圧が加わるとト
ランジスタ309のn型コレクタ領域とP型基板とで構
成さnるPNダイオードが順方向となり、このPNダイ
オードを介しサージ電荷が放電ざnる。−号外部入力端
子301にNPNトランジスタ309のコレクタベース
耐圧BVoao  以上の正のサージ電圧が加わると、
抵抗310を介して流几るリーク電流にニジNPNトラ
ンジスタ309が順方向Vc動作しサージ′町荷が放電
される。従ってこのN P N トランジスタ309の
性能にサージ電荷を吸収するに十分な程度高い必要があ
るが、−万過度に高性能であると自分自身が吸収する電
荷エネルギーの為に自身が破壊される場合がある。事実
、NPNトランジスタ309として、浅い接合を有する
高性能な第一の種類の高性能トランジスタを用いると、
入力に接続された200PF程度の容量に+200v程
度の電圧で充電さ几た静電エネルギーで、破壊さ几る。
Next, as a second application example of the present invention, the present invention? The case where it is applied to the input circuit section is shown. In FIG. 3, the P-channel MO8) raster 303, the N-channel MO8 transistors 304, 305, the first type of high-performance NPN transistor 306, 307, and the resistor 308 are the input terminal 3.
01t-Input terminal from outside the chip, output terminal 302'
This constitutes an input inverter circuit that serves as an output terminal to the inside of the chip. Further, the second type NPN transistor 309 having a deep base-collector junction and the resistor 310 constitute an electrostatic protection circuit based on the operating principle described below. When a negative surge voltage is applied to the external input terminal 301, a PN diode composed of an n-type collector region and a P-type substrate of the transistor 309 becomes forward-oriented, and the surge charge is discharged through this PN diode. When a positive surge voltage higher than the collector-base withstand voltage BVoao of the NPN transistor 309 is applied to the - external input terminal 301,
The leakage current flowing through the resistor 310 causes the NPN transistor 309 to operate in the forward direction Vc, and the surge 'load is discharged. Therefore, the performance of this N P N transistor 309 needs to be high enough to absorb surge charges, but if the performance is too high, it may be destroyed due to the charge energy it absorbs. There is. In fact, if the first type of high-performance transistor with a shallow junction is used as the NPN transistor 309,
It is destroyed by electrostatic energy charged with a voltage of about +200V to a capacitance of about 200PF connected to the input.

従って第3図に示しfcように、静電保護用NPNトラ
ンジスタとして比較的深い接合で且つfT、  hFl
l等の性能を緩和させた第2の種類の高耐圧NPNトラ
/ジスタを用いることにより、エフ高い破壊電圧を有す
る靜電保穫回路を構成することが可能となる。
Therefore, as fc shown in FIG. 3, the junction is relatively deep as an NPN transistor for electrostatic protection, and fT, hFl
By using the second type of high-voltage NPN transistor/transistor with relaxed performance such as 1, it becomes possible to construct a power protection circuit having a high breakdown voltage.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明μ、0MOSトランジスタと
NPN トランジスタとtA備してなる集積回路におい
て、コレクタ、ベース接合の深すが異なる29のNPN
 トランジスタを構成することにニジ、かつ、こtら2
種のNPNトランジスタの−1のベース領域iN型MO
SトランジスタのPつエル領域と同時に形成し、2種の
NPNトランジスタの各々のエミッタ領域とNチャンネ
ルMOSトランジスタのソースドレイン領域とに同時に
形成することにより、工程数を増やすことなく、浅い接
合を有する第1の種類の高性能NPNトランジスタと、
深い接合を有する高耐圧でサージ電圧に対して破壊さn
難い第2の種類の高耐圧N P Nトランジスタとを同
一集積回路内で使い分けることを可能にする効果がある
As explained above, in an integrated circuit comprising a μ, 0 MOS transistor, an NPN transistor, and a tA according to the present invention, 29 NPN transistors having different collector and base junction depths are used.
There are two things that need to be done to configure a transistor.
−1 base region of the seed NPN transistor iN type MO
By simultaneously forming the P-well region of the S transistor, the emitter region of each of the two types of NPN transistors, and the source/drain region of the N-channel MOS transistor, a shallow junction can be achieved without increasing the number of steps. a first type of high performance NPN transistor;
High withstand voltage with deep junction, destroys against surge voltage.
This has the effect of making it possible to use the second type of high-voltage N P N transistor, which is difficult to use, in the same integrated circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の集積回路の断面図、第2図
は本発明の第1の応用例を示す等価回路図、第3図に本
発明の第2の応用例を示す等価回路図、第4図に従来の
集積回路の断面図である。 101.401−・・・・・P型半導体基板、102゜
402−−−−−− P拒絶縁領域、103,104,
105゜403、 404−”−n型領域、I Q 6
. 405−・・・−P型ウェル領域、107,109
,407・・・・・・ベース領域、108,406・・
・・・・ゲート酸化膜、1)0、 408・−・−ゲー
ト電極、1)1,409・・・・・・P型ソース、ドレ
イン領域、1)2,1)3゜410・−・・・ベースコ
ンタクト領域、1)4.41)・−・・・・n型ンース
、ドレイン領域、1)5,1)6゜413・・・・・・
エミッタ領域、1)7,1)8,412・・・−・・コ
レクタコンタクト領域、1)9,414・・・・・・金
属電極、120,303,415・・・・・・Pチャン
ネルMOSトランジスタ、121,304,305゜4
16・・−・・−NチャンナルMOSトランジスタ、1
22123.205,206,306,307,309
゜417・−・・−・NPNトランジスタ、204,3
08゜310・・・・−・抵抗、201,202,30
1・・・・・・入力端子、203,302・−・・・・
出力端子。 代理人 弁理士  内 原   晋 : 予3図
Fig. 1 is a cross-sectional view of an integrated circuit according to an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram showing a first application example of the invention, and Fig. 3 is an equivalent circuit diagram showing a second application example of the invention. FIG. 4 is a sectional view of a conventional integrated circuit. 101.401--P-type semiconductor substrate, 102°402--P rejection edge region, 103,104,
105°403, 404-”-n type region, IQ 6
.. 405--P-type well region, 107, 109
,407... base area, 108,406...
... Gate oxide film, 1) 0, 408 --- Gate electrode, 1) 1,409 ... P-type source, drain region, 1) 2, 1) 3° 410 --- ...Base contact region, 1)4.41)...N-type base, drain region, 1)5,1)6゜413...
Emitter region, 1) 7, 1) 8, 412... Collector contact region, 1) 9, 414... Metal electrode, 120, 303, 415... P channel MOS Transistor, 121,304,305°4
16...--N channel MOS transistor, 1
22123.205, 206, 306, 307, 309
゜417・-・・・NPN transistor, 204,3
08゜310・・・Resistance, 201,202,30
1... Input terminal, 203, 302...
Output terminal. Agent: Susumu Uchihara, patent attorney: Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)相補型MOSトランジスタと縦型NPNトランジ
スタとを具備してなる半導体集積回路において、コレク
タ、ベース接合の深さが異なる2種類の縦型NPNトラ
ンジスタが構成されていることを特徴とする半導体集積
回路。
(1) A semiconductor integrated circuit comprising a complementary MOS transistor and a vertical NPN transistor, characterized in that two types of vertical NPN transistors having different collector and base junction depths are configured. integrated circuit.
(2)前記2種類の縦型NPNトランジスタの一方のベ
ース領域とNチャンネルのNPNトランジスタの各々の
エミッタ領域とNチャンネルMOSトランジスタのN型
ソースドレイン領域とが同時に形成されることを特徴と
した特許請求の範囲第(1)項記載の半導体集積回路。
(2) A patent characterized in that the base region of one of the two types of vertical NPN transistors, the emitter region of each of the N-channel NPN transistors, and the N-type source drain region of the N-channel MOS transistor are formed at the same time. A semiconductor integrated circuit according to claim (1).
JP14235586A 1986-06-17 1986-06-17 Semiconductor integrated circuit Pending JPS62298147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14235586A JPS62298147A (en) 1986-06-17 1986-06-17 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14235586A JPS62298147A (en) 1986-06-17 1986-06-17 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS62298147A true JPS62298147A (en) 1987-12-25

Family

ID=15313445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14235586A Pending JPS62298147A (en) 1986-06-17 1986-06-17 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS62298147A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0196955A (en) * 1987-10-09 1989-04-14 Hitachi Ltd Semiconductor device and manufacture thereof
JPH02199867A (en) * 1989-01-27 1990-08-08 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0196955A (en) * 1987-10-09 1989-04-14 Hitachi Ltd Semiconductor device and manufacture thereof
JPH02199867A (en) * 1989-01-27 1990-08-08 Nec Corp Semiconductor device

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