JPH02199867A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the degree of freedoms of designing an analog/digital hybrid Bi-CMOS integrated circuit by placing in mixture a bipolar transistor having high voltage resistance and high linearity and a bipolar transistor having a high speed on the same semiconductor substrate. CONSTITUTION:A N<+>-type buried layer 2 and a P<+>-type buried layer 3 are formed on the surface of a P-type silicon substrate 1 by an ion implanting method or a thermally diffusing method, an N-type epitaxial layer 4 is then grown, and a P-well 5 is then formed on the surfaces of an N-ch MOSFET region, a base region of a BIP 1 and a junction isolating region by an ion implanting method. In this case, the heat treating time of the P-well is so determined as to electrically connect the P<+>-type buried layer 3 to the P-well 5. Then, a gate oxide film 8, a gate polysilicon 7, a collector N<+>-type diffused region 11, a P-type base diffused region 10, a P<+>-type diffused layer 6 and an N<+>-type diffused layer are completed according to a conventional process. Thus, a P-ch MOSFET, an N-ch MOSFET, a bipolar transistor BIP 1 (for high voltage resistance) and a BIP 2 (for high speed) can be placed in mixture on the P-type silicon substrate 1.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a Bi-CM in which a digital circuit and an analog circuit coexist on the same semiconductor substrate.
Regarding O8 integrated circuits.

[Conventional technology]

Conventionally, this type of digital/analog mixed Bi-CMO
8 integrated circuits, NPN bipolar transistors, N-channel field effect transistors (
(hereinafter abbreviated as N-ch MO8FET), and P-channel field effect transistor (hereinafter abbreviated as P-ch MO8F
Due to limitations on the maximum voltage that can be applied to each element (abbreviated as ET), the following configuration, for example, had to be adopted.

The digital circuit mainly consists of CMOS logic with an operating voltage of 5V, and the analog circuit has a wide voltage range (5V).
It was constructed using NPN bipolar transistors with excellent linearity over the voltage range (V~20V).

Thus, in the manufacturing process of i-CMO3 integrated circuits, the collector-emitter breakdown voltage (B Vc*o) and early voltage (VA
) needs to be increased. To achieve this, as shown in FIG. It was necessary to form the thickness T2 of the P-type base layer 36 of the Bora transistor sufficiently deep to a junction depth of 1.0 to 2.0 μm.

That is, in the conventional B1-10MO8 integrated circuit, a bipolar transistor having almost the same characteristics (high breakdown voltage, high linearity, etc.) is mounted together with the MOSFET.

[Problem to be solved by the invention]

The conventional digital/analog mixed Bi-CMO mentioned above
8 integrated circuits can meet the demands for higher breakdown voltage of NPN bipolar transistors in order to form sufficiently thick N-type epitaxial layers and P-type base layers of NPN bipolar transistors. The configuration was such that it was impossible to satisfy the requirement of having a cutoff frequency ft. However, in recent years, in digital/analog mixed Bi-CMO8 integrated circuits, there are demands for high breakdown voltage and high linearity for the NPN bipolar transistors that make up the analog circuit.
Demand for higher speeds is also increasing, and conventional B
In the i-CMO8 integrated circuit, it has been extremely difficult to simultaneously achieve high breakdown voltage and high speed on the same chip.

〔the purpose〕

The purpose of the present invention is to provide digital/analog mixed Bi-CM
An object of the present invention is to provide a semiconductor device in which a bipolar transistor having high breakdown voltage and high linearity and a bipolar transistor having high speed are mounted on the same semiconductor substrate in an O8 integrated circuit.

[Means to solve the problem]

Digital-analog itB i -CMO8 of the present invention
The integrated circuit is a P-ch MO8FE on the same silicon substrate.
A T, N-ch MO8FET, a high-speed, low-voltage NPN bipolar transistor, and a low-speed, high-voltage NPN bipolar transistor are mounted together.

That is, - on the semiconductor substrate, an N-channel MO8FET
, a Bi-CMO3 integrated circuit in which a P-channel MO8FET and an NPN bipolar transistor are mounted together includes an NPN bipolar transistor having a deep base diffusion layer and an NPN bipolar transistor having a shallow base diffusion layer. At this time, the P-type base layer of the low-speed, high-voltage NPN bipolar is formed together with the P-well layer that constitutes the N-ch MO8FBT, and the low-speed, high-voltage NPN bipolar
The emitter layer of the PN bipolar is formed together with the emitter layer of the high speed, low voltage NPN bipolar or the source/drain region of the N-ch MO8FET.

With such a configuration, in the present invention, bipolar transistors with different characteristics on one chip can be appropriately used as necessary, thereby increasing the degree of freedom in design and easily increasing speed.

〔Example〕

FIG. 1 is a longitudinal sectional view of a first embodiment of the invention.

P-ch MO8FET, N-c on P-type silicon substrate 1
This shows how hMO8FET, bipolar transistors BIPI (for high voltage), and BIP2 (for high speed) are mounted together. That is, in addition to the usual P-ch MO3FET and N-ch MO8FET, the P-type silicon substrate l
Conventional high-voltage type B in which the mold base layer 5 is provided sufficiently deep.
An IPI and a high-speed BIP 2 in which a P-type base diffusion layer 10 is provided shallowly are mounted and formed together. Bi- of the present invention
In the CMO8 integrated circuit, an N+ buried layer 2 is formed on a P-type silicon substrate 1, and then an N-type epitaxial layer 4 is formed to a thickness of 1.
．． A P-ch MO8FET, BIPl, and BIP2 are formed on the surface of the N-type epitaxial layer 4 grown to a thickness of 0 to 2.0 μm, and a P+ buried layer 3 is formed on the P-type silicon substrate 1, and then an N-type epitaxial layer is formed. A P-type impurity such as boron is doped from the surface of the N-type epitaxial layer 4 to form a P-well 5, and an N-chMO8FET is formed on the surface of the P-well 5. At this time, the P well 5 is electrically connected to the P+ buried layer 3, and is also used when separating BIPI and BIP2 by PN junction as shown in FIG.

The gate of P-ch MO8FET has a junction depth of 0.3 to 0.
．． After forming the diffusion layer 6 (source/drain) in the N-type epitaxial layer 4, the thickness is approximately 0.
．． 4 μm N-type gate polysilicon 7 and thickness approx.
The gate oxide film 8 is formed by zero people.

In addition, the gate of N-ch MO8FET has a junction depth of 0.2
~0.3μm N+ diffusion layer 9 (source/drain)
After forming in the well 5, an N-type gate polysilicon oxide film 8 is formed like the N-type gate like the P-ch MO8FET.

The low-speed, high-voltage NPN bipolar transistor BIPI has a P-type base layer with a junction depth of 0.5 to 1.0 μm.
It is formed by forming a P+ diffusion layer 6 as a base electrode connection portion and an N+ diffusion layer 9 as an emitter in the well 5, and providing a collector N+ diffusion layer 1'1 so as to reach the N+ buried layer 2.

On the other hand, high-speed, low-voltage NPN bipolar transistor BI
P2 is a P+ diffusion layer 6 at the base electrode junction part, superimposed on the P type base diffusion layer 10 with a junction depth of 0.3 to 0.5 pm.
N+ is provided as an emitter in the P type base diffusion layer 10.
It is formed by forming a diffusion layer 9 and providing a collector N+ diffusion layer 11 so as to reach the N+ buried layer 2.

The entire manufacturing process of the Bi-CMO8 semiconductor device of the present invention will be briefly described. An N+ buried layer 2 and a P+ buried layer 3 are formed on the surface of a P-type silicon substrate 1 by ion implantation or thermal diffusion, and then an N-type epitaxial layer 4 is formed to a thickness of 1.0 mm.
~2.0 μm growth, then N-ch MO8FET region,
A P well 5 is formed by ion implantation from the surfaces of the base region and junction isolation region of the BIPI. At this time, the heat treatment time for the P well may be determined so that the P+ buried layer 3 and the P well 5 are electrically connected. Next, gate oxide film 8.
Gate polysilicon 7, collector N+ diffusion region 11. P
Mold base diffusion layer 10. The present invention can be realized by forming the P+ diffusion layer 6° and the N+ diffusion layer according to the conventional B1-CMOS process.

In the present invention, the thickness of the N-type epitaxial layer 4 is 1.0 to
Since the depth can be increased to 2.0 μm compared to the conventional one, the cutoff frequency fT of BIP2 is 4 GHz or more, and high-speed operation is possible.

Since the P-well 5 is used in the P-type base layer of B I P 1, the base junction depth is 0.5 to 1.0 μm, making it possible to achieve high breakdown voltage without increasing the manufacturing process. Formable. Furthermore, since the low-speed, high-voltage BIPI and the high-speed, low-thickness BIP2 are mixed on the same silicon substrate, analog-digital mixed Bi-CMO is possible.
3. When designing an integrated circuit, it is possible to use the right materials in the right places, and it also has the advantage of greatly increasing the degree of freedom in circuit design.

In other words, low-speed, high-voltage bipolar transistors BIPI are used in circuits where there is a high possibility that high voltages will be applied, such as protection circuits built into input stages that receive external signals, etc.
By using a high-speed, low-voltage bipolar transistor BIP2 with emphasis on operating speed for circuits that operate on a single power supply, such as internal circuits, the overall breakdown voltage of the Bi-CMO8 integrated circuit is comparable to that of conventional circuits. is maintained, making it possible to speed up circuit operation.

The circuits to which the BIP of the present invention can be applied are not limited to those described above, but can also be applied to circuits that require high-speed operation parts in parts such as the critical path of a linear circuit.

FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. P-ch MO8FET on P-type silicon substrate l.

N-ch MO8FET, BIP 1 (for high voltage resistance).

This figure shows how BIP2 (for high speed) is mixed, and the P-ch MO8FET, N-ch MO8FET, and BIPI are completely the same as in the first embodiment. High-speed, low-voltage NPN bipolar transistor BIP
2 is a P-type base diffusion layer 1 with a junction depth of 0.2 to 0.3 μm.
4. A P+ diffusion layer 6 at the base electrode junction, an emitter with a thickness of about 2,500 mm, and Tabori silicon 12. Emitter and N+ diffusion layer with a junction depth of 0.1 to 0.2 μm 13. It is composed of a gate oxide film 8 and a collector N+ diffusion layer 11. Since the emitter N+ diffusion layer 13 of BIP2 is formed by doping N-type impurities through the emitter polysilicon 12, it is possible to form a shallower emitter junction than in the first embodiment. As a result, the cutoff frequency f of BIP2? is 6~10GHz
reached even faster. On the other hand, BIPI is the first
As in the embodiment, it maintains the characteristic of high voltage resistance, so even if the digital part of the analog/digital mixed Bi-CMO8 integrated circuit becomes faster and more highly integrated, the speed will be lower than at least one part of the analog part. , it is possible to use the high voltage NPN bipolar transistor BIP2, and it is possible to design the right material in the right place as described above.

〔Effect of the invention〕

As explained above, the present invention provides P-chMO8FET,
By mounting an N-ch MO8FET, a high-speed, low-voltage NPN bipolar transistor, and a low-speed, high-voltage NPN bipolar transistor on the same silicon substrate, the degree of freedom in designing an analog-digital mixed Bi-CMO8 integrated circuit can be increased. Moreover, as a P-type base diffusion layer of a low-speed, high-voltage NPN bipolar transistor,
By using the P-well of MO8FET, there is an effect that manufacturing can be performed at low cost without increasing the manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of a first embodiment of a semiconductor device of the present invention, FIG. 2 is a vertical cross-sectional view of a second embodiment, and FIG. 3 is a vertical cross-sectional view of a conventional bipolar transistor. 1.31...P-type silicon substrate, 2,32...
...N+buried layer, 3...P+buried layer, 4,
34...N-type epitaxial layer, 5...
・P well, 6...P+ diffusion layer, 7...
・Gate polysilicon, 8... Gate oxide film,
9...N+ diffusion layer, 10,14.38...
...P-type base diffusion layer, 11,35...Collector N+ layer, 12...Emitter polysilicon, 1
3.37...Emitter N+ layer, 33...
- P type separation layer, T1... Thickness % of N type epitaxial layer T2... Junction depth of P type base diffusion layer. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A semiconductor device characterized in that a P-channel field effect transistor, an N-channel field effect transistor, a high-speed low-voltage bipolar transistor, and a low-speed high-voltage bipolar transistor are formed on one semiconductor substrate.