JPS62294Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to a field discrimination circuit, and more particularly to a field discrimination circuit for a television receiver equipped with a countdown type vertical synchronization circuit. As a field discrimination means for extracting the VIR signal inserted only in odd-numbered fields, a logic circuit accurately detects the vertical synchronization pulse and starts from the last pulse of the equalization pulse after the vertical synchronization pulse.
A device that performs field discrimination by detecting whether or not a horizontal synchronizing signal is present during a period of less than 1H is known, for example, from Japanese Patent Publication No. 54-29224. However, such a device has a complicated circuit and is expensive. In view of such conventional examples, the present invention provides a low-cost and highly reliable field discrimination circuit particularly suitable for television receivers employing a countdown type vertical synchronization circuit. The details of the present invention will be explained below with reference to the drawings showing one embodiment. Horizontal synchronous circuit HS shown in Figure 1
consists of a variable oscillation circuit VCO that basically oscillates at a center frequency of 32fH (however, fH is the horizontal scanning frequency), a countdown circuit CD that steps down the output of the circuit by 32, and a phase comparator circuit that is equipped with a ceramic filter cf.
It consists of PD. The countdown circuit CD is composed of five cascade-connected T flip-flop circuits F1 to F5, and the VCO output of 32fH is connected to F1.
As a trigger input, the duty is applied to the Q output of F5.
50%, resulting in a horizontal sync pulse of frequency fH. The phase comparison circuit PD has a transistor Q25 which receives the output of the flip-flop circuit F5 and generates its inverted output Q, a transistor Q26 which generates its inverted output, and the collectors of both transistors Q25 and Q26, respectively, from the composite video signal. It is equipped with a circuit Q22 for applying the separated horizontal synchronizing signal with the same polarity, and both transistors Q2
An AND output (as a kind of error signal) of the collector outputs of the respective transistors Q25 and Q26 and the horizontal synchronization signal is generated at the collectors of transistors Q25 and Q26. The AND output generated at the collector of the transistor Q25 is applied to the charging control circuit CC, and the AND output generated at the collector of the transistor Q26 is applied as a control input to the discharge control circuit CD, which controls the amount of charge of the capacitor CO, that is, the terminal voltage. do. The terminal voltage of the capacitor CO controls the variable oscillation circuit VCO so that the frequency and phase of the output of the VCO match the horizontal synchronization signal of the input video signal. Note that the series connection of the switching transistor T197 and the resistor Rb, which is connected in parallel to the resistor Ra connected to the ground side of the capacitor CO, is provided for switching the control sensitivity, but this is not the main purpose of the present invention. I will not go into details as it is not related to this. In FIG. 1 and the following description, the transistor indicated by Q is an I ² L type transistor, and the transistor indicated by T is a normal bipolar transistor. The vertical synchronization circuit VS shown in FIG. 2 is composed of a down counter DV, a pull-in frequency (range) setting circuit TF, and a reset circuit RT. The down counter DV is composed of nine cascade-connected T-flip-flop circuits F6 to F14, and the horizontal synchronization circuit receives voltage through an inverter transistor Q106.
Using the HS output as a count input, the frequency is sequentially divided into 50% duty pulses. In this embodiment, the vertical oscillation frequency pull-in range is selected as follows.

[Table] At that time, the down counter corresponding to each frequency
The count number of DV is as follows. NTSC method Frequency (Hz) Number of counts 54.632 288 (=2 ⁸ + 2 ⁵ ) 57.846 272 (= 2 ⁸ + 2 ⁴ ) 61.461 256 (= 2 ⁸ ) 65.588 240 (= 2 ⁷ + 2 ⁸ + 2 ⁵ + 2 ⁴ ) 59.939 (center frequency )262.5 PAL method Frequency (Hz) Number of counts 44.389 352 (=2 ⁸ + 2 ⁶ + 2 ⁵ ) 48.828 320 (= 2 ⁸ + 2 ⁶ ) 51.398 304 (= 2 ⁸ + 2 ⁵ + 2 ⁴ ) 54.253 288 (= 2 ⁸ + 2 ⁵ ) 50.000 (center frequency) 312.5 The down counter DV is controlled by the pull-in frequency range (from 288 to 240 in the case of NTSC system during VTR playback) by the function of the pull-in frequency (range) setting circuit TF and reset circuit RT, which will be described later. range of counts,
In the case of PAL system, the count range is from 352 to 288] [When receiving broadcasting, in the case of NTSC system, the count range is from 272 to 288]
Count range of 256, 320 for PAL method
If a vertical sync signal exists within the count range of 304 to 304, it will be reset in synchronization with that vertical sync signal;
During playback and during broadcast reception, up to the count number corresponding to the minimum pull-in frequency set according to each broadcasting system of NTSC and PAL, that is,

When the count reaches each count number in [Table], it is automatically reset and starts counting again from 0. Next, the pull-in frequency (range) setting circuit TF will be explained. The relationship between the Q output of each flip-flop circuit constituting the down counter DV and each pull-in frequency (corresponding count number) is as follows.

【table】

[Table] The above-mentioned pull-in frequency (range) setting circuit TF extracts a count number corresponding to the upper limit frequency of the above-mentioned pull-in frequency using a decoder, which will be exemplified later, sets the R-S flip-flop circuit FS1 with the output, The set output of the circuit and the output of the transistor Q64 whose base input is either the input vertical synchronizing signal or the output of a decoder for lower limit frequency detection, which will be exemplified later.
A circuit configuration is adopted in which an AND output is taken and the output is applied as a D input to a D flip-flop circuit F15 constituting the reset circuit RT. Next, the configuration of the decoder for each pull-in frequency setting is
This will be explained using the NTSC system as an example. Decoder DVL for the lower limit pull-in frequency of 54.632Hz (count number 288 = 2 ⁸ + 2 ⁵ ) during VTR playback This decoder DVL consists of a transistor Q101 whose base input is the output of the flip-flop circuit F11, and transistors connected sequentially to this transistor in cascade. Q102, Q10
3, a transistor Q105 whose base input is the Q output of the flip-flop circuit F14, and a transistor Q58 which inputs the AND output of the collector outputs of the transistors Q103 and Q105. The transistor Q58 is Q
In conjunction with 59, it also works as an NTSC-PAL reception mode switch. The figure indicates operation in NTSC reception mode, and indicates operation in PAL reception mode. (The same applies hereafter) Decoder DBL for the lower limit pull-in frequency of 57.846 Hz (number of counters 272 = 2 ⁶ + 2 ⁴ ) during broadcast reception. This decoder DBL is a transistor Q97 whose base input is the output of the flip-flop circuit F10.
and a transistor Q108 whose base input is the Q output of the flip-flop circuit F14, and a transistor Q109 connected in cascade to the transistor.
and the collector output of the transistor Q97.
Transistor 6 with AND output as base input
It consists of 1. The transistor Q61 and Q62 work together as an NTSC-PAL image reception mode changeover switch. Decoder DBU for the upper limit pull-in frequency of 61.461Hz (count number 256 = ²⁸ ) during broadcast reception This decoder DBU consists of transistor Q1 that inverts the output of flip-flop circuit F14.
05 and a transistor Q72 whose base input is the output. The transistor Q7
2 also functions as an NTSC-PAL reception mode switch in conjunction with Q71, and its output
-S Set flip-flop FS1. Decoder DVU for the upper limit pull-in frequency of 65.558 Hz (count number 240 = 2 ⁷ + ^{2 6} + ^{2 5} + 2 ⁴ ) during VTR playback This decoder DVU consists of a transistor Q97 whose base input is the output of the flip-flop circuit F10, and the collector output of this transistor. and flip-flop circuits F11, F12, F
It is composed of a transistor Q68 whose base input is the AND output of each of the 13 Q outputs. The transistor Q68 also functions as an NTSC-PAL image reception changeover switch, and its output sets the R-S flip-flop circuit FS1. Since the process is basically the same for the PAL system, we will omit the explanation. The reset circuit RT is connected to the output of the R-S flip-flop circuit FS1 (transistor Q
66 collector output) and transistor Q64
collector output or transistor Q61
(When receiving NTSC broadcasts) or Q58 (NTSC
The AND output of each collector output (during VTR playback) is used as the D input, and the T flip-flop circuit F1 constitutes the down counter of the horizontal synchronization circuit HS.
~D- with the Q output of F4 among F5 as the C input
It consists of a flip-flop circuit F15, an AND connection circuit A that ANDs the Q output of this circuit and the output of the flip-flop circuit F4, and cascaded transistors Q107 and Q165. Circuit F6-F1
Reset 4. The transistor T165
The reset output generated at the output is applied to a vertical drive circuit (not shown) as a vertical synchronization signal via a buffer or an inverter transistor, as required. Next, AFC circuit, burst gate creation circuit,
The details of the masking pulse generation circuit MP for deleting or masking the composite synchronization signal input from the DC reproduction pulse generation circuit, synchronization detection circuit, etc. during the vertical synchronization signal section including the preceding and succeeding equalization pulse sections will be explained. This masking pulse generation circuit MP is R-S
Flip-flop circuit FS2, set pulse decoder DSN, DSP and reset decoder DR
It consists of The R-S flip-flop circuit FS2 is composed of a pair of transistors Q53 and Q54 and a cross connection, and is set by the collector output of transistor Q57 in the NTSC image reception mode, and by the collector output of the transistor Q56 in the PAL image reception mode. and is reset by the collector output of transistor Q55 in any image reception mode. The masking pulse Pm is taken out from the collectors of the transistors Q54 and Q53, the former of which is connected to the switching transistor T170.
(Fig. 1) to ground the horizontal synchronizing signal output terminal of the horizontal synchronizing separation circuit HS, and the latter is connected to the horizontal synchronizing circuit HS in the burst gate pulse generation circuit BP (Fig. 1) connected to the horizontal synchronizing circuit HS. It is applied to the base of transistor Q3 to cut off said transistor Q3 during the masking pulse application period. The setting decoder DSN of the R-S flip-flop circuit FS2 in the NTSC reception mode includes a pair of cascade-connected transistors Q108 and Q10 that derive the Q output of the flip-flop circuit F14.
9, transistor Q9 that derives the output of F8
4, Q95, and cascade-connected transistors Q92 for taking out the Q outputs of F7, and a transistor Q84 that is turned on by a vertical blanking pulse in order to turn off the setting transistor Q57 in the vertical retrace section. With such a configuration, the setting transistor Q57 is
(Refer to time chart Figure 3) Each flip-flop circuit, Q output ○yo of F14 is H (high level),
The Q output of F8 is maintained at L (low level), the Q output of F7 is maintained at H, and the collector output of transistor Q84 becomes high at the timing of H, and the above R-S Flip-flop circuit FS
Set 2. Similarly, in the PAL reception mode, the set pulse decoder DSP is a flip-flop circuit Q10 that derives the Q output of the flip-flop circuit F14.
8, Q109, Q83, Q82, transistor Q which inverts the output of F11 and supplies it as Q output
101, Q102 and Q103, Q83, Q8
2. Transistors Q94, Q95, Q96 which invert and derive the output of F8 and supply it as a Q output, Q89, Q79 which derives the Q output of F6, and the transistor Q84 are connected in combination. In the PAL reception mode, the Q output of each flip-flop circuit F14 maintains H, the Q output of F11 maintains H, the Q output of F8 maintains H, and the Q output of F6 maintains H with respect to the base of the setting transistor Q56. and transistor Q8
When the collector of No. 4 is H, an H pulse is supplied to turn on Q56 and set the R-S flip-flop circuit FS2. Next, details of the reset pulse decoder DR will be explained. The reset pulse decoder DR includes a transistor Q94 that inverts the output of the flip-flop circuit F8, transistors Q89 and Q79 that derives the Q output of F6, and transistors Q84 and Q.
48 and both flip-flop circuits F8
And F6 is F8's Q output ○ is high, F6's Q output ○ is high, and transistor Q84's collector output ○ is high.
That is, in the interval where the vertical blanking pulse does not exist, the collector of Q48 is set to H, that is, the R-S flip-flop circuit FS3 (transistors Q44, Q4) is set by the reset pulse of the down counter DV and reset by the 22nd line selector pulse (described later).
The reset transistor Q55 is turned on at each timing when the collector output of the transistor Q48, which is controlled on/off by the output of the
Reset the S flip-flop circuit FS2. The reset pulse decoder DR is NTSC,
Can be used for both PAL reception modes. Using the masking pulse Pm that covers most of the equalization pulse and vertical synchronization signal sections at such timing, the input signal of the AFC circuit and the output signal of the burst gate pulse generation circuit BP are masked, etc. Deleting the signal in the vertical synchronization signal section including the sync pulse section will cause image curvature at the start of vertical scanning, uneven brightness near the vertical synchronization signal section, that is, above the screen, deterioration of the S/N ratio of the color reproduction system, and horizontal synchronization detection. All causes of image deterioration such as a decrease in circuit sensitivity can be improved. Next, the configuration of the line selector decoder will be explained. Line selector decoder 16L, 279 for extracting NTSC system (Japan) character multiplex signal
L, 20L, 283L and this decoder are used for the 16th and 20th fields of the first field where the character multiplex signal exists.
This is for extracting select pulses for extracting the 279th and 283rd lines of the 2nd and 2nd fields. The Q and output of each flip-flop circuit F6 to F10 of the down counter DV in the 16th and 279th lines are as follows.

[Table] Considering this condition, decoders 16L and 279L
The transistors Q89, F7 take out the inverted output of the Q output of the flip-flop circuit F8, F9, which derives the Q output.
The 16th or 279th line selector pulse is extracted as the AND of the collector outputs of the transistors Q88, Q89, and Q91. Similarly, each flip-flop circuit F6 of the down counter DV in the 20th and 283rd lines
~The Q and output of F10 are respectively

[Table] Considering that, the 20th and 283rd line selection decoders 20L and 283L
is composed of transistors Q85 and Q86 that take out the Q output of flip-flop circuit F10, and a transistor Q89 that inverts and takes out the Q output of F6, and selects the 20th and 283rd lines. The pulse is extracted as the AND of the collector outputs of transistors Q86 and Q89. Next, the line selector decoder D19 for forming the VIR extraction pulse in the NTSC (USA) system, that is, the 19th line selector pulse, will be described. Each flip-flop circuit F6 of the down counter DV in the 19th line
It is clear that the Q and output states of F10 to F10 are as follows.

[Table] Taking into consideration the state of the flip-flop circuit, the decoder D19 is connected to the transistor Q8 which derives the Q output of the flip-flop circuits F8 and F9.
It is constructed as shown in the figure with a transistor Q90 that takes out the inverted pulse of the output of F7, Q88, and F6, and a transistor Q91, Q92 that takes out the Q output of F7.
It can be formed as an AND pulse of the collector outputs of Q90 and Q92. The decoder 19L also serves as a decoder for extracting the 282nd line in the second field. Depending on the purpose of each receiver, the down counter DV can also be used for other lines [for example, the decoder 21L that forms the 21st pulse of the first field for extracting the NTSC (US) character multiplex signal]. It would be easy to construct a logic circuit from the charts of F6 to F10 of the flip-flop circuits F6 to F14 constituting the flip-flop circuits and take out the AND output. For example, the NTSC (USA) character multiplex signal is currently inserted only in the 21st field of the first field. In the 21st line and the 284th line, each Q and output of each flip-flop circuit F6 to F10 are as follows:

[Table] becomes. Therefore, in order to obtain a selector pulse that extracts only the 21st line, a logic circuit that extracts the pulse when the states of the flip-flop circuits F6 to F10 are satisfied is realized, and
Distinguish between odd and even (first and second fields), and calculate the logical product of the first field's discrimination pulse and the sampling pulse to identify the selector pulse for extracting only the 21st line. It is necessary to adopt a configuration that allows for extraction. Below, we will explain the details of the 21st and 284th line selector decoders, then explain the odd-even field discrimination circuit FD, and then explain the AND connection that discriminates and extracts only the 21st line selector pulse. explain. The 21st and 284th line selector decoders 21L and 284L are composed of cascaded flip-flop circuits Q85 and Q86 that extract the Q output of the flip-flop circuit F10, and a transistor Q90 that inverts and derives the output of the flip-flop circuit F6. The transistors Q86 and Q connected in common
The line selector pulse is output to the collector 90 as an AND output. The field discrimination circuit FD basically consists of a transistor Q that is turned off by vertical synchronization signal input.
The flip-flop circuit F4 receives the AND H output of the collector output of Q64 and the collector output of Q66 of the R-S flip-flop circuit FS1, and constitutes the down counter of the horizontal synchronous circuit HS in FIG.
(frequency 2fH, where fH is a pulse with a horizontal frequency and a duty of 50%) is inverted by Q40 and inputted as a clock pulse. 50% pulse) and outputs it to its collector, and the Q terminal of the D flip-flop circuit F15 and the transistor Q.
It consists of 106 AND connections, and its output is R
-S Set flip-flop circuit FS4. The R-S flip-flop circuit FS4 is composed of transistors Q50 and Q52, and the transistor Q52 turns on the field discrimination output.
Set the collector output of transistor Q4.
The line selector pulse for extracting the 22nd line generated at the collector of No. 6 is used as the reset input, and the field discrimination pulse in section H that rises with the set pulse and falls with the reset pulse is applied to the transistor Q49.
In addition to the collector of , through transistor Q78,
Of the 21st and 284th sampling line selector pulses generated at the collector of transistor Q49, only the former is applied to the base of output transistor T155. Here, the reset pulse and field discrimination pulse forming operations will be explained with reference to FIG. Now, as mentioned above, the vertical synchronizing signal Vsynch as shown in FIG. 4A is applied to the D input terminal D of the D flip-flop circuit F15, and the 2fH pulse as shown in FIG. 4B is applied to the clock input terminal C. As shown in the figure, when the clock pulse is inverted from H to L, the previous D input is output to the Q output terminal of the D flip-flop circuit, so in this case, a pulse that rises at time ta shown in the figure is obtained. .
Here, the Q of this D flip-flop circuit F15 is
The reason for this is that the output does not become a signal whose high level H continues for the period of the vertical synchronization signal Vsynch after the above-mentioned time ta, but becomes a pulse with a pulse width T1 (=1/2fH) as shown in Fig. 4C. This will be discussed later. The output pulse of the D flip-flop circuit F15 is led to the collector of the transistor Q41 (point A), and the output of the flip-flop circuit F4 appears at the point A from the collector of the transistor Q10 in FIG. 1 via Q40 and Q41 in FIG. By performing a logical AND operation with 2 and 2, a reset pulse Reset as shown in FIG. 4E is obtained. and,
This reset pulse H is applied via transistors Q107 and T165 to the reset terminals of each of the T flip-flop circuits F6 to F14 constituting the down counter DV, and each flip-flop circuit is reset at the timing of the rise of the reset pulse. In this way, each flip-flop circuit F
6 to F14 are reset and when the Q output of F14 becomes L, transistor Q108 is turned off and the Q output becomes L.
110 is turned on, and therefore the collector of transistor Q64, which is connected to the collector of Q110 and to which the vertical synchronizing signal is applied to the base, becomes low.
become. Thereby, the D flip-flop circuit F15 connected to the collector of this Q64
Since the input becomes L, the Q output of this F15 is 2fH
becomes L at the next falling edge of the pulse tb, that is, at the time tb,
The result will be as shown in Fig. 4 (c) mentioned above. Here, the Q output of the D flip-flop F15 is compared with the pulse having a horizontal frequency fH and a pulse width of 1/2 fH, which is shown in FIGS. As you can see, in the odd field, the above F
The Q output of F5 has the same polarity as the Q output of F15, but in an even field, the Q output of F5 has the opposite polarity. Therefore, by calculating the AND between the respective outputs of the flip-flop circuits F15 and F5, the field discrimination output pulse PF can be easily obtained. In the above embodiment, the flip-flop circuit F
Q output of F15 and Q of flip-flop circuit F5
The outputs H and H are logically ANDed, but instead of the former Q output C, the above-mentioned reset pulse is used.
You may also use Reset, in which case the above F
This is further advantageous for phase fluctuations of 15, etc. According to the field discrimination circuit of the present invention, in television receivers and the like equipped with countdown type horizontal and vertical synchronization circuits, a constant pulse width horizontal pulse synchronized with a horizontal synchronization signal can be easily extracted from the horizontal synchronization circuit. By simply adding a circuit that performs the logical product of the frequency pulse signal and the pulse signal for resetting the frequency dividing circuit in the vertical synchronization circuit for each field, it is possible to achieve stability and reliability against temperature drift, etc. There is an advantage that a high field discrimination operation can be realized at low cost.

[Brief explanation of the drawing]

The drawings are all related to the present invention; FIG. 1 is a circuit diagram showing a horizontal synchronization circuit which is the premise of the field discrimination circuit of the present invention, FIG. 2 is a circuit diagram showing a vertical synchronization circuit equipped with a field discrimination circuit, and FIG. The figure is an operation waveform diagram, and FIG. 4 is an operation explanatory diagram. HS...Horizontal synchronous circuit, VS...Vertical synchronous circuit,
RT...Reset circuit, DV...Down counter,
FD...Field discrimination circuit.

Claims (1)

[Scope of utility model registration request] A horizontal synchronization circuit that creates a horizontal frequency pulse signal by dividing the output of an oscillation circuit that is controlled to be synchronized with a horizontal synchronization signal and oscillates at a frequency sufficiently higher than the horizontal frequency, and a horizontal synchronization circuit that creates a horizontal frequency pulse signal. a vertical synchronization circuit that generates a vertical frequency pulse signal by synchronizing the frequency with a vertical synchronization signal;
A circuit for creating a pulse signal taken out from the vertical synchronization circuit and used to reset the frequency dividing circuit in the vertical synchronization circuit for each field; and a circuit for performing logical product of a pulse signal of horizontal frequency with a pulse signal of a horizontal frequency having the same or wider pulse width, and the field discriminating circuit is configured to perform a logical product of an odd number field and an even field based on the logical product output.