JPS62293759A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize large scale integration and improved performance of a semiconductor device by a method wherein polycrystalline Si which fills trenches formed in an Si substrate is used as storage capacitor electrodes and SOI-Si layers which are formed with apertures on the substrate surrounded by the capacitor electrodes as seeds are recrystallized to form switching transistors. CONSTITUTION:Trenches which are formed in an Si substrate 1 composed of a P<+>type Si substrate 1A and a P-type Si epitaxial layer are filled with polycrystalline Si 3 with insulating films 2 and 4 there between. SOI (Silicon on Insulator) recrystallized Si layers 5 are formed with the parts 1B of the Si substrate 1 as seeds and the SOI-Si layers 5B directly above the parts 1B are empolyed as channel regions of switching transistors Moreover, a part of one of N<+>type regions 5A of the source and drain of the switching transistor and a part of a storage capacitor electrode 3 are in direct contact with each other and the other N<+>type region of the source or drain is made to be common with the source or drain of one of the adjoining switching transistors to form a bit line 7. With this constitution, a DRAM or the like with high integrity and high performance can be obtained.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a semiconductor device, and particularly to a dynamic random semiconductor device formed from a memory cell consisting of a MOS (metal oxide semiconductor) transistor and a MOS capacitor. This relates to access memory (DRAM).

Conventional technology MO3 type DRAM is currently being actively researched and developed in various places as an ultra-highly integrated device. Improvements have been made to circuit technology, process technology, etc. for higher integration, and the structure of memory cells has also been improved to accommodate higher integration. (H. Sunami IDM Technical Digest (H.

Sunami IEDM, Teah, Dig, )pp
, 694-s97, 19ss) In particular, very recently,
In addition to improving the conventional two-dimensional structure, 5OI (
There are also examples in which high integration is achieved by incorporating a 5ilicon on in5ulator) structure in some parts. That is,
As shown in FIG. 3, a polycrystalline Si electrode 3 and an n''-3i layer 1B are embedded in a groove formed in a Si substrate 1 consisting of a p''-Si layer 1A and an n''-3i layer 1B. forms a storage capacitor, and the switching transistor 5O
Attempts have been made to achieve high integration by forming the ISi layers sA and sB.

Problems to be Solved by the Invention However, since the channel region 5B of the switching transistor formed in SOI is formed by lateral epitaxy using the opening of the substrate Si 1 as a seed, there are still problems with crystallinity, etc. Yes, there is a problem of deterioration of electrical characteristics. Further, it is necessary to further improve the structure of the storage capacitor formed in the groove in order to achieve high integration.

The present invention attempts to solve the above problems by improving the structure of the storage capacitor and the structure of the SOI switching transistor.

Means for Solving the Problems In the present invention, in order to solve these problems, a polycrystalline Si electrode buried in a groove formed in a Si substrate is used as a storage capacitor electrode for the Si substrate, and this storage capacitor A switching transistor is formed by recrystallizing a 5OISi layer using an opening on a Si substrate surrounded by electrodes as a seed.

Function: According to the structure of the present invention, high integration is achieved by using embedded polycrystalline Si as the electrode of the storage capacitor, and the channel part of the switching transistor is formed using single crystal silicon in order to be formed in the SOI recrystallized layer directly above the seed part. S
It is a high-quality crystal comparable to that of T-type crystals, and since the source and drain of the switching transistor are completely separated from each other in the form of SOI, stray capacitance can be extremely small, resulting in high performance characteristics. Furthermore, since the bit lines of adjacent switching transistors are directly coupled through their sources or drains, higher integration can be achieved. Adjacent cells can be completely separated by an insulator, resulting in a structure in which mutual interference between cells can be suppressed.

Embodiment An embodiment of a semiconductor device according to the present invention will be described with reference to FIG. FIG. 1 is a sectional view explaining the concept of one embodiment.

n+ in a groove of a desired depth formed in a Si substrate consisting of a p''-3t substrate 1A and a p-3t epitaxial layer.
Polycrystalline Si 3 is embedded with insulating films 2 and 4 interposed therebetween. The trench is made of Si so that it becomes a memory cell of the desired size.
When viewed from the top surface of the substrate 1, it is formed, for example, in a rectangular shape so as to surround the Si substrate. Therefore, in FIG. 1, L is the width of one cell. A 5oISi layer 5 insulated with an insulator 4 is formed except for a portion 1B of the Si substrate of one cell.

An example of a method for forming this 5OISi layer will be briefly explained with reference to FIG. As shown in FIG. 2a, a part of the opening is formed on the Si substrate 1 to form 5lo24 to form, for example, polycrystalline Sis', and then an energy beam 7 such as a laser beam or an electron beam is applied under appropriate conditions. By scanning in the X direction, crystal growth proceeds in the Y direction using the opening in the Si substrate as a seed, forming an SOI recrystallized Si layer. Further, as shown in FIG. 2b, an amorphous St layer is formed as a 5OISi layer, and by performing appropriate heat treatment, solid phase epitaxial growth occurs by seeding the opening of the Si substrate and an SOI crystal layer is obtained. In either of the above two examples, the recrystallized layer especially near the seed portion has crystallinity almost equivalent to that of the Si single crystal substrate.

Now, returning to Figure 1 again, using the method shown in the example in Figure 2, SOI is performed using part 1B of the Si substrate as a seed.
A recrystallized St layer 5 is formed, and the 5OIS directly above this sheet portion is
This structure is such that the i-layer 5B serves as a channel region of a switching transistor. Further, a portion of the n+ region 5A of one of the source and drain of the switching transistor and a portion of the storage capacitor electrode 3 are directly coupled. Further, the other source or drain region of the switching transistor is shared with the source or drain of one adjacent switching transistor to form a pit line.

Effects of the Invention As described above, according to the present invention, it is possible to provide a semiconductor device such as a highly integrated and high-performance dynamic random access memory.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment C of the present invention, FIG. 2 is a sectional view illustrating an SOI forming method of the same device, and FIG. 3 is a sectional view of a conventional example. 1...St substrate, 2, 4...S 10
2.3,6...polycrystalline Si, 5...S
OI recrystallized Si. Name of agent: Patent attorney Toshio Nakao and 1 other person/
−5, Substrate/A −P+−3= β −P−−5ε ”−−5iOz J,6− Akira Tase 5ε 5=501Re Mt kS Otsu5A −ri no n”4f3 or G4 cutting′transistor Sources are drain)

Claims (2)

[Claims] (1) A unit cell of a memory element consisting of a region surrounded by a groove dug at a desired position on one principal surface of a semiconductor substrate, a storage capacitor consisting of an electrode insulated and buried in the groove and the semiconductor substrate. , a switching transistor formed at a desired position in the cell region on a semiconductor substrate with source and drain regions insulated and separated; a source of one switching transistor with one electrode of the source or drain of the switching transistor adjacent to the other; Alternatively, a semiconductor device comprising a bit line formed in common with a drain, and the other source or drain electrode of the switching transistor is connected to the electrode of the storage capacitor. (2) The semiconductor device according to claim 1, which is a switching transistor formed in a semiconductor layer formed by melting and recrystallizing a non-single crystal semiconductor by energy beam irradiation or a semiconductor layer formed by solid phase epitaxial growth.