JPS62293667A - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPS62293667A JPS62293667A JP61136558A JP13655886A JPS62293667A JP S62293667 A JPS62293667 A JP S62293667A JP 61136558 A JP61136558 A JP 61136558A JP 13655886 A JP13655886 A JP 13655886A JP S62293667 A JPS62293667 A JP S62293667A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- low resistance
- polysilicon
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 238000003860 storage Methods 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 11
- 238000011109 contamination Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 41
- 238000009792 diffusion process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- -1 is formed thereon Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
産業上の利用分野
本発明は半導体記憶装置に関し、特にダイナミックラン
ダムアクセスメモリ（ＤＲＡＭ）の埋め込み型容量電極
に関するものである。DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a semiconductor memory device, and more particularly to an embedded capacitor electrode of a dynamic random access memory (DRAM).
従来の技術
第３図に従来のＤＲＡＭの構造を示す。第３図に基づき
従来例について説明する。Prior Art FIG. 3 shows the structure of a conventional DRAM. A conventional example will be explained based on FIG.
半導体基板１上に形成された分離域１１に囲まれた部分
の溝部２ｏの側面Ｋ、蓄積容量の一方の電極となる拡散
層が形成され、この層１２上に蓄積容量の誘電体層１７
さらＫその上に蓄積容量の他方の固定電位に接続された
プレート電極１４が形成されている。拡散層１２に蓄え
られた信号電荷は読み出しゲート１３を有するＭΦｓト
ランジスタ部１８を介して、コンタクト形成部１６を通
じて、ビット線１０に読み出される。１５はポリシリコ
ンよりなるプレート電極１４の表面に形成された高濃度
不純物層であシ、２は絶縁膜である。A diffusion layer serving as one electrode of the storage capacitor is formed on the side surface K of the groove portion 2o in a portion surrounded by the isolation region 11 formed on the semiconductor substrate 1, and a dielectric layer 17 of the storage capacitor is formed on this layer 12.
Furthermore, a plate electrode 14 connected to the other fixed potential of the storage capacitor is formed thereon. The signal charge stored in the diffusion layer 12 is read out to the bit line 10 through the MΦs transistor section 18 having the read gate 13 and the contact formation section 16 . 15 is a high concentration impurity layer formed on the surface of the plate electrode 14 made of polysilicon, and 2 is an insulating film.
この構造において、拡散層１２とプレート電極１４間の
結合容量によ見プレート電極１４の電位も変動すること
になる。プレート電極１４は隣接するメモリセルにも接
続されており、このプレート電極１４の電位が変動すれ
ば、隣接するメモリセルの蓄積電荷量にも影響を与える
という、プレート電極を介したセル間干渉の問題が発生
する。In this structure, the potential of the plate electrode 14 also varies depending on the coupling capacitance between the diffusion layer 12 and the plate electrode 14. The plate electrode 14 is also connected to an adjacent memory cell, and if the potential of the plate electrode 14 fluctuates, it will also affect the amount of accumulated charge in the adjacent memory cell. A problem occurs.
まだ、信号電荷の読み出しの際、プレート電極１４の電
位が一定値に落ちつくまでは、ビット線１０の電位は確
定せず、その結果ＤＲＡＭ全体のアクセス時間の低下を
招くことになる。以上の欠点を除くために従来は、プレ
ート電極１４の上部に、イオン注入等により高濃度の不
純物層１５を形成したりプレート電極１４全体を高濃度
の不純物を含む層で形成することによりプレート電極１
４の抵抗を下げこれにより、電位変動を少くするという
ことが行なわれている。However, when reading signal charges, the potential of the bit line 10 is not determined until the potential of the plate electrode 14 settles to a constant value, resulting in a reduction in the access time of the entire DRAM. In order to eliminate the above drawbacks, conventionally, a highly concentrated impurity layer 15 is formed on the top of the plate electrode 14 by ion implantation or the like, or the entire plate electrode 14 is formed with a layer containing a highly concentrated impurity. 1
4 is being lowered to reduce potential fluctuations.
プレート電極１４全体を高濃度の不純物を含む層で形成
しようとする場合、誘電体層１４への不純物の汚染が問
題である。他方、プレート電極１４の表面層にのみ不純
物層を形成する場合、溝２０の深さが深くなるにつれ、
プレート電極１４の低抵抗化の効果が薄れるという問題
点がある。When the entire plate electrode 14 is formed of a layer containing highly concentrated impurities, contamination of the dielectric layer 14 with impurities is a problem. On the other hand, when forming an impurity layer only on the surface layer of the plate electrode 14, as the depth of the groove 20 becomes deeper,
There is a problem that the effect of lowering the resistance of the plate electrode 14 is weakened.
発明が解決しようとする問題点
上に示したように、従来の方法では、容量部の溝深さが
深くなった場合、誘電体層１７を不純物に汚染されない
ようにして、プレート電極１４の低抵抗化を計ることが
できないという問題点がある。Problems to be Solved by the Invention As shown above, in the conventional method, when the groove depth of the capacitor section becomes deep, the dielectric layer 17 is prevented from being contaminated with impurities, and the plate electrode 14 is lowered. The problem is that it is not possible to measure resistance.
問題点を解決するだめの手段
本発明は、上記問題点を解決するために、蓄積容量の固
定電極がポリシリコン、低抵抗層、ポリシリコンからな
る３層構造をとるものである。Means for Solving the Problems In the present invention, in order to solve the above problems, the fixed electrode of the storage capacitor has a three-layer structure consisting of polysilicon, a low resistance layer, and polysilicon.
作 用
本発明は、蓄積容量の固定電極を３層構造とすることに
より、電極の低抵抗化を実現し同時に、不純物汚染を起
させないものである。Function The present invention realizes low resistance of the electrode by forming the fixed electrode of the storage capacitor into a three-layer structure, and at the same time prevents impurity contamination.
実施例
本発明の一実施例装置の断面図を第１図に示し第３図と
同一のものには同一番号を付している。Embodiment A sectional view of a device according to an embodiment of the present invention is shown in FIG. 1, and the same parts as in FIG. 3 are given the same numbers.
この場合の製造方法について説明する。シリコン基板１
に掘られた溝部２０の側面に、蓄積容量の一方の電極と
なる拡散層１２を形成しさらにその上にＳｉＯ３等の誘
電体層１７を形成した上に、他方の電極となるポリシリ
コン層３０を溝部２０に埋めこみ完全に溝部が埋ってし
まう前に、ポリシリコン層に高濃度のイオン注入を行い
低抵抗層３１を形成する。このようにして、埋め込みポ
リシリコン電極となる層３０中に、深さ方向に沿って、
低抵抗層、ｉｌを形成したあと再びポリシリコン層３２
の埋め込み形式を行って蓄積容量の固定電極を形成する
。次に読み出しＭＯＳ）ランジスタ部１８及コンタクト
部１６．ビット線１０を形成する。The manufacturing method in this case will be explained. Silicon substrate 1
A diffusion layer 12, which will become one electrode of the storage capacitor, is formed on the side surface of the trench 20, and a dielectric layer 17, such as SiO3, is formed thereon, and a polysilicon layer 30, which will become the other electrode, is formed on the side surface of the trench 20. is buried in the trench 20, and before the trench is completely filled, high concentration ions are implanted into the polysilicon layer to form a low resistance layer 31. In this way, along the depth direction in the layer 30 that will become the buried polysilicon electrode,
After forming the low resistance layer, il, the polysilicon layer 32 is formed again.
A fixed electrode of the storage capacitor is formed by embedding the electrode. Next, the readout MOS) transistor section 18 and contact section 16. A bit line 10 is formed.
本実施例は上記の方法により固定電極をポリシリコン層
３０．低抵抗層３１．ポリシリコン層３２の３層構造を
実現したものである。第２図はこの途中の様子を示すも
ので、溝部２０の誘電体層１７上にポリシリコン層３０
を埋込み形成し、層３０が溝部２０を埋める前に層３０
の表面に低抵抗層３１を形成する。したがって、層３１
は誘電体層１７に達することなく容易に形成可能となり
、かつ固定電極としては低抵抗化が可能となる。In this embodiment, the fixed electrode is formed using the polysilicon layer 30. Low resistance layer 31. A three-layer structure of polysilicon layer 32 is realized. FIG. 2 shows a state in the middle of this process, in which a polysilicon layer 30 is formed on the dielectric layer 17 in the groove 20.
The layer 30 is buried before the layer 30 fills the trench 20.
A low resistance layer 31 is formed on the surface. Therefore, layer 31
can be easily formed without reaching the dielectric layer 17, and the resistance can be lowered as a fixed electrode.
発明の効果
以上のように、本発明によれば容量電極をポリシリコン
、低抵抗層、ポリシリコンという３層構造にすることよ
り、容量電極全体としての低抵抗化を誘電体層への不純
物汚染をおこさせることなく可能とすることができる。Effects of the Invention As described above, according to the present invention, by forming the capacitor electrode into a three-layer structure consisting of polysilicon, a low resistance layer, and polysilicon, the resistance of the capacitor electrode as a whole can be lowered without impurity contamination in the dielectric layer. This can be done without causing any problems.
第１図は本発明の一実施例におけるＤＲＡＭの要部断面
図、゛第２図は同ＤＲＡＭの製造方法を説明する断面図
、第３図は従来のＤＲＡＭの断面図である。
１・・・・・・シリコン基板、１１・・・・・・分離部
、１２・・・・・・拡散層、１７・・・・・・誘電体層
、２ｏ・・・・・・溝部、３０゜３２・・・・・・ポリ
シリコン層、３１・・・・・・低抵抗層。FIG. 1 is a sectional view of essential parts of a DRAM according to an embodiment of the present invention, FIG. 2 is a sectional view illustrating a method of manufacturing the same DRAM, and FIG. 3 is a sectional view of a conventional DRAM. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 11... Separation part, 12... Diffusion layer, 17... Dielectric layer, 2o... Groove part, 30°32...Polysilicon layer, 31...Low resistance layer.
Claims (1)
リシリコン層の３層構造をとる半導体記憶装置。A semiconductor memory device in which a storage capacitor fixed electrode has a three-layer structure: a polysilicon layer, a low resistance layer, and a polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61136558A JP2702702B2 (en) | 1986-06-12 | 1986-06-12 | Semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61136558A JP2702702B2 (en) | 1986-06-12 | 1986-06-12 | Semiconductor storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62293667A true JPS62293667A (en) | 1987-12-21 |
| JP2702702B2 JP2702702B2 (en) | 1998-01-26 |
Family
ID=15178037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61136558A Expired - Lifetime JP2702702B2 (en) | 1986-06-12 | 1986-06-12 | Semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2702702B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4954927A (en) * | 1988-09-16 | 1990-09-04 | Samsung Electronics Co., Ltd. | Double capacitor and manufacturing method thereof |
| US5077232A (en) * | 1989-11-20 | 1991-12-31 | Samsung Electronics Co., Ltd. | Method of making stacked capacitor DRAM cells |
| WO2007069292A1 (en) * | 2005-12-12 | 2007-06-21 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263265A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS62266865A (en) * | 1986-05-15 | 1987-11-19 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-06-12 JP JP61136558A patent/JP2702702B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263265A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS62266865A (en) * | 1986-05-15 | 1987-11-19 | Hitachi Ltd | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4954927A (en) * | 1988-09-16 | 1990-09-04 | Samsung Electronics Co., Ltd. | Double capacitor and manufacturing method thereof |
| US5077232A (en) * | 1989-11-20 | 1991-12-31 | Samsung Electronics Co., Ltd. | Method of making stacked capacitor DRAM cells |
| WO2007069292A1 (en) * | 2005-12-12 | 2007-06-21 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| US7928515B2 (en) * | 2005-12-12 | 2011-04-19 | Fujitsu Semiconductor Limited | Semiconductor device and manufacturing method of the semiconductor device |
| JP4946870B2 (en) * | 2005-12-12 | 2012-06-06 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2702702B2 (en) | 1998-01-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |