JPS62293650A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62293650A
JPS62293650A JP61136972A JP13697286A JPS62293650A JP S62293650 A JPS62293650 A JP S62293650A JP 61136972 A JP61136972 A JP 61136972A JP 13697286 A JP13697286 A JP 13697286A JP S62293650 A JPS62293650 A JP S62293650A
Authority
JP
Japan
Prior art keywords
layer
bump electrode
tin
plating layer
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61136972A
Other languages
Japanese (ja)
Inventor
Yutaka Okuaki
奥秋 裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP61136972A priority Critical patent/JPS62293650A/en
Publication of JPS62293650A publication Critical patent/JPS62293650A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PURPOSE:To implement improvement in manufacturing efficiency and reliability and a low cost, by forming a lead plated layer on the side of a conductor member, which is connected for a bump electrode that is formed with a single composition of tin. CONSTITUTION:An oxide film 12 is formed on a semiconductor element 11. An electrode pad 13 is formed at a place where a bump electrode is to be formed, on the film 12. After a passivation film 14 is grown, a bump forming area is formed as a hole. A current conducting layer 15 is formed on the entire surface of the element 11. On the layer 15, a tightly contacted metal layer 16 and a diffused barrier plated layer 17 are formed. Thereafter, a part other than the bump electrode forming place is removed. A current is conducted to the layer 15, and a diffused barrier plated layer 19 is formed on the layer 17. Then, a tin plated layer 20 is formed on the layer 19. When the layer 20 is heated, a semispherical body is formed. Thus, a tin bump electrode 21 is obtained. The electrode 21 is thermally fused and fixed to a lead plated layer 33.

Description

【発明の詳細な説明】 3、発明の詳細な説明 (産業上の利用分野) 本発明は、バンプ電極を有する半導体素子を該バンプ電
極を介して導電部材に接続する半導体装置の製造方法に
関するものである。
Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element having a bump electrode is connected to a conductive member via the bump electrode. It is.

(従来の技術) 従来、このような分野の技術としては、例えば特開昭6
0−224248号公報に記載されるものがおった。以
下、その構成を図を用いて説明する。
(Prior art) Conventionally, as a technology in this field, for example, Japanese Patent Application Laid-open No. 6
There was one described in Publication No. 0-224248. The configuration will be explained below using figures.

第2図(1)〜(3)は従来の半導体装置の製造方法を
示す製造工程図である。この半導体装置は次のような工
程を経て製造される。
FIGS. 2(1) to 2(3) are manufacturing process diagrams showing a conventional method for manufacturing a semiconductor device. This semiconductor device is manufactured through the following steps.

■第2図(1)の工程 集積回路(IC)チップ等の半導体素子1上に形成され
たフィールド酸化l!2上において、バンプ電極形成予
定箇所にA〃電極パッド3を形成し、ざらにパッシベー
ション膜(不活性化膜)4を選択的に形成した後、その
上にアルミニウムAflの電流導通層5を蒸着する。次
に、電流導通層5上に選択的にチタンTiの密着金属層
6及び白金ptの拡散バリヤめっき層7を形成し、バン
プ電極形成予定箇所以外をめっき用のレジスタ膜8で覆
った後、電流導通層4に電流を流し、電気めっき法によ
って銅CuまたはニッケルNiの拡散バリヤめっき層9
を形成する。その後、鉛めっき層10及び錫めっき層1
1を形成する。
■Process shown in FIG. 2 (1) Field oxidation l! formed on a semiconductor element 1 such as an integrated circuit (IC) chip! 2, an electrode pad 3 is formed at the location where the bump electrode is to be formed, and a rough passivation film (inactivation film) 4 is selectively formed, and then a current conductive layer 5 of aluminum Afl is deposited thereon. do. Next, an adhesion metal layer 6 of titanium Ti and a diffusion barrier plating layer 7 of platinum PT are selectively formed on the current conducting layer 5, and areas other than the areas where bump electrodes are to be formed are covered with a resistor film 8 for plating. A current is passed through the current conducting layer 4, and a diffusion barrier plating layer 9 of copper Cu or nickel Ni is formed by electroplating.
form. After that, a lead plating layer 10 and a tin plating layer 1
form 1.

■第2図(2)の工程 レジスト層8をアクセント等の溶剤で除去した後、通常
のA、Qのエツチング液にて電流導通層5の一部をエツ
チングする。
(2) Process of FIG. 2(2) After removing the resist layer 8 with a solvent such as Accent, a part of the current conducting layer 5 is etched with a normal A or Q etching solution.

■第2図(3)の工程 加熱処理して釣めつき層10及び錫めっき層11を溶融
させ、鉛Pbと錫Snの合金化を行なって半球状の半田
からなるバンプ電極12を形成する。
■Process shown in FIG. 2 (3) The hooking layer 10 and the tin plating layer 11 are melted by heat treatment, and lead Pb and tin Sn are alloyed to form a bump electrode 12 made of hemispherical solder. .

このようにして作られたバンプ電極12は導電部材、例
えばフィルムキャリヤにおける半田めっきまたは錫めっ
きされた銅CU箔のリードフレーム13に、熱融着され
る。
The bump electrode 12 thus produced is heat-sealed to a conductive member, for example a lead frame 13 of solder-plated or tin-plated copper CU foil on a film carrier.

この種の製造方法では、白金の拡散バリヤめっき層7を
設けたので、銅またはニッケルの拡散バリヤめつき層9
を形成する際に、白金の活性剤処理を必要としない。ま
た、バンプ電極12の形成前において、鉛めっき層10
の外側を錫めっき層11で覆うため、電流導通層4の一
部をエツチングする際に、鉛めっき層10の上面がエツ
チング液で侵されない。そのため、活性剤処理が不要と
なって製造工程の簡略化、高信頼性のバリヤ効果が得ら
れるばかりか、高歩留りで半球状のバンプ形成処理が行
える。
In this type of manufacturing method, since a platinum diffusion barrier plating layer 7 is provided, a copper or nickel diffusion barrier plating layer 9 is provided.
No activator treatment of platinum is required to form the platinum. Furthermore, before forming the bump electrodes 12, the lead plating layer 10
Since the outside of the lead plating layer 10 is covered with the tin plating layer 11, the upper surface of the lead plating layer 10 is not attacked by the etching solution when a part of the current conducting layer 4 is etched. Therefore, activator treatment is not necessary, which not only simplifies the manufacturing process and provides a highly reliable barrier effect, but also enables hemispherical bump formation processing with high yield.

(発明が解決しようとする問題点) しかしながら、上記の製造方法では、次のような問題点
があった。
(Problems to be Solved by the Invention) However, the above manufacturing method has the following problems.

(i)  拡散バリヤめつき層9上に、鉛めっき層10
及び錫めっき層11という2種類のめつき処理を行うの
で、工程数が多くなるばかりか、2種のめつき槽を管理
、維持しなければならず、製造コストが高くなる。
(i) A lead plating layer 10 is formed on the diffusion barrier plating layer 9.
Since two types of plating processes, ie, the tin plating layer 11 and the tin plating layer 11, are performed, not only the number of steps increases, but also two types of plating tanks must be managed and maintained, which increases manufacturing costs.

(ii)  電流導通層4の一部をエツチング液で除去
する際に、第2図(2)のA部分における鉛めっき層1
0が腐食されてしまうばかりか、エツチング液の浸入に
より密着強度ヤJ信頼性が低下するおそれがある。
(ii) When removing a part of the current conductive layer 4 with an etching solution, the lead plating layer 1 in the part A of FIG.
Not only will the etching solution corrode, but there is a risk that the adhesion strength and reliability will decrease due to the infiltration of the etching solution.

(iii )  鉛めっき層10と錫めっき層11を合
金化して半田のバンプ電極12を形成する際に加熱処理
が必要となるため、加熱温度の管理に手数を要する。
(iii) Since heat treatment is required when alloying the lead plating layer 10 and the tin plating layer 11 to form the solder bump electrodes 12, it takes time and effort to control the heating temperature.

また、鉛と錫の合金化の際に、それらを良好に行うため
にフラックスを塗布、あるいは浸漬によって形成した後
、加熱処理をすることが多いが、この場合にはフラック
ス(flux)の形成工程だけ工程数が増え、製造効率
の低下とコスト高を招く。
In addition, when alloying lead and tin, in order to achieve good results, flux is often applied or immersed and then heat treated. This increases the number of steps, leading to lower manufacturing efficiency and higher costs.

(iv)  バンプ電極12を、例えば錫めっきされた
銅箔のリードフレーム13に接続する場合、Snめっき
にはボイスカー(whisker、猫のひげ)が発生す
ると一般的に云われているが、そのホイスカーは錫のメ
ッキ厚が薄いほど成長しやすく、例えば厚さ5μm以下
では成長速度が速くなる。このようなボイスカーがリー
ドフレーム13表面に発生していると、バンプ電極12
との接、涜時に接続不良をおこすおそれがある。
(iv) When connecting the bump electrode 12 to the lead frame 13 made of tin-plated copper foil, for example, it is generally said that Sn plating generates a voice car (whisker); The thinner the tin plating thickness is, the easier it is to grow. For example, when the thickness is 5 μm or less, the growth rate becomes faster. If such a voice car is generated on the surface of the lead frame 13, the bump electrode 12
There is a risk of a connection failure when connecting or tampering with the

本発明は前記従来技術が持っていた問題点として、めっ
き処理の煩雑化、鉛めっき層10の腐食と密着強度の低
下、フラックス形成による製造工程数の増加、リードフ
レーム13のボイスカー発生による接続不良の点などに
ついて解決した半導体装置の製造方法を提供するもので
ある。
The present invention solves the problems that the prior art had, complicating the plating process, corroding the lead plating layer 10 and reducing adhesion strength, increasing the number of manufacturing steps due to flux formation, and poor connection due to voice car formation in the lead frame 13. The present invention provides a method for manufacturing a semiconductor device that solves the above problems.

(問題点を解決するための手段) 本発明は前記問題点を解決するために、ICチップ等の
半導体素子上にバンプ電極を形成し、そのバンプ電極を
導電部材、例えばフィルムキャリヤのリードフレームに
熱融着する半導体装置の製造方法において、前記バンプ
電極は拡散バリヤめつき層上に錫めっきをした後、この
錫めっきを加熱処理により溶融させて所定形状に形成す
る。そして、リードフレームの表面に予め鉛めっき層を
形成しておき、この鉛めっき層に前記錫製バンプ電極を
熱融着するようにしたものである。
(Means for Solving the Problems) In order to solve the above problems, the present invention forms bump electrodes on a semiconductor element such as an IC chip, and connects the bump electrodes to a conductive member, such as a lead frame of a film carrier. In a method of manufacturing a semiconductor device by heat-sealing, the bump electrode is formed into a predetermined shape by plating tin on the diffusion barrier plating layer and then melting the tin plating by heat treatment. A lead plating layer is previously formed on the surface of the lead frame, and the tin bump electrode is heat-sealed to this lead plating layer.

(作 用) 本発明によれば、以上のように半導体装置のIt、4+
4造方法を構成したので、単一組成の錫めっき層はめっ
き処理の簡略化と、耐エツチング液性や密着強度を向上
させるように働く。錫製のバンプ電(々はホイスカーの
発生を防止し、しかも導電部材との接続時においてその
導電部材の鉛めつき層と半田合金を形成して接続強度を
向上させるように働く。従って前記問題点を除去できる
のでおる。
(Function) According to the present invention, as described above, it, 4+
Since four manufacturing methods are used, the tin plating layer having a single composition simplifies the plating process and improves etching resistance and adhesion strength. The tin bump electrodes prevent the generation of whiskers, and also form a solder alloy with the lead-plated layer of the conductive member when connected to the conductive member, thereby improving the connection strength.Thus, the above-mentioned problem can be solved. It is possible to remove points.

(実施例) 第り図(1)〜(4)は本発明の実施例を示す半導体装
置の製造工程図である。この半導体装置は、次のような
工程を経て製造される。
(Example) Figures (1) to (4) are manufacturing process diagrams of a semiconductor device showing an example of the present invention. This semiconductor device is manufactured through the following steps.

■第1図(1)の工程 集積回路(IC)チップ等の半導体素子11上に形成さ
れたフィールド駿化膜12上において、バンプ電極形成
予定箇所にAj等の電極パッド13を形成し、ざらにC
VD(Chemical Vapor Deposit
ion)法等でパッシベーション膜14を成長させた後
、ホトリソ技術により電極パッド13上にバンプ形成エ
リヤを開孔する。
■ On the field film 12 formed on the semiconductor element 11 such as the process integrated circuit (IC) chip shown in FIG. niC
VD (Chemical Vapor Deposit)
After the passivation film 14 is grown using the ion method or the like, bump forming areas are opened on the electrode pads 13 using photolithography.

次に、半導体素子11の全面に、へρ等からなる電流導
通層15を蒸着法等で形成し、その電流導通層15上に
チタンT1等の密着金属層16及び白金Pt等の拡散バ
リヤめつぎ層17を形成した後、それらの密着金属層1
6及び拡散バリヤめつき層17におけるバンプ電極形成
箇所以外の部分をホトリソ技術により除去する。ここで
、密着金属層16はフィールド酸化膜12及び電極パッ
ド13への密着機能を有している。
Next, a current conducting layer 15 made of ρ or the like is formed on the entire surface of the semiconductor element 11 by a vapor deposition method or the like, and an adhesion metal layer 16 such as titanium T1 and a diffusion barrier layer such as platinum Pt are formed on the current conducting layer 15. After forming the next layer 17, those adhesive metal layers 1
6 and the diffusion barrier plating layer 17 other than the portion where the bump electrode is to be formed are removed by photolithography. Here, the adhesive metal layer 16 has a function of adhering to the field oxide film 12 and the electrode pad 13.

ざらに、ホトリソ技術を用いて密着金属層16及び拡散
バリヤめつき層17の外縁部付近をめっき用のレジスト
膜18で覆った後、電流導通層15に通電して電気めっ
き法によって拡散バリヤめつき層17上に、銅CU、ニ
ッケルNi等の拡散バリヤめつき層19を形成する。拡
散バリヤめつき層19は、厚みが例えば5〜10μm程
に形成される。
Roughly, the vicinity of the outer edges of the adhesion metal layer 16 and the diffusion barrier plating layer 17 are covered with a resist film 18 for plating using photolithography, and then the current conducting layer 15 is energized to form a diffusion barrier plate by electroplating. A diffusion barrier plating layer 19 of copper CU, nickel Ni, etc. is formed on the plating layer 17 . The diffusion barrier plating layer 19 is formed to have a thickness of, for example, about 5 to 10 μm.

続いて、拡散バリヤめつき層19上に錫めっき層20を
形成する。ここで、拡散バリヤめっき層17゜19は、
錫めっき層20と電極パッド13との相互拡散を防止す
る機能を有している。
Subsequently, a tin plating layer 20 is formed on the diffusion barrier plating layer 19. Here, the diffusion barrier plating layer 17°19 is
It has a function of preventing mutual diffusion between the tin plating layer 20 and the electrode pad 13.

■第1図(2)の工程 めっき用のレジスト膜18をアセトン等の溶剤で除去し
た後、電流導通層15の外縁部を、例えばりん酸、硝酸
、氷酢酸、水の混合液からなるエツチング液でエツチン
グして除去する。
■ After removing the resist film 18 for process plating shown in FIG. 1 (2) with a solvent such as acetone, the outer edge of the current conducting layer 15 is etched with a mixture of phosphoric acid, nitric acid, glacial acetic acid, and water, for example. Remove by etching with liquid.

■第1図(3)の工程 錫めっき層20の球状化と内部の有機物除去の目的で、
N2等の雰囲気下において該錫めつき層20を温度34
0〜350 ’C程度に加熱する。すると、錫めっき層
20が半球化して錫製のバンプ電極21が得られる。こ
のバンプ電極21の高ざは、例えば25μm〜100μ
m程度に形成される。
■Process in Figure 1 (3) For the purpose of spheroidizing the tin plating layer 20 and removing internal organic matter,
The tinned layer 20 is heated to a temperature of 34°C in an atmosphere such as N2.
Heat to about 0-350'C. Then, the tin plating layer 20 becomes hemispherical and a bump electrode 21 made of tin is obtained. The height of the bump electrode 21 is, for example, 25 μm to 100 μm.
It is formed to about m.

■第1図(4)の工程 バンプ電極21と接続する導電部材、例えばフィルムキ
ャリヤ30を予め用意しておく。
(4) Process A conductive member, such as a film carrier 30, to be connected to the process bump electrode 21 in FIG. 1(4) is prepared in advance.

フィルムキャリヤ30は、チップ取付は用の孔をもった
フィルムテープ31を有し、そのフィルムテープ31上
には銅箔等のリードフレーム32が形成され、そのリー
ドフレーム32のインナリード部32aが前記孔中に突
出した構造をしている。従来はインナリード部32aの
表面に例えば半田めっき、または錫めっきが施されてい
るが、本実施例ではこのインナリード部32aの表面に
鉛めっき層33を形成しておく。
The film carrier 30 has a film tape 31 with a hole for chip attachment, and a lead frame 32 made of copper foil or the like is formed on the film tape 31, and an inner lead portion 32a of the lead frame 32 is formed on the film tape 31. It has a structure that protrudes into the hole. Conventionally, the surface of the inner lead portion 32a is plated with solder or tin, but in this embodiment, a lead plating layer 33 is formed on the surface of the inner lead portion 32a.

そしてインナリード部32aをバンプ電極21に当てが
って、例えば温度340〜350 ’C程度の加熱処理
を行う。すると、バンプ電極21の錫とインナリード部
32aの鉛めっき@33とが溶融し、それらが合金化さ
れて半田層40が形成され、この半田層40によりバン
プ電極21とインナリード部32aとが接続される。そ
の後、フィルムテープ32の所定箇所を切断したり、半
田層40を含む半導体素子11を樹脂封止する等の工程
を経て、所望の半導体装置を得る。
Then, the inner lead portion 32a is applied to the bump electrode 21, and heat treatment is performed at a temperature of, for example, about 340 to 350'C. Then, the tin of the bump electrode 21 and the lead plating @33 of the inner lead portion 32a are melted and alloyed to form a solder layer 40, and this solder layer 40 connects the bump electrode 21 and the inner lead portion 32a. Connected. Thereafter, a desired semiconductor device is obtained through steps such as cutting the film tape 32 at predetermined locations and sealing the semiconductor element 11 including the solder layer 40 with resin.

本実施例は、次のような利点を有する。This embodiment has the following advantages.

(a)第1図(2)の工程において、電流導通層15の
外縁部をエツチング液で除去する際、錫めっき層20は
エツチング液には侵されないので、該錫めつき層20の
密着強度が低下せず、そのため信頼性が向上する。しか
も、この錫めっき層2oは、錫の単一組成で形成される
ため、めっき処理が簡単となる。
(a) In the process of FIG. 1(2), when the outer edge of the current conducting layer 15 is removed with an etching solution, the tin plating layer 20 is not attacked by the etching solution, so the adhesion of the tin plating layer 20 is strong. does not decrease, thereby improving reliability. Moreover, since the tin plating layer 2o is formed of a single composition of tin, the plating process is simple.

(b)第1図(3)の工程において、錫製バンプ電極2
1はその高さが例えば20〜100μm程度と大きく、
しかも球状化のために加熱処理され、錫めっき内に存在
するめつき応力等が放出されるため、ボイスカーが発生
しにくい。同様に、第1図(4)の工程において、イン
ナリード部32aに形成されためつき層33は鉛めつき
であるため、ボイスカーが発生しない。このように、バ
ンプ電極21側及びインナリード部32a側にボイスカ
ーが発生しないため、それら両者間の接続時において接
続不良等の問題も生じない。
(b) In the process of FIG. 1 (3), the tin bump electrode 2
1 has a large height, for example, about 20 to 100 μm,
Moreover, since the tin plating is heat-treated to make it spherical and the plating stress present in the tin plating is released, voice ker is less likely to occur. Similarly, in the process shown in FIG. 1(4), since the plating layer 33 formed on the inner lead portion 32a is lead-plated, no voice car occurs. In this manner, since no voice car is generated on the bump electrode 21 side and the inner lead portion 32a side, problems such as poor connection do not occur when connecting these two.

しかも、バンプ電極21とインナリード部32aの接続
箇所は半田層40となるので、低融点での接続が可能と
なり、また大きな接着強度が得られる。
Moreover, since the solder layer 40 is used at the connection point between the bump electrode 21 and the inner lead portion 32a, connection at a low melting point is possible, and high adhesive strength can be obtained.

なお、上記実施例において、半導体素子側の各層の材質
や形状、おるいはバンプ電極21の形状、ざらには導電
部材の形状、構造、材質等を、図示以外のものに変形す
ることは可能でおる。
In the above embodiments, it is possible to change the material and shape of each layer on the semiconductor element side, the shape of the bump electrode 21, and the shape, structure, material, etc. of the conductive member other than those shown in the drawings. I'll go.

(発明の効果) 以上詳細に説明したように、本発明によれば、バンプ電
極を錫の単一組成で形成すると共に、それと接続する導
電部材側に鉛めっき層を形成したので、バンプ電極形成
時におけるめっき処理の簡単化、電流導通層の一部のエ
ツチング時における錫めっき層の耐エツチング液性の向
上と密着強度の低下防止、ホイスカーの発生防止、バン
プ電極と導電部材との接続時における低融点での接着と
その強度の向上化等が計れる。従って製造効率や信頼性
の向上、低コスト化という効果が期待できる。
(Effects of the Invention) As described above in detail, according to the present invention, the bump electrode is formed with a single composition of tin, and a lead plating layer is formed on the side of the conductive member connected thereto, so that the bump electrode can be formed. simplification of the plating process when etching a part of the current conductive layer, improvement of the etching resistance of the tin plating layer and prevention of decrease in adhesion strength, prevention of whisker generation, Adhesion at a low melting point and improvement of its strength can be achieved. Therefore, the effects of improved manufacturing efficiency, reliability, and cost reduction can be expected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(1)〜(4)は本発明の実施例を示す製j古工
程図、第2図(1)〜(3)は従来の製造工程図である
。 11・・・・・・半導体素子、12・・・・・・フィー
ルド酸化膜、13・・・・・−電極パッド、14・・・
・・・パッシベーション膜、15・・・・・・電流導通
層、16・・・・・・密着金属層、17.19・・・・
・・拡散バリヤめつき層、18・・・・・・レジスト膜
、18゜20・・・・・・錫めっき層、21・・・・・
・バンプ電極、30・・・・・・フィルムキャリヤ、3
2・・・・・・リードフレーム、33・・・・・・鉛め
っき層、40・・・・・・半田層。 出願人代理人  柿  本  恭  成本発8月の第寂
LD哩図 第1図 第1図 第2図 往来の製造二惺図 第2図
Figures 1 (1) to (4) are old manufacturing process diagrams showing an embodiment of the present invention, and Figures 2 (1) to (3) are conventional manufacturing process diagrams. 11...Semiconductor element, 12...Field oxide film, 13...-electrode pad, 14...
... Passivation film, 15 ... Current conduction layer, 16 ... Adhesion metal layer, 17.19 ...
...Diffusion barrier plating layer, 18...Resist film, 18°20...Tin plating layer, 21...
・Bump electrode, 30...Film carrier, 3
2... Lead frame, 33... Lead plating layer, 40... Solder layer. Applicant's agent: Takashi Kakimoto Diagram of Jaku LD in August from Narimoto Figure 1 Figure 1 Figure 2 Figure 2

Claims (1)

【特許請求の範囲】 半導体素子上のバンプ電極形成予定箇所以外を絶縁膜で
被覆し、この絶縁膜を含む前記半導体素子上に電流導通
層をめっきし、次いでバンプ電極形成予定箇所に密着お
よび拡散バリヤ用の金属層を形成し、前記電流導通層に
通電して前記金属層上に拡散バリヤめつき層を形成した
後、この拡散バリヤめつき層上に所定形状のバンプ電極
を形成し、このバンプ電極を導電部材に熱融着する半導
体装置の製造方法において、 前記バンプ電極は、前記拡散バリヤめっき層上に錫めっ
きをした後、この錫めつきを加熱処理により溶融させて
形成し、 この錫製バンプ電極を、前記導電部材の表面に予め形成
しておいた鉛めつき層と熱融着することを特徴とする半
導体装置の製造方法。
[Claims] Covering the semiconductor element with an insulating film other than the part where the bump electrode is to be formed, plating a current conducting layer on the semiconductor element including the insulating film, and then adhering and diffusing the part where the bump electrode is to be formed. After forming a metal layer for a barrier and applying current to the current conducting layer to form a diffusion barrier plating layer on the metal layer, a bump electrode of a predetermined shape is formed on the diffusion barrier plating layer. In a method for manufacturing a semiconductor device in which a bump electrode is heat-sealed to a conductive member, the bump electrode is formed by plating tin on the diffusion barrier plating layer and then melting the tin plating by heat treatment. A method for manufacturing a semiconductor device, characterized in that a tin bump electrode is thermally fused to a lead-plated layer previously formed on the surface of the conductive member.
JP61136972A 1986-06-12 1986-06-12 Manufacture of semiconductor device Pending JPS62293650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61136972A JPS62293650A (en) 1986-06-12 1986-06-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61136972A JPS62293650A (en) 1986-06-12 1986-06-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62293650A true JPS62293650A (en) 1987-12-21

Family

ID=15187776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61136972A Pending JPS62293650A (en) 1986-06-12 1986-06-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62293650A (en)

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