JPS6229272A - Automatic frequency pull-in circuit - Google Patents

Abstract

PURPOSE:To generate a signal phase-locked with a horizontal synchronizing signal in a compound video signal and to display a fine image by inputting the output of a frequency-voltage converter and that of a phase comparator to an amplifier, inputting the output of the amplifier to a voltage controlled oscillator as control voltage and phase-comparating the output of the voltage controlled oscillator with that of an equalizing pulse eliminating circuit. CONSTITUTION:The output of an equalizing pulse eliminating circuit 12 is supplied to a phase comparator 18 through a gate circuit 16 and is phase-compared with the output of a divider 22 supplied through a gate circuit 20. The output of the phase comparator 18 is supplied to and amplified and an amplifier 28 through a low-pass filter 24. Also, the output voltage of a frequency-voltage converter 14 is supplied to the amplifier 26 and adds an offset signal on the output of the amplifier 26. The output of the amplifier 26 is supplied to a voltage controlled oscillator 30 and its output is supplied to the divider 22. The output of the divider 22 is, for example, supplied to the horizontal deflection circuit of a monitoring receiver, triggering the horizontal deflection circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic frequency acquisition circuit, and more particularly to an automatic frequency acquisition circuit that obtains a signal synchronized with a horizontal synchronization signal from a video signal device or the like.

There are cases where there is no cut pulse in the vertical synchronization signal of a composite video signal output from a video signal device, such as a CT scan device, or even if there is a cut pulse, the timing is shifted. Generally, cutting pulses are inserted at intervals of 172H during the vertical synchronization signal. However, if there is no cutting pulse or the timing is off as described above, when trying to display an image on a monitor receiver after receiving a composite video signal from a video signal device, the relevant This causes the problem of image distortion. especially,
In the case of the interlaced display method, the scanning line of the even field does not fall in the center between the scanning lines of the odd field, and the quality of the displayed image deteriorates. For this reason, for example, in an image recording device that captures a video signal from video signal equipment used for disease diagnosis, displays it on a monitor receiver, and records the displayed image by taking a photograph, it is difficult to record the recorded image. If this happens, detailed information about the affected area will no longer be displayed, creating an opportunity for misdiagnosis, which is a major inconvenience.

In addition, in such image recording devices, raster erase is generally performed in which new scanning lines are inserted between the scanning lines of the monitor receiver to make the scanning lines of the recorded image less noticeable. There is a problem that lines cannot be inserted at equal intervals.

The present invention has been made to overcome the above-mentioned disadvantages, and is an automatic frequency control system capable of displaying precise images by generating a signal that is phase-synchronized with the horizontal synchronization signal in the composite video signal. The purpose is to provide a lead-in circuit.

In order to achieve the above object, the present invention provides an equalization pulse removal circuit that is supplied with a synchronization signal separated from a composite video signal and alternately removes equalization pulses to obtain a horizontal synchronization signal, and an equalization pulse removal circuit. A frequency-to-voltage converter that converts the output signal frequency of
The output of the frequency-voltage converter and the output of the phase comparator are input to the amplifier, and the output of the amplifier is input as a control voltage to the voltage controlled oscillator, and the output of the voltage controlled oscillator and the equalization are input. It is characterized in that the phase of the output of the pulse removal circuit is compared by the phase comparator.

Therefore, the phase of the output signal of the voltage controlled oscillator is in phase synchronization with the horizontal synchronization signal separated from the composite video signal, and is automatically drawn into the horizontal synchronization signal.

Next, preferred embodiments of the automatic frequency pull-in circuit according to the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 1 shows a block diagram showing the configuration of one embodiment of the present invention.

Therefore, the input terminal 10 is supplied with a synchronization signal separated from the composite video signal. This composite video signal is, for example, C
This is the output from the T-scan device. Input terminal 1
The synchronizing signal supplied to 0 is supplied to an equalization pulse removal circuit 12 consisting of a monostable multivibrator. The monostable multivibrator constituting the equalization pulse removal circuit 12 is set to generate a 3/4H width pulse in response to its trigger signal. The reason why the pulse width is set to 374H is that it is assumed that even if an equalization pulse exists and its pulse position is shifted, it will not exceed an intermediate value between 1H and 1/2H.

The output of the equalization pulse removal circuit 12 is sent to the frequency-voltage converter 1.
4 and is converted into a voltage, and the converted voltage is fed back to the monostable multivibrator constituting the equalization pulse removal circuit 12 to control the time constant of the monostable multivibrator to adjust the output pulse width of the monostable multivibrator. 374H
is controlled. In this embodiment, the frequency-voltage converter 14 includes a pulse shaping circuit 14a driven by an output pulse from the equalizing pulse removal circuit 12, and a low-pass filter 14b smoothing the output of the pulse shaping circuit 14a. It is composed.

On the other hand, the output of the equalization pulse removal circuit 12 is output from the gate circuit 16.
A frequency divider 22 (described later) is supplied to the phase comparator 18 via a gate circuit 20.
The phase is compared with the output of The output of the phase comparator 18 is supplied to an amplifier 26 via a low-pass filter 24 for amplification. The output voltage of the frequency-to-voltage converter 14 is also supplied to an amplifier 26 to add an offset signal to the output of the amplifier 26.

The output of the amplifier 26 is supplied to a voltage controlled oscillator 3o, and the output of the voltage controlled oscillator 30 is supplied to a frequency divider 22. The output of frequency divider 22 is applied as a horizontal synchronization signal to, for example, a horizontal deflection circuit of a monitor receiver to trigger the horizontal deflection circuit. Note that the free-running oscillation frequency of the voltage controlled oscillator is N
Set it to fh.

On the other hand, the synchronization signal supplied to the input terminal 10 is supplied to the vertical synchronization signal separation circuit 28 to separate the vertical synchronization signal.

The vertical synchronization signal separated by the vertical synchronization signal separation circuit 28 is supplied to the gate circuits 16 and 20, and the gates of these gate circuits 16 and 20 are closed by this vertical synchronization signal.

Therefore, in one embodiment of the present invention configured as described above, the synchronization signal input to the input terminal 10 is as shown in FIG.
The waveform shape shown in a) is shown.

Therefore, the monostable multivibrator of the equalization pulse removal circuit 12 is triggered by the fall of the synchronization signal shown in FIG. 2(a), and the equalization pulse and cutting pulse inserted at the 1/2H position are removed and equalized pulse removal circuit 1
The outputs of 2 have an interval of 1H as shown in FIG. 2(b). This increases the output pulse width of the equalization pulse removal circuit 12, that is, the output pulse width of the monostable multivibrator, by 3
This is because it is set to 74H, and the equalization pulse and /
Or, even if the position of the cutting pulse is shifted, 1/2H to 3/4H
Every other equalization pulse and cutting pulse will be removed unless the period exceeds .

The output of the pulse shaping circuit 14a that receives the output of the equalization pulse removal circuit 12 is as shown in FIG. It becomes as shown in (d). This signal is fed back to the equalization pulse removal circuit 12 as described above. Therefore, the frequency of the output of the equalization pulse removal circuit 2 is controlled to maintain a pulse width of 3/4H.

On the other hand, the vertical synchronization signal separated in the vertical synchronization signal separation circuit 28 from the synchronization signal supplied to the input terminal 10 becomes as shown in FIG. 2 (61), and the vertical synchronization signal period shown in FIG. The gates of the gate circuits 16 and 20 are open except during the low potential period in FIG. The phase is compared,
The phase comparison output is as shown in FIG. 2 (fl).

This phase comparison output is smoothed by a low pass filter 24. On the other hand, during the vertical synchronization signal period, the gates of gate circuits 16 and 20 are closed and the phase comparison input is cut off. Therefore, the phase comparison output retains its immediately previous value. The output of the low-pass filter 24 is shown in Fig. 2 (
It becomes as shown in a.

Incidentally, the output of the low-pass filter 24 is amplified by the amplifier 26, and in this case, the output voltage of the frequency-voltage converter 14 is applied to the amplifier 26. As a result, the output of the amplifier 26 has an offset added thereto depending on the output voltage of the frequency-voltage converter 14, that is, the frequency of the input synchronizing signal, and is further corrected by the output of the low-pass filter 24. . Therefore, responsiveness to the horizontal synchronization signal is improved.

Since the output voltage of the amplifier 26 is input to the voltage controlled oscillator 30, the output frequency of the voltage controlled oscillator 30 is also input to the input terminal 1.
The frequency Nf depends on the frequency of the horizontal synchronizing signal supplied to 0 and is corrected by the phase difference of the re-input input to the phase comparator 18, and is the frequency Nf shown in FIG. 2(h).
The output of h is output from the voltage controlled oscillator. Note that reference symbol fh indicates the horizontal synchronization signal frequency in the synchronization signal supplied to the input terminal 10.

The output from the voltage controlled oscillator 30 is divided into 1 by the frequency divider 22.
/H. Therefore, from the frequency divider 22 to the input terminal 1
The signal shown in FIG. For comparison with the high case, FIG. 3 shows the output waveform corresponding to FIG. 2.

As explained above, according to the present invention, unnecessary equalization pulses are removed by receiving a synchronization signal separated from a composite video signal,
PLL that takes as input a signal from which unnecessary equalization pulses have been removed
Since a circuit is provided to obtain a signal that is phase-synchronized with the signal from which unnecessary equalization pulses have been removed, this phase-synchronized signal can be used as a horizontal synchronization signal.

Further, since an offset is added to the output of the amplifier constituting the PLL circuit by the output of the frequency-voltage converter, there is also the effect of improving the responsiveness to the horizontal synchronizing signal.

Although the present invention has been described above with reference to preferred embodiments, the present invention is not limited to these embodiments.
Of course, various improvements and changes in design are possible without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention,
2 and 3 show waveform diagrams illustrating the invention in detail. 10... Input terminal 12... Equalization pulse removal circuit 14... Frequency-voltage converter 14a... Pulse shaping circuit 14b... Low pass filter 16... Gate circuit 18... Phase comparator 20... Gate circuit 22... Frequency divider 2
4...Low pass filter 26...Amplifier 28...
・Vertical synchronization signal separation circuit 30... Voltage controlled oscillator patent applicant Fuji Photo Film Co., Ltd. Same as above Ikegami Tsushinki Co., Ltd.

Claims (2)

[Claims] (1) An equalization pulse removal circuit that is supplied with a synchronization signal separated from the composite video signal and alternately removes equalization pulses to produce a horizontal synchronization signal, and converts the output signal frequency of the equalization pulse removal circuit into a voltage. comprising a frequency-voltage converter, and a PLL circuit composed of at least a phase comparator, a voltage-controlled oscillator, and an amplifier, the output of the frequency-voltage converter and the output of the phase comparator being input to the amplifier; , the output of the amplifier is input as a control voltage to the voltage controlled oscillator, and the phase of the output of the voltage controlled oscillator and the output of the equalization pulse removal circuit is compared by the phase comparator. circuit. (2) In the circuit according to claim 1, the equalization pulse removal circuit includes a monostable multivibrator that uses the output of the frequency-voltage converter as a control signal, and the output of the monostable multivibrator An automatic frequency pull-in circuit characterized in that the pulse width is selected to be more than 1/2H and less than 1H.