JPS62292013A - Interface system between comparator and logic circuit - Google Patents

Abstract

PURPOSE:To suppress the increase of power consumption, by providing a gate circuit which controls the output of a comparator between the comparator having the cancel function of an offset voltage, and a MOS logic circuit. CONSTITUTION:A comparator 6 is constituted of switched capacitors 1-4, and an operational amplifier, and has the cancel function of an offset voltage VOFF. A NOR gate 23 is provided between the output 9 of the circuit 6, and a CMOS logic circuit 13. The terminal 26 of the gate 23 is controlled at a level '0' at the time of performing no offset cancel function by the circuit 6. Thereby, the inversion level of the output 9 of the circuit 6 is outputted to the output terminal 25 of the gate 23, and it is inputted as it is to the circuit 13. Since a transistor Tr15 is turned off by controlling the terminal 26 at a level '1' while executing the offset cancel function, no through current is permitted to flow through the circuit 23 itself, and a Tr18 is energized, then the terminal 25 is set at the level '0l compulsorily. Therefore, no through current is permitted to flow from the circuit 6 to the circuit 13 by the action of the circuit 23, thereby, it is possible to reduce the power consumption.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an interface system between a comparison circuit and a logic circuit, and in particular, an interface system between a comparison circuit and a cMOS logic circuit composed of a switched capacitor and an operational amplifier. Concerning interface methods.

[Conventional technology]

Conventionally, a comparison circuit that combines a switched capacitor and an operational amplifier with an offset voltage canceling function has been developed by B. E.
eL al), Switched Capacitor Circ (5w1tcbed Capacitor Circ)
units), Pan Nosl ~ Rand Reinhold (
Published by Van No5Lrand Re1nhold),
For circuits other than the comparison circuit, see Chiba.

Kudo, Kido [Switched capacitor type summing amplifier ■c that automatically compensates for offset voltage], Institute of Electronics and Communication Engineers Technical Research Report CAS 82-83 (March 1983) has been published. Both of these attempt to cancel the offset voltage of an operational amplifier using a switch and a capacitor.

FIG. 3 is a circuit diagram of an example of a circuit in which a conventional comparison circuit and a CMOS logic circuit are connected.

In FIG. 3, a circuit surrounded by a broken line 6 is a comparison circuit constructed by combining a switched capacitor and an operational amplifier, and a circuit surrounded by a broken line 13 is a CMOS logic circuit. The operation of this comparison circuit 6 will be explained.

First, when switch 1 is opened and switches 2 and 3 are closed, capacitor 4 is connected to positive phase input terminal 8 and output terminal 9.
is charged to a voltage equal to the potential difference between At this time, if the input offset voltage of the operational amplifier 5 is VoFF and the potential of the positive phase input terminal 8 is V8, the voltage ■c charged in the capacitor 4 is V c = V OFF + V oo/
2 Vs. This operation is called an offset cancellation function. During this time, the potential 9 of the output terminal 9 is approximately the midpoint potential (power supply potential) Next, switches 2 and 3 open, and conversely switch 1 closes.If the potential of the negative phase input terminal 7 is V7, then the operational amplifier The potential VIO of the negative phase input terminal 10 of No. 5 is as follows: yIO= V7 +VC= V 7 + V Opp
+V DD/'2V8. Therefore, the potential difference 1 between the negative phase input terminal and the positive phase input terminal of the operational amplifier 5 is V + =V+o (VOFF +Voo/2)
-V7V8. In other words, due to the offset cancellation function,
Offset voltage V□pp is canceled out. As a result, V
7>V8, the output terminal 9 is at the "0" level, V7
(If it is VB, it can be seen that the output terminal 9 is at the °“1°” level. The above is the operation of the comparator circuit 6.

The output terminal 9 of the comparison circuit 6 is directly connected to the CMOS logic circuit 13, and the voltage comparison result of the comparison circuit 6 is digitally processed in the subsequent logic circuit.

[Problem that the invention seeks to solve]

In the conventional logic integrated circuit described above, a large current may flow while the comparator circuit 6 executes the offset cancel function. This is because during that period, as mentioned above, the potential of the output terminal 9 of the comparator circuit 6 is almost equal to the midpoint potential, and the CMOS
At the input stage of the logic circuit 13, the P-channel MOS transistor 11 and the N-channel MO3 transistor 12 are both conductive, and a large through current I flows from the power supply VDD to the ground. This is because 0 flows. Furthermore, since the output terminal 14 of the input stage also has an unstable intermediate potential, there is a risk that a through current may flow to the gate of the subsequent stage, resulting in an increase in power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interface system between a comparison circuit and a logic circuit that can prevent a through current from flowing during execution of an offset cancel function, and thus suppress an increase in power consumption.

[Means for solving problems]

The interface system of the comparison circuit and logic circuit of the present invention is such that the comparison circuit is composed of a switched capacitor and an operational amplifier and has an offset voltage canceling function, and the CM
an OS logic circuit, an output terminal of the comparison circuit, and the CMO
It is connected between the input terminal of the S logic circuit, and during a period when the comparator circuit is not performing the offset voltage canceling function, the output of the comparator circuit is passed through at the same or inverted level and sent to the CMOS logic circuit. The CMOS logic circuit is configured to include a control gate that sets the CMOS logic circuit to either a power supply potential or a ground potential during a period in which the comparator circuit executes an offset voltage canceling function.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

This first embodiment is an example in which a NoR gate is used as a control gate. Comparison circuit 6 and CMOS logic circuit 13 are the same circuits as in the conventional example shown in FIG. In this embodiment, the output terminal 9 of the comparison circuit 6 and the first input terminal of the NOR gate 23 are connected, and the output terminal 25 of the NOR gate 23 is connected to the input terminal of an external CMOS logic circuit.

If the offset cancel function is not being executed, select NO.
The second input terminal 26 of the R gate 23 is externally controlled to a logic "O" level. As a result, the NOR gate 23
The inverted level of the output terminal 9 of the comparator circuit 6 is outputted to the output terminal 25 of the comparator circuit 6, and inputted as is to the CMO8 logic circuit 13.

On the other hand, while the offset cancel function is being executed, the second input terminal 26 of the NOR gate 23 is externally controlled to the logic "1" level. No through current flows, and moreover, the N-channel transistor 18 becomes conductive, and the output terminal 25 of the NOR gate 23 is forced to the logic "O" level (the potential of the output terminal 25 becomes almost the ground potential). Comparator circuit Although the potential of the output terminal 9 of 6 is a midpoint potential, this midpoint potential is not input to the CMOS logic circuit 13 due to the action of the NOR circuit 23.NOR
Since the potential of the output terminal 25 of the gate 23 is approximately the ground potential, no through current flows in the subsequent CMOS logic circuit either.

In the first embodiment described above, the NOR gate 23 is used as the control gate, and if the control gate is the inverter connected next to the NOR gate 23, when the offset cancel function is not executed, the comparator circuit 6 The output of the CMOS logic circuit 13 is input to the CMO8 logic circuit 13 at the same logic level, and the input terminal of the CMOS logic circuit 13 can be set to logic "1" (potential approximately equal to the power supply voltage VDD) while the offset cancel function is being executed. Even if you do this, CMO
No through current flows through the S logic circuit 13.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

This second embodiment is an example in which a NAND gate is used as a control gate. The comparator circuit 6 and the CMO8 logic circuit 13 are the same as those in the conventional example shown in FIG.

When the offset cancel function is not executed, set to NA.
The second input terminal 28 of the ND gate is externally controlled to a logic ``1'' level. As a result, the inverted level of the output terminal 9 of the comparator circuit 6 is outputted to the output terminal 27 of the NAND gate, and inputted as is to the CMO8 logic circuit 13.

On the other hand, while the offset cancel function is being executed, the NAND
The second input terminal 28 of gate 24 is externally controlled to a logic "o" level. As a result, the N-channel transistor 22 is turned off, so that no through current flows through the NAND gate 24 itself. Moreover, the P-channel transistor 20 becomes conductive, and the output terminal 27 of the NAND gate 24 is forced to the logic level 1". (The potential of the output terminal 27 is approximately equal to the power supply potential VDD.) Therefore, no through current flows in the subsequent CMOS logic circuit either.

In the second embodiment, the NAND gate 24 is used as the control gate, but if the control gate is an inverter connected next to the NAND gate 24, the comparison circuit 6 is used when the offset cancel function is not executed. input to the CMOS logic circuit 13 at the same logic level as the output of
During execution of Offcella 1 to Cancel function, the input terminal of the CMOS logic circuit 13 can be set to logic "0" (potential approximately equal to ground potential).
No through current flows through the logic circuit 13.

As explained above, the comparison circuit 6 and the CMOS logic circuit 1
By connecting a control gate between 3 and 3 and setting the potential of the input end of the CMOS logic circuit to the ground potential or power supply potential while the offset canceling function is being executed, it is possible to prevent a through current from flowing.

〔Effect of the invention〕

As explained above, in the present invention, a control gate is connected between the comparison circuit having the offset/I cancel function and the C0M5 logic circuit, and when the offset/I to cancel function is not executed, the comparison circuit is The output is sent to the CMO8 logic circuit at the same logic level or the inverted level, and the output of the control gate is sent to the CMO8 logic circuit at the same logic level or the inverted level.
o” or logic “1” and the input terminal potential of the CMOS logic circuit is set to a potential approximately equal to the ground potential or power supply potential, so that it is possible to prevent a through current from flowing during the execution of the offset cancel function. is possible,
This has the effect of reducing power consumption.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a first embodiment of the present invention, Fig. 2 is a circuit diagram of a second embodiment of the invention, and Fig. 3 is a circuit connecting a conventional comparison circuit and a CM OS logic circuit. It is a circuit diagram of an example. 1.2.3...Switch, 4...Capacitor, 5.
...Operation amplifier, 6... Comparison circuit, 7... Negative phase input terminal, 8... Positive phase input terminal, 9... Output terminal, 10
...Reverse phase input terminal, 11, 15, 16, 19.20.
...P-channel MoS transistor, 12.17.18
．． 21.22...N channel MOS transistor, 1
3... CMOS logic circuit, 14... Output terminal, 23
...NOR gate, 24...NAND gate, 25
...Output terminal, 16...Second input terminal, 27...
- Output terminal, 28... second input terminal.

Claims (1)

[Claims] A comparison circuit consisting of a switched capacitor and an operational amplifier and having an offset voltage canceling function, and a CMO
an S logic circuit, an output terminal of the comparison circuit, and the CMOS
The comparator circuit is connected between the input terminal of the logic circuit and, during a period when the comparator circuit is not performing the offset voltage canceling function, the output of the comparator circuit is passed at the same or inverted level and sent to the CMOS logic circuit. An interface method for a comparison circuit and a logic circuit, characterized in that the comparison circuit includes a control gate that sets the CMOS logic circuit to either a power supply potential or a ground potential during a period when the comparison circuit is performing an offset voltage canceling function. .