JPH04177913A - Input level decision circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to reduce the power consumption by setting an input voltage applied to plural inverters to be a prescribed level corresponding to a threshold level with the resistance division ratio of a resistor connection circuit when the input signal given to an input terminal is at an open level. CONSTITUTION:Inverters whose threshold level differ from each other are employed for a 1st inverter 1 and a 2nd inverter 2, and inverters used for signal polarity inversion usually are employed for 3rd-5th inverters 3-5. Moreover, a 1st resistor R1 and a 2nd resistor R2 are used to divide a power supply voltage VDD. An input voltage when the input terminal IN is open depends on a ratio of resistance of the 1st resistor R1 and the 2nd resistor R2. A logical threshold level of the 1st inverter 1 is set higher than an input voltage VR and a logical threshold level of the 2nd inverter 1 is set lower than the input voltage VR. Thus, the circuit constitution is simplified and the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an input level determination circuit, and in particular, the present invention relates to an input level determination circuit, and in particular, the present invention relates to an input level determination circuit that determines input level determination circuits.
This is suitable for use in a level determination circuit into which a value level is input.

<Summary of the Invention> The input level determination circuit of the present invention connects a plurality of inverters with different threshold values in parallel, and selectively operates these inverters to determine the level of an input signal. A voltage generation circuit is configured by connecting a plurality of resistors in series, and an input signal is supplied to a connection point of the resistors in the voltage generation circuit, and the input signal is supplied to the level determination circuit via the connection point. By applying a signal, the logic threshold of the inverter can be controlled by the voltage generated by the voltage generation circuit when the input signal level is open level, and the multi-value signal level can be controlled. This is an input level determining circuit that has a simplified circuit configuration and can reduce power consumption.

<Prior art> If it can be constructed based on one type of basic operator, it will be very effective both in systematically handling logic systems and in terms of engineering applications such as integration. Value theory systems are attracting attention. The input level determination circuit used in such a three-value theory system has two types of input level determination circuits:
In addition to the "level", there is also a need to judge the "oven" level. When configuring a ternary threshold gate circuit capable of determining three types of logic levels, conventionally, for example, I
It was constructed using a C operational amplifier.

<Problem to be solved by the invention> In the case of a circuit that judges multivalue levels such as 3 values,
Generally, separate input circuits are required for positive weights and negative weights, which complicates the circuit configuration. therefore,
In the case of a multi-value input level determination circuit, a large number of elements are required to form the circuit, and power consumption increases accordingly.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to simplify the circuit configuration of an input level determination circuit capable of determining multilevel signal levels, and to reduce its power consumption.

Means for Solving the Problems> The input level determination circuit of the present invention selectively operates according to an input terminal to which a signal for level determination is applied and the level of the input signal applied to the input terminal. For this purpose, a level judgment circuit is constructed by connecting multiple inverters in parallel, each with a different threshold value, and multiple resistors connected in series. and a resistor connection circuit that supplies an input signal to the connection point and supplies the potential of the connection point to each input terminal of the plurality of inverters, and according to the resistance division ratio of the resistance connection circuit, the When the input signal applied to the input terminal is at an open level, the magnitude of the input voltage supplied to the plurality of inverters can be set to a predetermined magnitude corresponding to the threshold value.

<Operation> A level determination circuit is constructed by connecting a plurality of inverters in parallel, making the threshold values of these inverters different, and selectively operating each inverter. Further, a voltage generating circuit is configured by connecting a plurality of resistors in series, and an input signal is supplied to a connection point of the resistors, and the input signal is applied to the level determination circuit via the connection point. Make it. Thereby, when the level of the input signal is at the open level, the logic threshold of the inverter is controlled by the voltage generated by the voltage generation circuit, and the level determination of the input signal can be performed on a multi-value basis.

<Embodiment> FIG. 1 is a configuration diagram of an input level determination circuit showing an embodiment of the present invention.

As is clear from FIG. 1, the input level determination circuit of this embodiment converts the input signal SIN applied to the input terminal IN into
It is supplied to the connection point 10 between the first resistor R1 and the second resistor R2, and is supplied to the first inverter 1 and the second inverter 2, respectively, via the connection point IO. and,
The output A of the first inverter 1 is supplied to the fourth inverter 4 and also to one input terminal of the AND circuit 6 . Further, the output B of the second inverter 2 is supplied to the other input terminal of the fifth inverter 5 and the AND circuit 6 via the third inverter 3. Then, the output of the fifth inverter 5 is supplied to the first output terminal Q1, the output of the AND circuit 6 is supplied to the second output terminal Q2, and the output of the fourth inverter 4 is supplied to the third output terminal Q3. .

Among these circuits, the first inverter 1 and the second inverter 2 are inverters having different threshold values,
As the third inverter 3 to the fifth inverter 5, inverters commonly used for inverting the polarity of signals are used.

Further, the first resistor R1 and the second resistor R2 are connected to the power supply voltage (2). It is arranged to divide the pressure.

Next, the operation of the input level determination circuit according to the embodiment configured as described above will be explained.

For example, first inverter 1 and second inverter 2
is a CMOS inverter, the input voltage when the input terminal IN is open is the first resistor R1 and the second resistor R1.
It is determined by the ratio of the resistance values of resistor R2. That is,
When the input voltage is VR, VR= (R1/R1+R2)'voo - (1)
becomes.

Note that the state where the input is open means, for example, that the input terminal I
For example, when a tristate output cell is connected to N and its output is in a high impedance state.

Here, the logical threshold value ■THI of the first inverter 1
(hereinafter referred to as the first logic threshold) is the input terminal ■8
The logic threshold VTH□ (hereinafter referred to as the second logic threshold) of the second inverter 2 is set lower than the input voltage VTH.

That is, VTH2<VR< VTHI・
... (2).

With this setting, the inputs are "'L", "H" and "
The output chart at the "open" level is shown in Table 1 below.

Table 1 The output states of the first inverter 1 and the second inverter 2 at this time are shown in the characteristic diagram of FIG.

In FIG. 2, characteristic A indicated by a broken line is the output of the first inverter 1, and characteristic B indicated by the dashed line is the output of the second inverter 2.
The output of each is shown.

By performing such an operation, the input becomes “L”,
When “open”, “H” level, output terminals Ql, Q
2. The output of Q3 becomes active high "AH" level.

Next, specific circuit configurations of the first and second inverters 1.2 will be explained according to the circuit configuration diagram of FIG. In Figure 3, R3-R6 are resistors, MNI, MN2 are NM
O3) Ranjisuf, MP1゜MP2 indicates PMO3, respectively, and the first inverter 1 has resistors R3,
R4 and transistor MN2. It is composed of MP2.

Further, the second inverter 2 is composed of resistors R5, R6 and transistors MNI, MPI.

In the input level determination circuit of FIG. 3 configured in this way, the input voltage 8
is determined by the division ratio of the resistance values of the resistors R3 to R6.

That is, the input voltages v and l are ■□= (R3+R4)
・VDD/(R3+ R4+ R5+ R6) =R1・VIID/ (R2+R3) ・・・ (
3). However, R1= R3+ R4R2= R
5+R6 Next, the threshold value of the first inverter 1 will be explained.

FIG. 4 is a circuit configuration diagram of the first inverter 1. As is clear from Fig. 4, this first inverter 1ON
The gate electrode G of the MO3 transistor MN2 is connected to the connection point between the third resistor R3 and the fourth resistor R4. Further, the source electrode S is connected to the ground GND, and the drain D is connected to the drain D of the PMO3) Ranjisuf MP2, and the output A is derived from these commonly connected drains D.

Further, the gate G of the transistor MP2 is connected to the input terminal IN and the other end of the resistor R4, and the source S is connected to the power supply ■.

, is connected to. Although not shown, the hack gate of the transistor MN2 is connected to the ground GND.
The hack gate of transistor MP2 is voltage tiVo
connected to n.

Assume that a voltage is gradually applied to the input terminal IN of the circuit of FIG. 4 constructed in this manner, and the voltage value of the output A becomes VDD/2, that is, the input voltage becomes a logic threshold. If the input voltage at this time is VIN, then VIN-VTHI (4) is obtained.

Here, the drain-source current of the transistor MN2 is assumed to be 14□, and the drain-source current of the transistor MP2 is assumed to be I dsp. Now, assuming that transistor MN2 and transistor MP2 have operating points in the saturation region, these currents 48. and Iasp, Iasm=K・β,・(αVIN VtN)”・・
・(5) I asp = %' βp ・(
αV, N vDD VTP) z...(6) Here, R0, β are the gain coefficients of the NMOS transistor and PMOS transistor, respectively, V T
N, V? P is the threshold voltage of each transistor. Further, α is the division ratio of resistors R3 and R4, and is α-R3/R3+R4 (7).

Now, I dsm = I asp, ■IN=V THI
Then, from equations (5) and (6) above, the threshold value is found: VT, l, = VD, +VTP+cxV1d]
Tfu1■÷(1+α,/1τ7T;) -vts +(v,.+VTF VTN)÷(1+
α n p) ...(8). However, V,, -V. , −■□, <0.

By the way, since 0<α=R3/R3+R4≦1,
By varying the values of the resistors R3 and R4, the logic threshold can be raised to a controlled level. Here, a certain amount means, for example, when the input is at the "H" level, a small amount (both transistor MN2
This means that it is possible to obtain a division ratio such that Von can be turned on, and if VTN=0.7V, then R3/R3+R4+Von>0.7V. Here, if VDD=5V, α-R3/R3+R4>0.14...(
9).

Similarly, the threshold values V and A2 of the second inverter 2 are calculated as follows:
V□)÷(r+(7cho7〕)...GO). Here, γ-R6/R5+R6.

00) In 2, ■. o VTN>O1Va, <0
Therefore, the eclipse is more negative than VDD.

Since 0<r=R6/R5+R6≦1, in this case as well, it is possible to control the logic threshold value by dividing the resistors and lower it to the extent that it is possible.

In this case, as in the case of the first inverter 1, when the input is at the "L" level, at least the resistance division ratio is such that the transistor MPI can be turned on. That's what it means.

As is clear from the above explanation, according to the input level determination circuit of this embodiment, a three-value input cell is realized by changing the gate voltage of the MOS transistor by resistor division and controlling the threshold value of the CMOS inverter. You can. The conditions are as shown in equation (2), VTH□<v, l<VT, 11. Here, VT)+2. V, l, and VT□ are as shown in formula 00, formula (3), and formula (8) 2 above, and a=R3・VDD/ (R3+R4) >VrNT=
The constants may be selected so as to satisfy the formula R6'VDD/(R5+R6)>l VrrI.

When we actually substitute the numerical values, we get Vnn-5V, ■7N=lVarl-+〇, 7V, β. = β, = 500 μA/V2, R3 to R6 = 20 and Ω, then α = r = 20/20 + 20 10, 5 VrHz = (0,5 5 0.7 + 0.7 f)
:(0,5+7)-1,7V ■A H1=(50,7+0.5・0.7,/T)
÷(1+FD=3.I V VR= (20+20) ÷(20+2020±20
)-2.5V. Therefore, VTMZ =1.7 V<2.5 V<V7)++ =
3. I V2.5 V>VT) I=0.7 V, 2.5 V>(VTP=0.7. V).

Next, regarding the current consumption when the input is open, the formula for the drain current Ids of the first inverter 1 and the drain current dsp of the second inverter 2 described above, that is, Ids++=Z·β.・(αVIN VTN)2・
...(5) Idsp-%・βp・(TV+s V
an Vtr)2...(6) As is clear from the equation, it can be reduced by the amount by which α and γ are multiplied. Therefore, since the voltage applied to the gate is reduced, power consumption when the gate is open can be reduced.

<Effects of the Invention> As described above, the present invention connects a plurality of inverters with different threshold values in parallel, and selectively operates these inverters according to the level of the input signal voltage. At the same time, a plurality of resistors are connected in series to form a voltage generation circuit, and the input signal applied to the input terminal is once supplied to the connection point of the resistors and then applied to the level determination circuit. As a result, since the logic threshold of the inverter is controlled by the voltage generated by the voltage generation circuit when the level of the input signal is at the open level, it is possible to judge the level of the input signal using multiple values. The circuit configuration of the input level determination circuit can be simplified and its power consumption can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an input level determination circuit showing an embodiment of the present invention. FIG. 2 is an operation characteristic diagram for explaining the operation of an inverter with different threshold values. FIG. 4 is a circuit diagram showing a specific circuit configuration of the level determination circuit. FIG. 4 is a circuit diagram showing the configuration of the first inverter. 1...first inverter. 2...Second inverter. 3...Third inverter. 6...AND circuit, 10...Connection point. IN...Input terminal, R1...First resistor. R2...second resistor, Ql...first output terminal. Q2...Second output terminal 1 Q3...Third output terminal + SIN...Input signal. Patent Applicant Sony Corporation Agent Patent Attorney Funahashi Kuninori 2nd 2nd Interference Cycle 1 Each 2nd Cause Figure 3

Claims (1)

[Claims] An input terminal to which a signal for level determination is applied, and thresholds for each are set to be different in order to operate selectively according to the level of the input signal applied to the input terminal. A level determination circuit is constructed by connecting a plurality of inverters in parallel and a plurality of resistors connected in series, and the input signal given to the input terminal is supplied to the connection point, and the above connection a resistor connection circuit that supplies a potential at a point to each input terminal of the plurality of inverters, and a resistor division ratio of the resistor connection circuit allows the input signal applied to the input terminal to be at an open level. An input level determination circuit characterized in that the magnitude of the input voltage supplied to each inverter can be set to a predetermined magnitude corresponding to the threshold value.