JPS62291158A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPS62291158A JPS62291158A JP61135167A JP13516786A JPS62291158A JP S62291158 A JPS62291158 A JP S62291158A JP 61135167 A JP61135167 A JP 61135167A JP 13516786 A JP13516786 A JP 13516786A JP S62291158 A JPS62291158 A JP S62291158A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- base material
- package body
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 19
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims abstract description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 4
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 30
- 230000017525 heat dissipation Effects 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract 6
- 230000000052 comparative effect Effects 0.000 description 6
- 230000005855 radiation Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 ３、発明の詳細な説明 ［発明の目的］ （産業上の利用分野） 本発明は、ＩＣパッケージの改良に関する。[Detailed description of the invention] 3. Detailed description of the invention [Purpose of the invention] (Industrial application field) The present invention relates to improvements in IC packages.
（従来の技術）
半導体チップの高出力化、＾集積化に伴い、半導体チッ
プ当りの発熱量は近年大巾に増大している。かかる集積
度の高い半導体チップを実装したパッケージとしては、
ビングリッド型パッケージ（ＰＧＡ）があり、従来より
第２図に示すように比較的熱伝導性が良好なアルミナ系
セラミックス製ＰＧＡが用いられている。即ち、図中の
１は図示しない多層の配線“が形成され、かつ階段状の
凹部２を有するアルミナ系セラミックスのパッケージ本
体である。このパッケージ本体１の凹部２内には、半導
体チップ３がマウントされている。(Prior Art) With the increase in output power and integration of semiconductor chips, the amount of heat generated per semiconductor chip has increased significantly in recent years. As a package mounted with such a highly integrated semiconductor chip,
There is a bin grid type package (PGA), and as shown in FIG. 2, a PGA made of alumina-based ceramics, which has relatively good thermal conductivity, has traditionally been used. That is, 1 in the figure is an alumina ceramic package body on which multilayer wiring (not shown) is formed and has a step-like recess 2.In the recess 2 of the package body 1, a semiconductor chip 3 is mounted. has been done.
この半導体チップ３は、ワイヤ４を介して前記パッケー
ジ本体１の図示しない配線と接続されている。また、前
記凹部２が開孔されたパッケージ本体１の面には前記半
導体チップ３を気密に封止するためのキャップ５が固定
されている。このキャップ５の固定面と反対側のパッケ
ージ本体１の面には、前記半導体チップ３に対応するよ
うに金属製の放熱フィン６が高熱伝導性の樹脂又は半田
層７を介して接合されている。なお、図中の８は前記パ
ッケージ本体１に取着され、該本体１の図示しない配線
とスルホールを介して接続された端子（ビン）である。This semiconductor chip 3 is connected to wiring (not shown) of the package body 1 via wires 4. Further, a cap 5 for hermetically sealing the semiconductor chip 3 is fixed to the surface of the package body 1 in which the recess 2 is formed. A metal radiation fin 6 is bonded to the surface of the package body 1 opposite to the fixed surface of the cap 5 via a highly thermally conductive resin or solder layer 7 so as to correspond to the semiconductor chip 3. . Note that 8 in the figure is a terminal (bin) attached to the package main body 1 and connected to wiring (not shown) of the main body 1 via a through hole.
しかしながら、上述した第２図図示のパッケージではパ
ッケージ本体１を構成するアルミナ系セラミックスの熱
伝導率が１７〜２０Ｗ／ｍ・Ｋ程度であるため、より一
層の高熱伝導性が要求される高出力、高集積度の半導体
チップに充分に対応できないという問題があった。However, in the above-mentioned package shown in FIG. 2, the thermal conductivity of the alumina ceramics constituting the package body 1 is about 17 to 20 W/m·K, so high output power, which requires even higher thermal conductivity, There was a problem in that it could not adequately accommodate highly integrated semiconductor chips.
このようなことから、パッケージ本体を高熱伝導性の窒
化アルミニウム（ＡβＮ）、炭化ケイ素（ＳｉＣ）やベ
リリア（８８０）により構成することが試みられている
が、現状ではいずれもコスト及び成形性の点から単独で
は使用せず、第３図に示すようにアルミナ系セラミック
スと複合化して用いられている。即ち、図中の１′は図
示しない多層の配線が形成され、かつ階段状の開孔部９
を有するアルミナ系セラミックスのパッケージ本体であ
る。このパッケージ本体１′の開孔部９には、断面が凸
状をなす高熱伝導性セラミックス基材１０が嵌合され、
かつこれらパッケージ本体１′と基材１０とは開孔部９
周辺の本体１′面に配置したガラス系接着層１１を介し
て接合されている。この高熱伝導性セラミック基材１０
の外側の面には、放熱フィン６が半田層７を介して接合
されている。また、前記基材１０の開孔部９側の面には
半導体チップ３がマウントされ、かつ該半導体チップ３
は、ワイヤ４を介して前記パッケージ本体１−の図示し
ない配線と接続されている。For this reason, attempts have been made to construct the package body using highly thermally conductive materials such as aluminum nitride (AβN), silicon carbide (SiC), and beryllia (880). Therefore, it is not used alone, but is used in a composite with alumina ceramics, as shown in Figure 3. That is, 1' in the figure is a stepped opening 9 where multilayer wiring (not shown) is formed.
The package body is made of alumina ceramics. A highly thermally conductive ceramic base material 10 having a convex cross section is fitted into the opening 9 of the package body 1'.
In addition, the package body 1' and the base material 10 have an opening 9.
They are bonded via a glass adhesive layer 11 disposed on the peripheral surface of the main body 1'. This highly thermally conductive ceramic base material 10
A heat dissipating fin 6 is bonded to the outer surface of the radiator 2 with a solder layer 7 interposed therebetween. Further, a semiconductor chip 3 is mounted on the surface of the base material 10 on the side of the opening 9, and the semiconductor chip 3
is connected to wiring (not shown) of the package body 1- via a wire 4.
更に、前記基材１０の嵌合部と反対側のパッケージ本体
１−の面には前記半導体チップ３を気密に封止するため
のキャップ５が固定されている。なお、図中の８は前記
パッケージ本体１′に取着され、該本体１′の図示しな
い配線とスルホールを介して接続された端子（ビン）で
ある。Furthermore, a cap 5 for hermetically sealing the semiconductor chip 3 is fixed to the surface of the package body 1- on the side opposite to the fitting portion of the base material 10. Note that 8 in the figure is a terminal (bin) attached to the package main body 1' and connected to wiring (not shown) of the main body 1' via a through hole.
しかしながら、上述した第３図図示のＰＧＡでは難加工
性の高熱伝導性セラミックス基材１ｏを断面が凸状に加
工する必要があるため、加工コストが高くなるばかりか
、加工時に割れ等を発生する恐れがある。また、該基材
１０を断面凸状にするために必然的に厚くなり、マウン
トされた半導体チップ３から放熱フィン６への熱伝達効
率が低下する問題があった。However, in the above-mentioned PGA shown in FIG. 3, it is necessary to process the highly thermally conductive ceramic base material 1o, which is difficult to process, into a convex cross section, which not only increases the processing cost but also causes cracks etc. during processing. There is a fear. Furthermore, since the base material 10 has a convex cross-section, it inevitably becomes thicker, resulting in a problem that the efficiency of heat transfer from the mounted semiconductor chip 3 to the heat dissipation fins 6 decreases.
（発明が解決しようとする問題点）
本発明は、上記従来の問題点を解決するためになされた
もので、高熱伝導性セラミックス基材への加工が不要乃
至最低限で済み、かつ半導体チップから放熱フィンへの
熱伝達効率を向上したＩＣパッケージを提供しようとす
るものである。(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned conventional problems. The present invention aims to provide an IC package with improved heat transfer efficiency to radiation fins.
［発明の構成］
（問題点を解決するための手段）
本発明は、配線及び端子を有するアルミナ系セラミック
スからなるパッケージ本体と、この本体に接合され、半
導体チップがマウントされた高熱伝導性セラミックス基
材との複合セラミックス構造を持つＩＣパッケージにお
いて、前記高熱伝導性セラミックス基材が平板状をなし
、かっ該基材を前記アルミナ系セラミックスのパッケー
ジ本体に埋込むと共に該パッケージ本体に開孔された穴
部を通して前記半導体チップのマウント面と反対側の前
記基材の面に放熱フィンを設けたことを特徴とするＩＣ
パッケージである。[Structure of the Invention] (Means for Solving the Problems) The present invention comprises a package body made of alumina ceramics having wiring and terminals, and a highly thermally conductive ceramic base bonded to the body and having a semiconductor chip mounted thereon. In an IC package having a composite ceramic structure with a ceramic material, the highly thermally conductive ceramic base material has a flat plate shape, the base material is embedded in the alumina ceramic package body, and a hole is formed in the package body. An IC characterized in that a heat dissipation fin is provided on a surface of the base material opposite to a mounting surface of the semiconductor chip through the portion.
It's a package.
（作用）
本発明のＩＣパッケージは、アルミナ系セラミックスの
パッケージ本体に組込まれ、半導体チップがマウントさ
れる高熱伝導性セラミック基材を単純な平板状とするこ
とによって、該基材の製作のための加工を不要乃至最低
限に留どめることが可能となり、コストの低減化と製作
時の割れ発生を防止できる。従って、高熱伝導性セラミ
ックスとして従来から汎用された酸化ベリリウムを９５
重量％以上含有するベリリア（熱伝導率：２００Ｗ／ｍ
・Ｋ以上）や高熱伝導性を有するが複雑な形状に加工す
ることが困難なホットプレス成形された炭化ケイ素を９
５重量％以上含有する炭化ケイ素（熱伝導率： ２００
Ｗ／ｍ−ｋ以上）或いは窒化アルミニウムを９０重量％
以上含有するＡｆｌＮ（熱伝導率： ５０Ｗ／ｍ−ｋ以
上）等が使用可能となる。(Function) The IC package of the present invention is incorporated into an alumina-based ceramic package body, and the highly thermally conductive ceramic base material on which the semiconductor chip is mounted is made into a simple flat plate. Processing can be kept to a minimum or unnecessary, reducing costs and preventing cracks from occurring during manufacturing. Therefore, 95% of beryllium oxide, which has been widely used as a highly thermally conductive ceramic,
Berylium containing at least % by weight (thermal conductivity: 200W/m
・Hot press molded silicon carbide that has high thermal conductivity but is difficult to process into complex shapes.
Silicon carbide containing 5% by weight or more (thermal conductivity: 200
W/m-k or more) or 90% by weight of aluminum nitride
AflN (thermal conductivity: 50 W/m-k or more) containing the above can be used.
また、高熱伝導性セラミックス基材を平板状にすること
によって、該基材を薄くすることが可能となり、基材面
にマウントされた半導体チップから該基材のマウント面
と反対側の面に接合された放熱フィンへの熱伝達効率を
向上できる。なお、アルミナ系セラミックスのパッケー
ジ本体はアルミナ系セラミックスのグリーンシートを積
層成形することによって製作できるため、高熱伝導性セ
ラミックス基材を平板状とすることにより該パッケージ
本体の形状が多少複雑になっても製作上の困難さは伴わ
ない。In addition, by making the highly thermally conductive ceramic base material flat, it is possible to make the base material thinner, and the semiconductor chip mounted on the base material surface is bonded to the surface opposite to the mounting surface of the base material. The efficiency of heat transfer to the heat dissipation fins can be improved. Note that the alumina-based ceramic package body can be manufactured by laminating and molding alumina-based ceramic green sheets, so even if the shape of the package body becomes somewhat complicated by making the highly thermally conductive ceramic base material into a flat plate, There are no manufacturing difficulties involved.
（発明の実施例）
以下、本発明を第１図に示すＰＧＡ型のＩＣパッケージ
を例にして説明する。(Embodiments of the Invention) The present invention will be described below using a PGA type IC package shown in FIG. 1 as an example.
実施例
図中の２１は、図示しない多層の配線が形成され、かつ
三つの階段状とした開孔部２２を有するアルミナ系セラ
ミックスのパッケージ本体である。Reference numeral 21 in the drawings indicates an alumina-based ceramic package body on which multilayer wiring (not shown) is formed and has three step-shaped openings 22.
このパッケージ本体２１は、例えば前記階段状の開孔部
に対応して大、中、小の内径穴を有する４枚（２枚は中
間の内径穴を有する）のアルミナグリーンシートを所定
のシートに配線となる導体ベーストを印刷した状態で積
層し、焼結することにより製作した。前記パッケージ本
体２１の開孔部２２内の２段目の平面には、例えばＡｆ
ｉＮ焼結体からなる基材２３が低膨張ガラスフリットを
主材とするガラス系接着８２４を介して接合されている
。この平板状の基材２３は、酸素量的１％のＡｆｉＮ粉
末に３重層％のＹ２０３を添加し、成形した後、窒素雰
囲気中で１８００℃、２時間常圧焼結することにより得
た熱伝導率が
１７０Ｗ／ｍ・ＫのＡｆｆｉＮ焼結体を厚さ０．６ａｍ
に加工したものである。This package body 21 is made of, for example, four alumina green sheets having large, medium, and small inner diameter holes corresponding to the stepped openings (two sheets have an intermediate inner diameter hole), and are arranged in a predetermined sheet. It was manufactured by laminating printed conductor bases, which will serve as wiring, and sintering them. For example, Af
A base material 23 made of an iN sintered body is bonded via a glass adhesive 824 mainly made of low expansion glass frit. This plate-shaped base material 23 is made by adding 3% Y203 to AfiN powder containing 1% oxygen, molding it, and then sintering it under normal pressure at 1800°C for 2 hours in a nitrogen atmosphere. AffiN sintered body with conductivity of 170 W/m・K with thickness of 0.6 am
It is processed into.
前記ＡｆｉＮ焼結体の基材２３の前記パッケージ本体２
１との接合側の面には、前記開孔部２２を通して挿入さ
れ、先端断面を凸状とした放熱フィン２５が半田層２６
を介して接合されている。また、前記放熱フィン２５の
接合面と反対側の前記基材２３の面には半導体チップ２
７がマウントされ、かつ該半導体チップ２７は、ワイヤ
２８を介して前記パッケージ本体２１の図示しない配線
と接続されている。更に、前記放熱フィン２５挿入部と
反対側のパッケージ本体２１の面には前記半導体チップ
２７を気密に封止するためのキャップ２９が固定されて
いる。なお、図中の３０は前記パッケージ本体２１に取
着され、該本体２１の図示しない配線とスルホールを介
して接続された端子（ビン）である。The package body 2 of the base material 23 of the AfiN sintered body
1, a heat dissipating fin 25 having a convex tip cross section is inserted through the opening 22 and is connected to the solder layer 26.
are connected via. Further, a semiconductor chip 2 is provided on the surface of the base material 23 opposite to the bonding surface of the heat dissipation fin 25.
7 is mounted, and the semiconductor chip 27 is connected to wiring (not shown) of the package body 21 via wires 28. Furthermore, a cap 29 for airtightly sealing the semiconductor chip 27 is fixed to the surface of the package body 21 opposite to the insertion portion of the radiation fin 25. Note that 30 in the figure is a terminal (bin) attached to the package main body 21 and connected to wiring (not shown) of the main body 21 via a through hole.
比較例１
前述した第２図図示のＩＣパッケージにおいて、パッケ
ージ本体１を熱伝導率が１８Ｗ／ｍ・Ｋのアルミナ系セ
ラミックスにより形成した。Comparative Example 1 In the IC package shown in FIG. 2 described above, the package body 1 was formed of alumina ceramics having a thermal conductivity of 18 W/m·K.
比較例２
前述した第３図図示のＩＣパッケージにおいて、高熱伝
導性セラミックス基材１０として実施例と同様な熱伝導
率（１７０Ｗ／ｍ−ｋ）のＡｆｆＮ焼結体を断面が凸状
となるように研磨加工した最大厚さ部分（チップのマウ
ンド部）が１．５ｍのものを用いた。Comparative Example 2 In the above-mentioned IC package shown in FIG. 3, an AffN sintered body having the same thermal conductivity (170 W/m-k) as in the example was used as the highly thermally conductive ceramic base material 10 so that the cross section was convex. A chip with a maximum thickness (mound part of the chip) of 1.5 m was used.
しかして、本実施例及び比較例１．２のＩＣパッケージ
の熱抵抗を測定した。その結果、半導体チップをアルミ
ナ系セラミックスのパッケージ本体にマウントした比較
例１のＩＣパッケージでは熱抵抗が２．８０℃／Ｗ、半
導体チップを凸状をなすＡｆｉＮ焼結体の基材にマウン
トした比較例２のＩＣパッケージでは熱抵抗が０．４０
℃／Ｗであった。これに対し、本実施例のＩＣパッケー
ジでは熱抵抗が０．２５℃７・／Ｗと比較例２に比べて
＝１０−
良好な結果となり、しかもＡｆｆｉＮ焼結体を加工せず
そのまま基材として使用できることから比較例２のパッ
ケージに比べてコストを著しく低減できた。The thermal resistance of the IC packages of this example and comparative example 1.2 was then measured. As a result, the IC package of Comparative Example 1, in which the semiconductor chip was mounted on an alumina-based ceramic package body, had a thermal resistance of 2.80°C/W, compared to the IC package in which the semiconductor chip was mounted on a convex AfiN sintered base material. The IC package of Example 2 has a thermal resistance of 0.40.
℃/W. On the other hand, the IC package of this example had a thermal resistance of 0.25°C7·/W, which was =10- better than Comparative Example 2, and the AffiN sintered body could be used as a base material without being processed. Since the package can be used, the cost can be significantly reduced compared to the package of Comparative Example 2.
［発明の効果］
以上詳述した如く、本発明によれば高熱伝導性セラミッ
クス基材への加工が不要乃至最低限で済み、かつ半導体
チップから放熱フィンへの熱伝達効率を向上した低コス
トで高性能のＩＣパッケージを提供できる。[Effects of the Invention] As detailed above, according to the present invention, processing on a highly thermally conductive ceramic base material is unnecessary or minimal, and the heat transfer efficiency from the semiconductor chip to the heat dissipation fins is improved at a low cost. We can provide high-performance IC packages.
第１図は本発明の一実施例を示すＰＧＡ型のＩＣパッケ
ージの断面図、第２図は従来のＰＧＡ型のＩＣパッケー
ジを示す断面図、第３図は半導体チップのマウント部に
高熱伝導性セラミックス基材を用いた従来の改良された
ＰＧＡ型のＩＣパッケージを示す断面図である。
２１・・・アルミナ系セラミックスのパッケージ本体、
２３・・・平板状をなす高熱伝導性セラミックス基材、
２５・・・放熱フィン、２７・・・半導体チップ、２９
・・・キャップ。Figure 1 is a sectional view of a PGA type IC package showing an embodiment of the present invention, Figure 2 is a sectional view of a conventional PGA type IC package, and Figure 3 is a sectional view of a PGA type IC package showing an embodiment of the present invention. 1 is a cross-sectional view showing a conventional improved PGA type IC package using a ceramic base material. 21... Alumina ceramics package body,
23... Highly thermally conductive ceramic base material having a flat plate shape,
25... Heat radiation fin, 27... Semiconductor chip, 29
···cap.
Claims (4)
からなるパッケージ本体と、この本体に接合され、半導
体チップがマウントされた高熱伝導性セラミックス基材
との複合セラミックス構造を持つＩＣパッケージにおい
て、前記高熱伝導性セラミックス基材が平板状をなし、
かつ該基材を前記アルミナ系セラミックスのパッケージ
本体に埋込むと共に該パッケージ本体に開孔された穴部
を通して前記半導体チップのマウント面と反対側の前記
基材の面に放熱フィンを設けたことを特徴とするＩＣパ
ッケージ。(1) In an IC package having a composite ceramic structure consisting of a package body made of alumina ceramics having wiring and terminals, and a highly thermally conductive ceramic base material bonded to this body and on which a semiconductor chip is mounted, The ceramic base material has a flat plate shape,
and that the base material is embedded in the alumina-based ceramic package body, and a heat dissipation fin is provided on the surface of the base material opposite to the mounting surface of the semiconductor chip through a hole formed in the package body. Characteristic IC package.
を９０重量％以上含有する熱伝導率が ５０Ｗ／ｍ・Ｋ以上のものであることを特徴とする特許
請求の範囲第１項記載のＩＣパッケージ。(2) The IC package according to claim 1, wherein the highly thermally conductive ceramic contains 90% by weight or more of aluminum nitride and has a thermal conductivity of 50 W/m·K or more.
重量％以上含有する熱伝導率が ２００Ｗ／ｍ・Ｋ以上のものであることを特徴とする特
許請求の範囲第１項記載のＩＣパッケージ。(3) High thermal conductivity ceramics contain 95% silicon carbide.
The IC package according to claim 1, wherein the IC package contains at least % by weight and has a thermal conductivity of 200 W/m·K or more.
９５重量％以上含有する熱伝導率が ２００Ｗ／ｍ・Ｋ以上のものであることを特徴とする特
許請求の範囲第１項記載のＩＣパッケージ。(4) The IC package according to claim 1, wherein the highly thermally conductive ceramic contains 95% by weight or more of beryllium oxide and has a thermal conductivity of 200 W/m·K or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135167A JPS62291158A (en) | 1986-06-11 | 1986-06-11 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135167A JPS62291158A (en) | 1986-06-11 | 1986-06-11 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62291158A true JPS62291158A (en) | 1987-12-17 |
Family
ID=15145397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61135167A Pending JPS62291158A (en) | 1986-06-11 | 1986-06-11 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62291158A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5057903A (en) * | 1989-07-17 | 1991-10-15 | Microelectronics And Computer Technology Corporation | Thermal heat sink encapsulated integrated circuit |
| US5057376A (en) * | 1988-11-15 | 1991-10-15 | Asahi Glass Company Ltd. | Hybrid package, glass ceramic substrate for the hybrid package, and composition for the glass ceramic substrate |
| WO1996013056A3 (en) * | 1994-10-14 | 1996-07-11 | Nat Semiconductor Corp | Hermetically sealed hybrid ceramic integrated circuit package |
| US5885853A (en) * | 1990-06-22 | 1999-03-23 | Digital Equipment Corporation | Hollow chip package and method of manufacture |
| CN109479384A (en) * | 2016-09-27 | 2019-03-15 | 深圳市大疆创新科技有限公司 | Radiator structure, electronic device, holder and aircraft |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5896757A (en) * | 1981-12-04 | 1983-06-08 | Hitachi Ltd | Semiconductor device |
| JPS6066843A (en) * | 1983-09-22 | 1985-04-17 | Hitachi Ltd | Integrated circuit package |
-
1986
- 1986-06-11 JP JP61135167A patent/JPS62291158A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5896757A (en) * | 1981-12-04 | 1983-06-08 | Hitachi Ltd | Semiconductor device |
| JPS6066843A (en) * | 1983-09-22 | 1985-04-17 | Hitachi Ltd | Integrated circuit package |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5057376A (en) * | 1988-11-15 | 1991-10-15 | Asahi Glass Company Ltd. | Hybrid package, glass ceramic substrate for the hybrid package, and composition for the glass ceramic substrate |
| US5057903A (en) * | 1989-07-17 | 1991-10-15 | Microelectronics And Computer Technology Corporation | Thermal heat sink encapsulated integrated circuit |
| US5885853A (en) * | 1990-06-22 | 1999-03-23 | Digital Equipment Corporation | Hollow chip package and method of manufacture |
| WO1996013056A3 (en) * | 1994-10-14 | 1996-07-11 | Nat Semiconductor Corp | Hermetically sealed hybrid ceramic integrated circuit package |
| CN109479384A (en) * | 2016-09-27 | 2019-03-15 | 深圳市大疆创新科技有限公司 | Radiator structure, electronic device, holder and aircraft |
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