JPS62290164A - Formation of semiconductor element - Google Patents
Formation of semiconductor elementInfo
- Publication number
- JPS62290164A JPS62290164A JP13169386A JP13169386A JPS62290164A JP S62290164 A JPS62290164 A JP S62290164A JP 13169386 A JP13169386 A JP 13169386A JP 13169386 A JP13169386 A JP 13169386A JP S62290164 A JPS62290164 A JP S62290164A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistance
- polysilicon
- layer polysilicon
- resistance element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 65
- 229920005591 polysilicon Polymers 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 16
- 238000009413 insulation Methods 0.000 abstract 2
- 239000002184 metal Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
（産業上の利用分野）
この発明は半導体素子の形成方法に関し、詳しくは、第
１層ポリシリコン−第２層ポリシリコン−第１層ポリシ
リコンの構造を有する高抵抗素子を半導体基板上に形成
する方法に関する。Detailed Description of the Invention 3. Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for forming a semiconductor element, and more specifically, a method for forming a semiconductor device by forming a first layer polysilicon layer, a second layer polysilicon layer, a first layer polysilicon layer, and a first layer polysilicon layer. The present invention relates to a method of forming a high resistance element having a silicon structure on a semiconductor substrate.
（従来の技術）
上記高抵抗素子を半導体基板上に形成する従来の方法を
第３図ｔ−参照して説明する。(Prior Art) A conventional method for forming the above-mentioned high resistance element on a semiconductor substrate will be described with reference to FIG.
まず、シリコン基板１上に絶縁膜２を既知のＳｌと０．
の酸化反応１友はＣＶＤ法によって１００〜１５０λ厚
く形成する。その後、その上に、ＣＶＤ＠を用いて５Ｉ
Ｈ４の熱分解反応により第１層ポリシリコン３を３００
０〜４０００＾厚に形成し、その全面にリンを熱拡散に
より５〜６ Ｅ ２０ ｔｏｎｓ／、−拡散させること
により、第１層ポリシリコン３のシート抵抗値ｆ、２０
〜３０Ｑ／Ｄに下げる。その後、公知のホトリソ・エツ
チング技術を用いて第１層ポリシリコン３と絶縁膜２を
図に示すように一対の・千ターンに形成する。First, an insulating film 2 is coated on a silicon substrate 1 with known Sl and 0.0.
The oxidation reaction 1 layer is formed to a thickness of 100 to 150λ by the CVD method. Then, apply 5I on top of it using CVD@.
The first layer polysilicon 3 is heated to 300% by thermal decomposition reaction of H4.
The sheet resistance value f, 20 of the first layer polysilicon 3 is reduced by forming the polysilicon layer 3 to a thickness of 0 to 4000^ and diffusing phosphorus over the entire surface by thermal diffusion at a rate of 5 to 6 E20 tons/-.
Lower to ~30Q/D. Thereafter, the first layer polysilicon 3 and the insulating film 2 are formed into a pair of 1,000 turns using known photolithography and etching techniques, as shown in the figure.
その後、８１と０２の酸化反応またはＣＶＤ法により全
面に絶縁膜４を１０００〜２０００＾厚に形成する。続
いて、第１層ポリシリコン３と後述する第２層ポリシリ
コンロを電気的に接続するためのコンタクトホール５を
公知のホトリソ・エツチング技術を用いて絶縁膜４に各
第１層ポリシリコン３上にて形成する。Thereafter, the insulating film 4 is formed to a thickness of 1000 to 2000 mm over the entire surface by the oxidation reaction of 81 and 02 or the CVD method. Subsequently, a contact hole 5 for electrically connecting the first layer polysilicon 3 and a second layer polysilicon 3 (described later) is formed in the insulating film 4 using a known photolithography/etching technique. Form on top.
その後、高抵抗体となる第２層ポリシリコンロをＣＶＤ
法によＩ）５００〜ａｏｏｏＡ全面に形成する。After that, the second layer of polysilicon, which will become a high-resistance material, is deposited by CVD.
Formed on the entire surface of I) 500 to aoooA by method.
そして、この第２層ポリシリコンロにイオンイングラン
チージョン法により３１ｐ＋を０〜９ Ｅ １８１０”
／ａｄ打込むことにより所望の抵抗値を得、しかる後、
公知のホトリン・エツチング技術を用いて第２層ポリシ
リコンロを図に示すように、一対の第１層ポリシリコン
３間に接続されるような所望のパターンに形成する。な
お、この時、第２層ポリシリコンロはその所望の抵抗値
によって膜厚・長さ・幅が決定され、膜厚を薄く、長さ
を長く、幅を短くすると、より高抵抗となる。Then, 31p+ was applied to this second layer of polysilicon by the ion-injection method.
/ad to obtain the desired resistance value, and then,
Using a known photolin etching technique, the second layer polysilicon layer is formed into a desired pattern so as to be connected between a pair of first layer polysilicon layers 3, as shown in the figure. At this time, the film thickness, length, and width of the second polysilicon layer are determined by its desired resistance value, and the smaller the film thickness, the longer the length, and the shorter the width, the higher the resistance.
続いて、ＣＶＤ法を用いて全面に？、縁膜７ｔ−５００
０〜８０００λ厚に形成し、その後、後述する金属配線
９ａ、９ｂと電気的接続を得るためのコンタクトホール
８を各第１層ポリシリコン３上にて絶縁膜７．４に形成
する。最後に、コンタクトホール８を通して各第１層ポ
リシリコン３に接続される金属配線９ａ、９ｂを形成す
る。Next, use the CVD method to cover the entire surface. , membrane 7t-500
After that, contact holes 8 are formed in the insulating film 7.4 on each first layer polysilicon 3 for electrical connection with metal wirings 9a and 9b, which will be described later. Finally, metal interconnections 9a and 9b connected to each first layer polysilicon 3 through contact holes 8 are formed.
以上のような方法によれば、一対の第１層ポリシリコン
３およびその間の第２層ポリシリコンロからなる高抵抗
素子がシリコン基板１上に形成され、高抵抗素子の両端
は金属配線９ａ、９ｂＫ接続される。そして、金属配線
９ａを接地し、金属配線９ｂから電圧を印加すると、金
属配線９ｂ→コンタクトホ一ル８→第１層ポリシリコン
３→コンタクトホール５→第２層ポリシリコンロ→コン
タクトホール５→第１／ｉｌポリシリコン３→コンタク
トホール８→金属配線９ａ→ＧＮＤと電流が流れ、その
際の電流量は第２層ポリシリコンロによって決定される
。し九がって、この高抵抗素子をメモリーセルに用いた
際の消費電力は、この電流値によって決定され、消費電
力を低くするためには、第２層ポリシリコンロの抵抗値
を増加させる必要がある。According to the method described above, a high resistance element consisting of a pair of first layer polysilicon 3 and a second layer polysilicon between them is formed on silicon substrate 1, and both ends of the high resistance element are connected to metal wiring 9a, 9bK connected. Then, when the metal wiring 9a is grounded and a voltage is applied from the metal wiring 9b, the metal wiring 9b → contact hole 8 → first layer polysilicon 3 → contact hole 5 → second layer polysilicon → contact hole 5 → A current flows from the first polysilicon layer 3 to the contact hole 8 to the metal wiring 9a to GND, and the amount of current is determined by the second layer polysilicon layer. Therefore, the power consumption when this high resistance element is used in a memory cell is determined by this current value, and in order to lower the power consumption, the resistance value of the second layer polysilicon layer must be increased. There is a need.
（発明が解決しようとする問題点）
しかるに、第２層ポリシリコンロの寸法・膜厚には限界
があり、ノンドーグポリシリコンを用いても第２層ポリ
シリコンロの高抵抗化には限界がおる。し九がって、半
導体素子の集積度の増大による消費電力の増大を防ごう
として、高抵抗素子に一層の高抵抗値が求められるよう
になると、上記従来の方法ではその高抵抗値を実現でき
なくなるという問題点があった。また、上記従来の方法
では、第１層ポリシリコン３中のＰ＋がコンタクトホー
ル５ｔ−通して第２層ポリシリコンロ中に拡散し、第２
層ポリシリコンロの不純物濃度が増加することにより高
抵抗値を実現できないという欠点もあつ之。(Problem to be solved by the invention) However, there are limits to the dimensions and film thickness of the second layer polysilicon, and even if non-doped polysilicon is used, there is a limit to increasing the resistance of the second layer polysilicon. There is. As a result, in order to prevent the increase in power consumption due to the increase in the degree of integration of semiconductor devices, even higher resistance values are required for high-resistance elements. The problem was that it was not possible. Furthermore, in the conventional method described above, P+ in the first layer polysilicon 3 diffuses into the second layer polysilicon layer through the contact hole 5t-.
Another drawback is that a high resistance value cannot be achieved due to an increase in the impurity concentration of the polysilicon layer.
この発明は上記の点に鑑みなされ友もので、その目的は
、高抵抗素子のより高抵抗化を実現することができる半
導体素子の形成方法を提供することにある。The present invention was developed in view of the above points, and an object of the present invention is to provide a method for forming a semiconductor element that can realize a higher resistance of a high-resistance element.
（問題点を解決するための手段）
この発明では、半導体基板上に高抵抗素子の両溝として
の第１層ポリシリコンパターンを形成した後、全面に絶
縁膜を形成し、この絶縁膜に第１層ポリシリコンの各ノ
９ターン上にてコンタクトホールを形成した後、高抵抗
素子の高抵抗体となる第２層ポリシリコンを形成する際
に、コンタクトホールの第１層ポリシリコンの表面に薄
く酸化膜を形成するようにする。(Means for Solving Problems) In the present invention, after forming a first layer polysilicon pattern as both grooves of a high resistance element on a semiconductor substrate, an insulating film is formed on the entire surface, and a first layer polysilicon pattern is formed on the entire surface of the semiconductor substrate. After forming contact holes on each of the nine turns of the first-layer polysilicon, when forming the second-layer polysilicon that becomes the high-resistance element of the high-resistance element, the surface of the first-layer polysilicon in the contact hole is Form a thin oxide film.
（作用）
コンタクトホールの第１層ポリシリコン表面に形成され
几薄い酸化膜は高抵抗体として作用する。(Function) The thin oxide film formed on the surface of the first polysilicon layer of the contact hole acts as a high resistance element.
（，７ｔがって、この発明によれば、第２層ポリシリコ
ンからなる高抵抗体の両端に、酸化膜による尚抵抗体が
付加され友高抵抗素子が形成される。Therefore, according to the present invention, resistors made of oxide films are added to both ends of the high-resistance element made of the second layer polysilicon to form a high-resistance element.
（実施例） 以下この発明の一実施例を第１図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
第１図に示すこの発明の一実施例では、絶縁膜４にコン
タクトホール５を開孔するまで、従来と全く同一の工程
を進める。その同一工程については説明を省略し、同一
工程によって形成さ７−した各部についても、第１図中
に第３図と同一符号を付すことによシ同じく説明を省略
する。In one embodiment of the present invention shown in FIG. 1, the same steps as in the prior art are performed until a contact hole 5 is formed in an insulating film 4. Description of the same steps will be omitted, and each part formed by the same steps will be designated by the same reference numerals as in FIG. 3 in FIG.
その後、全面に第２層ポリシリコンロｔ−減圧ＣＶＤ法
を用いて５９０℃で５ＩＨ４の熱分解によって形成する
が、その際、ＳｉＨ，を炉内に流出させる前に％Ｏｔ
ｔ’ ５分間程度炉内に流出させる。すると、第２図の
酸化成長膜厚特性図で示される膜厚の酸化膜１０がコン
タクトホール５の第１層ポリシリコン３表面に形成され
る。その後、０．の流出を止め。Thereafter, a second layer of polysilicon is formed on the entire surface by thermal decomposition of 5IH4 at 590°C using a low-pressure CVD method.
t' Allow to flow into the furnace for about 5 minutes. Then, an oxide film 10 having a thickness shown in the oxide growth film thickness characteristic diagram of FIG. 2 is formed on the surface of the first layer polysilicon 3 in the contact hole 5. After that, 0. Stop the outflow.
ＳｉＨ，を流出させ、全面に第２層ポリシリコンロｔ−
形成する。SiH, is poured out and a second layer of polysilicon is deposited on the entire surface.
Form.
その後は再び従来と同様にして第２層ポリシリコン６の
パターニング、絶縁膜７の形成、コンタクトホール８の
形成、金属配線９ａ、９ｂの形成を行い、素子を完成さ
せる。After that, the second layer polysilicon 6 is patterned, the insulating film 7 is formed, the contact hole 8 is formed, and the metal wirings 9a and 9b are formed again in the same manner as in the prior art, thereby completing the device.
その完成した構成において、金属配５９ａを接地し、金
属配線９ｂより電圧を印加すると、電流は、金属配置１
９ｂ→コンタクトホ一ル８→第１層ポリシリコン３→コ
ンタクトホール５→酸化膜１０→第２層ポリシリコンロ
→酸化膜１０→コンタクトホール５→第１層ポリシリコ
ン３→コンタクトホール８→金属配線９ａ→ＧＮＤと流
れる。そして、ここにおいて酸化膜１０が薄い酸化膜で
膜厚が３０λであるとすると、ここを流れる電流は。In the completed configuration, when the metal wiring 59a is grounded and a voltage is applied from the metal wiring 9b, a current flows through the metal wiring 11.
9b → contact hole 8 → first layer polysilicon 3 → contact hole 5 → oxide film 10 → second layer polysilicon → oxide film 10 → contact hole 5 → first layer polysilicon 3 → contact hole 8 → metal The line flows from wiring 9a to GND. Assuming that the oxide film 10 is a thin oxide film with a film thickness of 30λ, the current flowing through it is as follows.
５Ｖｔ−印加すると約２Ｅ−１２Ａ程度であり、見かけ
上４００ＧΩの抵抗体が存在することになる。When 5Vt- is applied, it is about 2E-12A, and there is an apparent resistor of 400GΩ.
−万、第２層ポリシリコンロからなる抵抗体は、該ポリ
シリコンロにノンドーグポリシリコンを用い、膜厚を５
００〜１ｏｏｏ＾とし、寸法を長さＬ＝３〜ｌＱμｆｆ
！、幅Ｗｚ １〜１．２μｍとすると、抵抗値が１５０
０ＧΩ程度となる。そして、この第２層ポリシリコンロ
からなる抵抗体の両端に前記酸化膜１０からなる抵抗体
が直列に接続された形で上記一実施例によれば高抵抗素
子が形成される友め、その高抵抗素子の全抵抗値は１５
００ ＋ ４００ ＋ ４００−２３００ＧΩとなり、
５ｖ印加の際は約２Ｅ−１３Ａの電流値が流れる。- For the resistor made of the second layer of polysilicon, non-doped polysilicon is used for the polysilicon layer, and the film thickness is 5.
00 to 1ooo^, and the dimensions are length L = 3 to lQμff
! , the width Wz is 1 to 1.2 μm, the resistance value is 150
It becomes about 0GΩ. According to the above embodiment, a high resistance element is formed by connecting the resistor made of the oxide film 10 in series to both ends of the resistor made of the second layer polysilicon. The total resistance value of the high resistance element is 15
00 + 400 + 400-2300GΩ,
When 5V is applied, a current value of approximately 2E-13A flows.
ま之、酸化膜１０の膜厚ｆｔ５０λとすると、５ｖ印加
時の酸化膜１０の抵抗値は７００ＧΩとなり、高抵抗素
子の全抵抗値は約３０００ ＧΩとな９，５ｖ印加時の
電流値は約１．５Ｅ−１３Ａとなる。However, if the thickness of the oxide film 10 is ft50λ, the resistance value of the oxide film 10 when 5V is applied is 700GΩ, the total resistance value of the high resistance element is about 3000GΩ, and the current value when 9.5V is applied is about It becomes 1.5E-13A.
そして、この高抵抗素子を１つのメモリセルに１個用い
てメモリデバイスを形成すると、従来の場合は消費電力
が１．７Ｅ−１１Ｗであったのに対して消費電力は１．
１Ｅ−１１Ｗ（ただし、酸化膜１０の膜厚は３０＾）と
なり、酸化膜１０の膜厚を５０大とすると、消費電力は
更に０．８Ｅ−１１Ｗとなり、消費電力が低下する。When a memory device is formed using one high-resistance element in one memory cell, the power consumption is 1.7E-11W compared to the conventional case of 1.7E-11W.
If the thickness of the oxide film 10 is set to 1E-11W (the thickness of the oxide film 10 is 30^), and the thickness of the oxide film 10 is set to 50, the power consumption becomes 0.8E-11W, which further reduces the power consumption.
（発明の効果）
以上詳細に説明しｔように、この発明の方法によれば、
第２層ポリシリコンからなる高抵抗体の両端に、酸化膜
からなる高抵抗体を付加して高抵抗素子を形成するよう
Ｋ（、ｆＣので、膜厚・寸法的に限界のあった高抵抗素
子の高抵抗値をより高抵抗にすることが町馳となり、今
後の崗集積度化するデバイスへの適用が可能となる。ま
た、前記酸化膜は、コンタクト部において第１層ポリシ
リコンから第２層ポリシリコンへの不純物拡散を防止す
るので、その不純物拡散による抵抗値の低下が防止され
、かつ抵抗値の制御性が向上する。(Effects of the Invention) As explained in detail above, according to the method of the present invention,
A high-resistance element made of an oxide film is added to both ends of a high-resistance element made of a second layer polysilicon to form a high-resistance element. It is becoming popular to increase the resistance value of the element to a higher resistance value, and it will be possible to apply it to devices with higher integration density in the future.In addition, the oxide film is formed in the contact area from the first polysilicon layer to the second layer polysilicon layer. Since impurity diffusion into the two-layer polysilicon is prevented, a decrease in resistance value due to the impurity diffusion is prevented, and controllability of resistance value is improved.
第１図はこの発明の半導体素子の形成方法の一実施例を
説明するための断面図、第２図は酸化時間対酸化膜厚の
関係を示す酸化成長膜厚特性図、第３図は従来の高抵抗
素子の形成方法を説明する念めの断面図である。
１・・・シリコン基板、３・・・第１層ポリシリコン、
４・・・絶縁膜、５・・・コンタクトホール、６・・・
第２層ポリシリコン、１０・・・酸化膜。
Ｏ９化時間（９）
自賛化ノζ長暉肩ｆ斗÷ヱ５］
仇寮オ丞の色面図
第３図FIG. 1 is a cross-sectional view for explaining one embodiment of the method for forming a semiconductor element of the present invention, FIG. 2 is an oxide growth film thickness characteristic diagram showing the relationship between oxidation time and oxide film thickness, and FIG. 3 is a conventional FIG. 3 is a cross-sectional view for explaining a method of forming a high resistance element. 1... Silicon substrate, 3... First layer polysilicon,
4... Insulating film, 5... Contact hole, 6...
Second layer polysilicon, 10... oxide film. O9 conversion time (9) Self-praise no ζ long shoulders f d ÷ ヱ 5] Figure 3 of the color surface diagram of Ojo
Claims (1)
シリコンの構造を有する高抵抗素子を半導体基板上に形
成するようにした半導体素子の形成方法において、 （ａ）半導体基板上に高抵抗素子の両端としての第１層
ポリシリコンパターンを形成した後、全面に絶縁膜を形
成し、この絶縁膜に第１層ポリシリコンの各パターン上
にてコンタクトホールを形成した後、高抵抗素子の高抵
抗体となる第２層ポリシリコンを形成する際に、 （ｂ）コンタクトホールの第１層ポリシリコンの表面に
薄く酸化膜を形成することを特徴とする半導体素子の形
成方法。[Scope of Claims] A method for forming a semiconductor element in which a high resistance element having a structure of first layer polysilicon-second layer polysilicon-first layer polysilicon is formed on a semiconductor substrate, comprising: (a) After forming first-layer polysilicon patterns as both ends of a high-resistance element on a semiconductor substrate, an insulating film was formed on the entire surface, and contact holes were formed in this insulating film on each pattern of the first-layer polysilicon. After that, when forming the second layer polysilicon which becomes the high resistance element of the high resistance element, (b) a semiconductor device characterized in that a thin oxide film is formed on the surface of the first layer polysilicon of the contact hole. Formation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13169386A JPS62290164A (en) | 1986-06-09 | 1986-06-09 | Formation of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13169386A JPS62290164A (en) | 1986-06-09 | 1986-06-09 | Formation of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62290164A true JPS62290164A (en) | 1987-12-17 |
Family
ID=15063998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13169386A Pending JPS62290164A (en) | 1986-06-09 | 1986-06-09 | Formation of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62290164A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168076A (en) * | 1990-01-12 | 1992-12-01 | Paradigm Technology, Inc. | Method of fabricating a high resistance polysilicon load resistor |
| US5172211A (en) * | 1990-01-12 | 1992-12-15 | Paradigm Technology, Inc. | High resistance polysilicon load resistor |
-
1986
- 1986-06-09 JP JP13169386A patent/JPS62290164A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168076A (en) * | 1990-01-12 | 1992-12-01 | Paradigm Technology, Inc. | Method of fabricating a high resistance polysilicon load resistor |
| US5172211A (en) * | 1990-01-12 | 1992-12-15 | Paradigm Technology, Inc. | High resistance polysilicon load resistor |
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