JPS62290149A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of a parasitic MOS transistor by forming a wiring having potential, which does exceed field threshold voltage, onto the surface of a first conductivity type region held by a second conductivity type region. CONSTITUTION:An insulating film 4 is shaped, a wiring 9 for cutting a channel is formed onto an N-type region 1 held by two P-type regions 2, 3 and a normal wiring 6 is shaped onto the wiring 9 through an insulating film 8. Predetermined high voltage is applied to the wiring 9 for cutting the channel so that the potential difference VG of the wiring 9 for cutting the channel and the N-type region 1 just under the wiring 9 holds ¦VG¦<¦VTH¦ at all times to field threshold voltage VTH determined in response to the potential deference (back gate voltage) of the P-type region 2 and the N-type region 1. Accordingly, even when the wiring 6 having potential where the potential difference of the wiring 6 and the N-type region 1 exceeds field threshold voltage VTH passes on the wiring 9 for cutting the channel, no channel is shaped in the N-type region 1 just under the wiring 9 for cutting the channel, thus operation no parasitic MOS transistor.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention provides a semiconductor device in which special wiring is provided to prevent the generation of parasitic MOS transistors. Regarding.

(Prior art) For example, as shown in FIG. 4 or FIG. 6, when the potential difference between the wiring 6 and the N-type region 1 exceeds a value called the field threshold voltage, the surface of the N-type region 1 directly under the wiring 6 is inverted to P-type, and two P A channel 7 is formed between the mold regions 2, 3. In other words, due to the potential of the wiring 6, the high potential side P
A strange MO8l transistor is formed having the type region [2 as the source, the low-potential side P-type region as the drain, and the wiring FA6 as the gate, which causes malfunction of the circuit.

Therefore, conventionally, as shown in FIG. 6, an N+ type region 8 doped with N type impurities at high temperature is provided between the P type regions 2 and 3, and by cutting the Bouillonelle 7, parasitic MO
This prevented the operation of the S transistor. Incidentally, the situation is similar not only in the case of such a P-channel type parasitic MOS transistor but also in the case of an N-channel type.

(Problems to be Solved by the Invention) However, in the conventional configuration described above, a region for forming a high concentration region for channel cutting is required in addition to the normal pattern, resulting in an increase in the device area. was. Or, in order to avoid this increase in number of people, parasitic M
It was necessary to detour the wiring to prevent the occurrence of O8l- transistors, reducing the degree of freedom in wiring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that prevents the occurrence of anomalous MOS I-transistors without increasing the element area or reducing the degree of freedom in wiring.

[Structure of the invention]

(Means for Solving the Problems) Therefore, the present invention provides a semiconductor device in which a plurality of semiconductor regions of a second conductivity type are formed sandwiching a semiconductor region of a first conductivity type, as described above. The first region sandwiched between the two conductivity type regions
A wiring having a potential not exceeding the field threshold voltage is formed on the surface of the conductivity type region.

(Function) In Figure 4.5, the potential of N-type region 1 is VD1, the potential of wire 36 is V8, which corresponds to the gate, and the potential of P, which corresponds to the source, is V8.
The potential of the wall region 2 is V, and the P-type head 1f corresponding to the drain
If the potential of i3 is the installation 1 potential, N for wiring 6
Potential difference ■G in type region 1 is V6=V, -V8 -S+' for P wall region 2 6 Potential difference in N type region 1 ■,
6 (back gate voltage) is vBG-VD-■c.

At this time, a potential difference V between the wiring 6 and the N-type region 1.

However, for the field threshold voltage vTl+, which is determined as shown in FIG. 3 according to the back gate voltage vBG, l VGl
> l V, , 1, the N-type head 141 directly below the array FA6 is inverted to P-type, and a bizarre MO3t-transistor is formed. In other words, the potential difference V between the wiring 1fA6 and the N-type region 1. exceeds the field threshold voltage V□11, an anomalous MOS transistor is formed.

Therefore, in the present invention, a new wiring is provided on the surface of the N-type region 1, and the potential difference with this N-type region 1 does not exceed the field threshold voltage ■Tll. Let it pass. As a result, since the N-type region 1 directly under the newly installed wiring is not inverted to P-type, the channel is cut off here, and the operation of the extraneous MoS transistor is prevented.

Furthermore, the present invention has the same effect as described above not only in the case of such a P-channel type oddly generated MO8l~ transistor, but also in the case of an Nji1 nonel type, just by reversing the polarity of the potential. .

(Example) The present invention will be explained below with reference to Examples.

One embodiment of the present invention is shown in FIG. 1, where J3 is an N type region 1.
, the P wall region 2.3, and the insulating film 4 are formed in the same manner as in FIG. 4 described above. In this embodiment, after forming the insulating film 4,
First, the N-shaped head 1fJ sandwiched between the two P wall regions 2 and 3,
A channel cutter 1 to a wiring line Ji 19 are formed on the substrate 1, and a normal wiring 6 is formed thereon with an insulating film 8 interposed therebetween. Then, the N-type region 1 of the wiring for channel cut and its true F
potential difference between

is the field @ value voltage determined according to the potential difference (back gate voltage) VBo between the P wall region 2 and the N type region 1 11
A predetermined high voltage is applied to the channel cut wiring 9 so that IV I < I V d [11] is always obtained for the channel cut wiring 9.

With such a configuration, what potential difference in the N-type region 1 on the channel cup wiring 9 causes the field threshold voltage v1H?
Even if a wiring 6 having a potential exceeding 1 is passed through, a channel is not formed in the N-type region 1 directly under the channel cut wiring 9, so that the strange MOS transistor does not operate.

FIG. 2 shows an example of application of the present invention. There are two P-type head regions (resistances) 12.13 in the N-type region 11, and the potential difference between the N-type head 1!11 on both [ ]-type region 2.13 is the field threshold a1'1. Wires 16a and 16b having a potential exceeding the voltage v+1 cross each other. This wiring 16
Immediately below a and 16b, a channel cut wiring 19 is maintained at a potential such that the potential difference (6) with the N-type region Ia11 becomes IV IIV, (I) with respect to the field threshold voltage vTH.
is the through line.

As can be seen from FIG. 2, in the case of the conventional high-concentration diffusion region for channel cutting, in addition to the width of the diffusion region itself, the distance between this region and other regions is also required. In the case of the channel cut wiring 19 of the present invention, the device area can be significantly reduced because it is limited only by the wiring spacing. Also, this channel cup 1-
By placing Q19 around various locations where parasitic MoS transistors may be formed as shown in the figure, wiring can be laid out freely without considering the generation of parasitic MO3l- transistors, increasing the degree of freedom in wiring. increases significantly.

In the above explanation, an example is given in which a region of one conductivity type is sandwiched between two regions of one conductivity type, but a region of another conductivity type is sandwiched between three or more regions of one conductivity type. Of course, the present invention is also applicable to cases where

〔Effect of the invention〕

As explained above, according to the present invention, a wiring having a potential not exceeding the field threshold voltage is provided on the surface of the region where the channel of the parasitic MOS transistor is formed.
Since the channel is rounded, there is no need to provide a nui region for channel cutting, and the device area can be significantly reduced.The degree of freedom in wiring is also greatly increased. It will be done.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of an embodiment of the present invention, FIG. 2 is a plan view showing a layerer 1 of an application example of the present invention, and FIG. 3 is a diagram showing the relationship between field threshold voltage and back gate voltage. The characteristic diagrams shown in FIGS. 4 and 5 are cross-sectional views for explaining the generation of parasitic MO3l- transistors, and FIG. 6 shows the structure of a conventional semiconductor device. ! FIG. 1.11...N type region, 2.3.12.13...P
Mold area, 6, 16a, 16b--Wiring, 9.19--
・Wiring for channel cut. Applicant's agent Yuka Sato 1 Figure 2 Figure 2 Vea γ-hi 9 Goushi Vea [V] Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] In a device in which two or more semiconductor regions of a second conductivity type are formed sandwiching a semiconductor region of a first conductivity type, on the surface of the first conductivity type region sandwiched between the second conductivity type regions, A semiconductor device characterized in that a wiring having a potential difference with respect to the first conductivity type region does not exceed a field threshold voltage is formed.