JPS62287668A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve breakdown strength of a field-effect transistor, and to enable reduction of the area thereof by a method wherein the drain region of the field effect transistor is provided in the main surface part of a semiconductor region of the same conductive type with the drain region and having impurity concentration lower than the drain region. CONSTITUTION:A p-type buried semiconductor region 11 is formed in the main surface part of the semiconductor substrate 1 of an MISFET Qw forming region. The semiconductor region 11 is formed by introducing p-type impurities (boron, for example) according to ion implantation using a photo resist mask covering other MISFET forming regions and a field insulating film 2. After then, at the drain region forming region of the MISFET Qw, a semiconductor region 12 is formed to one side part of a gate electrode 7B by selfalignment in relation thereto. Accordingly, because impurity concentration of the drain region can be reduced by stages, and the peak of the electric field of the drain region part can be reduced, the breakdown strength of the field-effect transistor can be improved.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device having a high voltage field effect transistor. It is about effective techniques.

[Conventional technology]

A semiconductor integrated circuit device with ultraviolet erasable non-volatile memory function! ! (hereinafter referred to as EPROM) is known. An EPROM memory cell is composed of a field effect transistor having a floating gate electrode and a control gate electrode.

Field effect transistors (memory cells) include LDD (L
There is a tendency for a highly doped drain structure to be adopted. In this field effect transistor, a drain region is composed of a semiconductor region with a high impurity concentration and a semiconductor region with a low impurity concentration of the same conductivity type (LDD region) provided between the semiconductor region with a high impurity concentration and a channel formation region. This is what I did. The field effect transistor with LDD structure is
The diffusion distance (wrapping) of the drain region toward the channel forming region side can be reduced, and the effective channel length can be ensured. In other words, a field effect transistor having an LDD structure has a feature that it can prevent short channel effects and can achieve high integration.

Since the LDD structure can be formed in the same manufacturing process, in addition to the field effect transistors that make up the memory cell, the M I S FETs of the read system and write system that make up the peripheral circuit
It will also be adopted.

Regarding EPROMs having field effect transistors employing an LDD structure, for example, Japanese Patent Application No. 1986-1
No. 84141.

[Problem that the invention seeks to solve]

The inventor of the present invention discovered the following problem as a result of the electrical characteristic test and study on the above-mentioned EPROM.

The field effect transistor (memory cell) and read system M
What is ISFET and writing MISFET?

Different operating voltages. The former has a drain-source voltage of, for example, 5.0 [V], and the latter has a drain-source voltage of, for example, 12.5 [V] (write voltage).

In an EFROM, in order to increase the speed of information read operation, the LDD structure is configured to optimize field effect transistors (memory cells) and read system M I S FETs. Therefore, the withstand voltage of the write system MISFET cannot be ensured. Writing system M I S FET
are provided in the X decoder circuit in correspondence with the number of word lines.

Therefore, it is conceivable to adopt a so-called offset structure in which the LDD portion of the drain region is formed long in order to ensure the breakdown voltage, although this is not an essential improvement in breakdown voltage, for the write-in MIS FET.

However, the offset structure is
In addition, it is necessary to increase the dimension in the channel length direction and to provide a margin for mask alignment that allows the LDD portion to be made long. Therefore, the area of the X decoder circuit increases, and the degree of integration of the EPROM decreases.

Furthermore, since the write system MISFET interval and the word line interval do not match, the layout of the memory cell array and the X-decoder circuit becomes difficult.

Another object of the present invention is to provide a technique capable of improving the withstand voltage of a field effect transistor and reducing its area in a semiconductor integrated circuit device having a field effect transistor.6.Other objects of the present invention An object of the present invention is to provide a technology that can improve the electrical reliability and the degree of integration in a semiconductor integrated circuit device having a memory function.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a field effect transistor, the drain region of the field effect transistor is formed on one side of the gate electrode in a self-aligned manner with respect to the drain region, and has the same conductivity type as the drain region and has a lower conductivity than that. Provided on the main surface of the semiconductor region with impurity concentration.

[For production]

According to the above-mentioned means, the impurity concentration in the drain region can be reduced step by step in the direction from the drain region to the channel forming region, and the peak of the electric field in the drain region can be reduced, so that the withstand voltage of the field effect transistor can be reduced. can be improved. Furthermore, since the semiconductor region can be formed in a self-aligned manner with respect to the gate electrode, and mask alignment margins in the manufacturing process can be reduced, the area of the field effect transistor can be reduced.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to an EPROM.

In addition, in the planning of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example ■]

Embodiment I of the present invention is shown in FIG. 1 (cross-sectional view of main parts) of an EPROM. In FIG.
FET, writing type n-channel MIS FET on the right side
It shows.

In FIG. 1, reference numeral 1 denotes a p-type semiconductor substrate (or well region) made of single-crystal silicon. 6 Although not shown in the figure, a complementary MIS
An i-type well region that constitutes a p-channel MISFET is provided.

Reference numeral 2 represents a field insulating film, and reference numeral 3 represents a p-type channel stopper region, which are configured to electrically isolate semiconductor elements.

The field effect transistor Qm constituting the memory cell is formed on a semiconductor substrate 1. Gate insulating film 4, floating gate electrode 5, gate insulating film 6A, control gate electrode 7A
, a pair of n-type semiconductor regions 8A, and a pair of n°-type semiconductor regions 10. The gate electrode 7A is configured integrally with the gate electrode 7A of another field effect transistor Qm in a predetermined direction, and constitutes a word line.

Although not shown, this word line is connected to the source region of the write system MISFETQw that constitutes the X decoder circuit.

The gate electrode 5 and the word line 1 are made of, for example, a polycrystalline silicon film.

Like the gate electrode 5, the gate electrode 7A is made of a polycrystalline silicon film. Further, the gate electrode 117A is made of a single layer of high melting point metals (Mo, Ta, Ti, W
) film or refractory metal silicide (MoSi2.T
It may be composed of a5i2eTiSiz, WSi2) film. Also.

The gate electrode 7A may be formed of a composite film in which a high melting point metal film or a high melting point metal silicide film is provided on top of a polycrystalline silicon film.

The semiconductor region 10 with high impurity concentration is used as a source region or a drain region.

The low impurity concentration semiconductor region (LDD section) 8A is provided on the main surface of the semiconductor substrate 1 between the high impurity concentration semiconductor region 10 and the channel formation region. Semiconductor area 8A
constitutes a field effect transistor Qm having an LDD structure. The voltage between the source and drain regions of this field effect transistor Qm is a low voltage of about 5.0 [V].

Read-out n-channel MISFETQ that constitutes the peripheral circuit
r is the semiconductor substrate 1. Gate insulating film 6B.

Gate*t! 7B, a pair of n-type semiconductor regions 8B, and a pair of n-type semiconductor regions 10.

The gate insulating film 6B and the gate insulating film 6A, and the gate electrode 7B and the gate electrode 7A are formed in the same manufacturing process. The semiconductor region (LDD section) B is formed in the same manufacturing process as the semiconductor region 8A, or is formed in a separate manufacturing process with an impurity concentration lower than that of the semiconductor region 8A.

The voltage between the source and drain of this MISFETQr is 5.
It is a low voltage of about 0 [V].

Write-related n-channel MISF E that constitutes the peripheral circuit
TQw is a semiconductor substrate 1, a gate insulating film 6B, a gate electrode 7B, and a pair of n-type semiconductor regions 8B.

It is composed of a pair of n1 type semiconductor region 10 and n- type semiconductor region 12.

The semiconductor region 12 with a low impurity concentration is formed on one side of the gate electrode 7B on the drain region side in a self-aligned manner with respect to the gate fIi electrode 7B. This semiconductor region 12 is
It has a lower impurity concentration than each of the semiconductor regions 8B and 10, and a deeper junction depth than each of the semiconductor regions 8B and 10. In other words,
Semiconductor regions 8B and 10, which are drain regions, are provided on the main surface of semiconductor region 12.

The voltage between the source and drain of MISFETQW is 12.0
~IS, is a high voltage (write voltage) of about O[V].

As shown in FIGS. 2 to 4, the semiconductor region 12 is configured to improve the withstand voltage of the M I SFET Qw that uses a high voltage.

FIG. 2 is a schematic diagram showing the dose amount of the impurity concentration of the semiconductor region provided in the M I SFET Qw. Figure 3 shows an M I S with an LDD structure that employs an offset structure.
It is a schematic diagram of FETQo. FIG. 4 shows that in each of the MISFETQw and MISFETQo,
FIG. 3 is a diagram showing the electric field strength Ex on the substrate surface.

The semiconductor region 10 shown in FIG.
[atoms/c+++” of arsenic at 80[KeV
] It is introduced and formed by Nifurugi's ion implantation.

The semiconductor region 10 is 10''' [at, ots/
cm3] and a surface concentration of 0.20 to 0.25 Cμ.
It is constructed with a bonding depth of about m.

The semiconductor region 8B is 1.0XIO” [at, o+*
It is formed by introducing phosphorus of approximately s/cm' by ion implantation of 50 [KeV] energy. Semiconductor area 8B
has a surface concentration of about 10''-1019[aLo@s/am3].

The junction depth is approximately 0.20 [μm].

The semiconductor region 12A is 1.0XIO"' [ajom
s/cmJ, and the semiconductor region 12B is 3. OX10
"3[at, oms/am"] degree, semiconductor region 12
C is 5.0XLO” [:at-orms/as”
] about 50 [KeV] by ion implantation. Each of the semiconductor regions 12A to 12G is approximately toLi[a ss/am3]
It has a surface concentration of about 0.7 to 1.4 [ttm] and a junction depth of about 0.7 to 1.4 [ttm].

The conditions of the semiconductor region 8B and the semiconductor region 10 of the MIS)'ETQo shown in FIG. 3 are the same as those of the MISFET Qw. The semiconductor region 8C having a predetermined offset length ○■- is formed under the same conditions as the semiconductor region 8B.

As shown by reference numeral 8C in FIG. 4, a semiconductor region 8C (LDD section or offset section) on the drain region side of MISFETQo has a gate? t[7B Because the influence of the electric field at the end is noticeable, 6X107~7xlO' [V
A peak electric field of about /m1 appears. On the other hand, as shown by reference numerals 12A to 12G in FIG.
Since the semiconductor region 12 is provided, the electric field in the semiconductor region 8B on the drain region side of FETQw is 5×10
It is relaxed (reduced) to about 7[V/m] or less. The peak of the electric field can be reduced by increasing the impurity concentration in the semiconductor region 12, but if the impurity concentration is too high (this will increase the extension of the depletion region toward the channel formation region and cause a short channel effect, The impurity concentration of the region 12 is appropriately selected.The semiconductor region 12 provided in the MI SFETQw is a semiconductor region (LDD section).
Regardless of the presence or absence of 8B, the peak of the electric field can be reduced.

Furthermore, the semiconductor region 12 is basically provided on the side to which a bias is applied.

In this way, MlSFETQ used as a high voltage element
By providing a W drain region (semiconductor regions 8B, 10) on the main surface of the semiconductor region 12 formed on one side of the gate electrode 7B in a self-aligned manner with respect to the gate electrode 7B, the direction from the drain region to the channel formation region is In addition, the impurity concentration in the drain region can be reduced in stages, and the peak of the electric field in the drain region can be reduced.
The breakdown voltage of W can be improved.

Moreover, there is no need to increase an extra region to form the semiconductor region 12, and the semiconductor region 12 can be connected to the gate electrode 7.
Since it is formed in a self-aligned manner with respect to B, and the mask alignment margin in the manufacturing process can be reduced, M
The area of Q w can be reduced.

Further, by providing the semiconductor region 12 only on the drain region side, a depletion region formed from the semiconductor region 12 toward the channel forming region side and the semiconductor region 10 serving as the source region
Since coupling with the depletion region formed toward the channel forming region side, so-called punch-through, can be prevented, so that a sufficient effective channel length can be ensured. In other words, it prevents the short channel effect and M I S F E T Q
Since the area of w can be reduced, the degree of integration can be improved.

In addition, as shown in FIG. 1, by providing a p-type buried semiconductor region 11 between the semiconductor region 10 and the semiconductor region 12, which are the source regions of the MISFET Qw, from the drain region to the channel forming region side. Since the extension of the formed depletion region can be reduced, punch-through can be further prevented.

In addition, by providing a p-type buried semiconductor region along the lower part of the semiconductor region 10, which is the source region of the 1MZSFETQw, a parasitic bipolar structure is created in which the source region is the emitter region, the semiconductor substrate 1 is the base region, and the drain region is the collector region. The current amplification factor (h fe) of the transistor can be reduced.

This can prevent latch-up phenomena.

Therefore, in EPROM, the writing system MISFE
Since it is possible to improve the withstand voltage of TQw and the degree of integration, it is possible to improve the electrical reliability and degree of integration of the X-decoder circuit.

In the semiconductor region 10 of the field effect transistor Qm,
A wiring (data line or source line) 15 is connected through the connection hole 14 provided in the layer interlayer 81113. Similarly, in the semiconductor regions IO of MISFETQr and QW! Through the connection hole 14 provided in the insulation wA13,
Wiring 15 is connected.

Next, regarding the manufacturing method of the EPROM configured as described above, FIGS. 5 to 7 (EPRO
This will be briefly explained using a cross-sectional view of the main part of M.

First, on the main surface of the semiconductor substrate @1 between the semiconductor element forming regions,
Field atom membrane 2. P-type channel stopper regions 3 are respectively formed.

Thereafter, as shown in FIG. 5, a gate insulating film 4 is formed on one main surface of the semiconductor substrate in the semiconductor element formation region.

Next, a p-type buried semiconductor region 11 is formed on the main surface of the semiconductor substrate 1 in the MISFETQw formation region. The semiconductor region 11 is injected with p-type impurities (for example, boron) by ion implantation using a photoresist mask covering the I S FET formation region and field insulation rm2.
can be formed by introducing Note that the semiconductor region 11 may be formed after the gate electrode 5 is formed.

After this, the gate electrode 5. is applied to the field effect transistor Qm formation region. Gate insulating film 6A and gate 1! While forming the poles 7A one after another, gate insulation fi16B is newly formed in each formation region of MISFETQr and Qw, and then the gate electrode 7B is formed.

And 1MISFETQm without a sign.

An insulating film (buffer layer or contamination gettering layer) is formed to cover at least the main surface of the semiconductor substrate 1 in the source region and drain region formation regions of Qr and Qw.

Thereafter, as shown in FIG. 6, in the drain region formation region of MISFETQW, a semiconductor region 12 is formed on one side of the gate electrode 7B in a self-aligned manner with respect to the gate electrode 7B.

The semiconductor region 12 is formed using a photoresist film covering other regions under the conditions described above.

Next, in the MISFETQm formation region, gate 1!
An n-type semiconductor region 8A is formed on the main surface of the semiconductor substrate 1 on both sides of the poles 5 and 7A, and the semiconductor substrate 1 and the semiconductor region 12 on both sides of the gate electrode 7B are formed in the formation regions of MISFETQr and Qw. An n-type semiconductor region 8B is formed on the main surface.

Thereafter, impurity introduction masks (sidewall spacers) 9 are formed on each side of gate electrodes 5.7A and 7B.

Then, using the impurity introduction mask 9, as shown in FIG.
An n-type semiconductor region 10, which is a source region or a drain region, is formed in each formation region of Qw. Through this step of forming the semiconductor region 10, field effect transistors 1a Qm1MLSl'ETQr and Qw are formed, respectively.

Next, as shown in FIG. 1, the interlayer insulating film 13, connection hole 14 and wiring 15 are sequentially formed to complete the EFROM of this embodiment.

[Example ■]

Embodiment 2 is another embodiment of the present invention in which the write MISFET of Embodiment I is provided in the well region.

An EFROM which is an embodiment (2) of the present invention is shown in FIG. 8 (a sectional view of the main part).

EPROM writing system MIS FETQ of this embodiment (■)
w is constructed as shown in FIG. In other words, M
ISFETQw is provided in the n-type well region 12A, and semiconductor regions 8B and 10, which are source regions, are provided in the main surface of the p-type semiconductor region 11A.

The semiconductor region 11A is formed on one side of the gate electrode 7B on the source side in a self-aligned manner with respect to the gate electrode 7B, and has substantially the same function as the buried semiconductor region 11 of Example I.

The well region 12A has substantially the same function as the semiconductor region 12 of the embodiment (2). The well region 12A is formed in the channel formation region so that the dimension between the semiconductor region 11A and the semiconductor region 8B on the drain region side is self-aligned with one side of the gate electrode 7B on the drain region side. . That is, since the semiconductor region 11A is formed in a self-aligned manner, the well region 12A is formed in a self-aligned manner as a result.

M I S F E T Q w configured like this
In this case, substantially the same effect as in the first embodiment can be obtained.

In the above, the invention made by the present inventor has been specifically explained based on the above embodiments, but one aspect of the present invention is as follows.

It goes without saying that the invention is not limited to the embodiments described above, and that various modifications may be made without departing from the spirit thereof.

For example, one aspect of the present invention is to replace an LDD structure MIS FET with a so-called double drain structure MIS FET in which a drain region is formed by providing a low impurity concentration region along the lower part of a high impurity concentration region. Can be applied.

Further, the present invention provides an MIS with a so-called single drain structure in which the drain region is formed only from a region with high impurity concentration.
It can be applied to FET.

Furthermore, the present invention is not limited to MISFETs.

It can be applied to field effect transistors with floating gate electrodes.

Furthermore, the present invention is not limited to E P ROM, but also applies to high voltage M, IS FETs, such as semiconductor integrated circuit devices (EEPROM) having an electrically erasable non-volatile memory function.
The present invention can be applied to a semiconductor integrated circuit device having.

〔Effect of the invention〕

A brief explanation of the effects that can be obtained by one representative invention among the inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a field effect transistor, a drain region of the field effect transistor is formed on one side of a gate electrode in a self-aligned manner thereto. By providing the impurity concentration in the main surface of a semiconductor region that is of the same conductivity type as the drain region and has a lower impurity concentration than that of the drain region, the impurity concentration of the drain region is gradually reduced in the direction from the drain region to the channel formation region. Since the peak of the electric field can be reduced, the withstand voltage of the field effect transistor can be improved. Furthermore, since the semiconductor region can be formed in a self-aligned manner with respect to the gate electrode, and mask alignment margins in the manufacturing process can be reduced, the area of the field effect transistor can be reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of an EPROM which is Embodiment 1 of the present invention. FIG. 2 is a schematic diagram showing the dose amount of the semiconductor region provided in the M I S FET shown in FIG. 1, and FIG.
A schematic diagram of a MISFET with an LDD structure that employs an offset structure. 4 is a diagram showing the electric field strength of the MISFET shown in FIGS. 2 and 3, and FIGS. 5 to 7 are diagrams showing the electric field strength of the MISFET shown in FIGS.
FIG. 8 is a cross-sectional view of the main part of an EPROM which is Embodiment (2) of the present invention. In the figure, 1... semiconductor substrate, 2... field insulating film, 3... channel stopper region, 4+6A, 6B...
・Gate insulating film, 5, 7A, 7B...Gate 1! very,
8A. 8B, 8G, 10.11, 12A... semiconductor region. 12...Buried semiconductor region, 12A...Well region, Qm...Field effect transistor, Qr, Qw...
It is MISFET. To I-ゝma 匁■寥MACHINO C tate condyle/general beo 2

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a field effect transistor, the drain region of the field effect transistor is formed on one side of a gate electrode in a self-aligned manner and is the same as the drain region. 1. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is provided on the main surface of a semiconductor region of a conductive type and with a lower impurity concentration. 2. The drain region includes a high impurity concentration region and a low impurity concentration region with a higher impurity concentration than the semiconductor region, which is provided on the main surface of the semiconductor region between the high impurity concentration region and the channel formation region. A semiconductor integrated circuit device according to claim 1, characterized in that it is comprised of: 3. The drain region is composed of a high impurity concentration region and a low impurity concentration region with a higher impurity concentration than the semiconductor region, which is provided on the main surface of the semiconductor region along the lower part of the high impurity concentration region. A semiconductor integrated circuit device according to claim 1, characterized in that: 4. Between the source region of the field effect transistor and the semiconductor region, or on the main surface of the substrate or well region along the lower part of the source region, there is a conductivity type that is the same as that of the substrate or well region, and has a higher conductivity than that of the substrate or well region. A semiconductor integrated circuit device according to any of claims 1 to 3, characterized in that a semiconductor region with an impurity concentration is provided.