JPS6228762Y2 - - Google Patents

Info

Publication number
JPS6228762Y2
JPS6228762Y2 JP18237581U JP18237581U JPS6228762Y2 JP S6228762 Y2 JPS6228762 Y2 JP S6228762Y2 JP 18237581 U JP18237581 U JP 18237581U JP 18237581 U JP18237581 U JP 18237581U JP S6228762 Y2 JPS6228762 Y2 JP S6228762Y2
Authority
JP
Japan
Prior art keywords
adhesive
resin base
integrated circuit
time
circuit element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18237581U
Other languages
Japanese (ja)
Other versions
JPS5887350U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18237581U priority Critical patent/JPS5887350U/en
Publication of JPS5887350U publication Critical patent/JPS5887350U/en
Application granted granted Critical
Publication of JPS6228762Y2 publication Critical patent/JPS6228762Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は廉価で信頼性の高い回路基板に関す
る。
[Detailed Description of the Invention] The present invention relates to an inexpensive and highly reliable circuit board.

従来第1図に示すように積層された導電箔1
2,12……を有する樹脂基台11を利用して一
方に発光ダイオード16,16……等を利用した
表示部10、他方に集積回路素子4を載置固着し
配線を施こした駆動演算部20を有する表示装置
においては、表示部10の大きさに対し比較的小
さい占有体積で各種機器に取付けられ、しかも配
線等が少ないので取り扱い易く好んで使用され
る。ところが、全体を廉価にするため、基板にセ
ラミツク等を用いないで樹脂基台に導電箔を積層
したいわゆるプリント基板を用いるので種々の問
題が生じる。特に表示部10と駆動演算部20が
近いと表示部10が機器の外部から観察されるよ
うに配置するため、外光や温度変化といつた環境
の変化を駆動演算部20が受けやすく、その時誤
動作を生じないため集積回路素子4を環境から隔
離するのが好ましい。ところが樹脂等で集積回路
素子4覆うと暖かい時と寒い時とで樹脂等と集積
回路素子4等と樹脂基台11との熱膨張係数の相
異等から歪や応力が発生し、とりわけ集積回路素
子4に配線を施こす金属細線17,17が切断や
剥離を生じるため好ましくない。
Conventionally, conductive foil 1 is laminated as shown in FIG.
2, 12..., a display section 10 using light emitting diodes 16, 16..., etc. is placed on one side, and an integrated circuit element 4 is placed and fixed on the other side, and wiring is provided. The display device having the section 20 can be attached to various types of equipment with a relatively small volume compared to the size of the display section 10, and there are few wirings, etc., so it is easy to handle and is used favorably. However, in order to reduce the overall cost, various problems arise because a so-called printed circuit board, in which a conductive foil is laminated on a resin base, is used instead of using ceramic or the like for the board. In particular, when the display unit 10 and the drive calculation unit 20 are located close to each other, the display unit 10 is arranged so that it can be observed from the outside of the device. It is preferable to isolate integrated circuit device 4 from the environment to prevent malfunctions. However, when the integrated circuit element 4 is covered with resin, etc., distortion and stress occur due to differences in thermal expansion coefficients between the resin, etc., the integrated circuit element 4, etc., and the resin base 11 depending on whether it is warm or cold. This is not preferable because the thin metal wires 17, 17 for wiring the element 4 may be cut or peeled off.

そこで図のような枠体13で覆うと、これらの
欠点が改まるが、樹脂基台11はもともと薄板
(プリブレグ)の積層体であるため気泡微粒子が
たまりやすい。それに加えて第2図に示すように
導電箔12,12……はワイヤボンド特性を向上
させるためメツキや粗面加工やエツチングをくり
返すため全体的に丸味がついたり表面に凹凸がつ
きやすい。このため導電箔12,12……の周辺
には気泡がたまりやすいので枠体13を接着剤1
5で貼着しようとすると接着剤15の硬化中に気
泡が集合し成長しやすい。この時形成される空洞
18,18……により接着力が低下するのみなら
ず外気(特に湿気)が枠体内に侵入するので長時
間使用しようとすると不良を生じた。
Therefore, if the resin base 11 is covered with a frame 13 as shown in the figure, these drawbacks can be corrected, but since the resin base 11 is originally a laminate of thin plates (pre-regs), air bubble particles tend to accumulate there. In addition, as shown in FIG. 2, the conductive foils 12, 12, . . . are subjected to repeated plating, roughening, and etching to improve wire bonding properties, so they tend to become rounded overall and have uneven surfaces. For this reason, air bubbles tend to accumulate around the conductive foils 12, 12..., so the frame 13 is
If an attempt is made to attach the adhesive 15 using adhesive 15, air bubbles tend to gather and grow while the adhesive 15 is curing. The cavities 18, 18, . . . formed at this time not only reduce the adhesive force but also allow outside air (particularly moisture) to enter the frame, resulting in defects when used for a long time.

本考案はこのような欠点をあらためるためにな
されたもので、以下本考案を実施例に基づいて詳
細に説明する。
The present invention has been devised to overcome these drawbacks, and will be described in detail below based on embodiments.

第3図は本考案実施例の回路基板の要部断面図
で、1はガラスエポキシ樹脂、紙エポキシ樹脂、
紙フエノール樹脂、ベーク樹脂等からなる樹脂基
台で、2,2……は樹脂基台1に積層された銅等
からなる導電箔である。3は集積回路素子(第1
図4参照)を覆うセラミツク、硬質樹脂等からな
る枠体で5,5′は枠体3を樹脂基台1に貼着す
るための接着剤である。
FIG. 3 is a sectional view of the main parts of the circuit board according to the embodiment of the present invention, in which 1 is a glass epoxy resin, a paper epoxy resin,
A resin base is made of paper phenol resin, baked resin, etc., and 2, 2 . . . are conductive foils made of copper or the like laminated on the resin base 1. 3 is an integrated circuit element (first
(see FIG. 4) is made of ceramic, hard resin, etc., and 5 and 5' are adhesives for sticking the frame 3 to the resin base 1.

この接着剤5,5′のうち枠体3側にある接着
剤5はゲル化時間の長い接着剤で、樹脂基台1側
にある接着剤5′はゲル化時間の短い接着剤であ
る。このような接着剤5,5′を用いる事によ
り、接着剤の硬化にあたつてまずゲル化時間の短
い接着剤5′が樹脂基台1の凹部へ侵透してしま
う。この時気泡が多少生ずるものの2つの接着剤
5,5′の接合面へ集まりやすく、この状態でゲ
ル化時間の短い接着剤の界面は平坦であるからゲ
ル化時間の長い接着剤5の硬化に併つて気泡が追
い出されてしまう。このような効果を得る接着剤
5,5′の例として、ゲル化時間の長い接着剤5
は厚さ50乃至300μmのエポキシ樹脂系接着剤で
あり、そのゲル化時間は例えば16分で、一方ゲル
化時間の短い接着剤5′は厚さ50乃至150μmでゲ
ル化時間は8分程度であつた。これらの接着剤の
厚さはゲル化時間の短い接着剤5′が基板の凹
凸、即ち導電箔2,2……の厚さ(例えば35μ
m)より充分厚く、そしてゲル化時間の長い接着
剤5はゲル化時間の短い接着剤5′と等しいかそ
れ以上の厚みであればよい。しかしいずれも厚す
ぎると接着剤内部の分子の共有結合力に接着力が
依存してしまうので、フアンデルワールス力の及
ぶ程度で薄い方がよい。一方ゲル化時間は無機質
フイラー(例えばガラスとかマイカ)の微量調整
で可能であるが、3フツ化ほう素モノエチルアミ
ン等の硬化剤の添加後の放置時間によつて調整し
てもよく、いずれの場合にもその目安は、上層が
ゲル化する前にゲル化した下層が凹部等に侵透で
きればよいので、ゲル化時間の差が数分以上あれ
ばよい。しかし生産性からは塗布時間の制約のな
い前者の方が好ましい。
Of these adhesives 5, 5', the adhesive 5 on the frame 3 side is an adhesive with a long gelling time, and the adhesive 5' on the resin base 1 side is an adhesive with a short gelling time. By using such adhesives 5, 5', the adhesive 5' having a short gelation time penetrates into the recessed portion of the resin base 1 first when the adhesive is cured. Although some bubbles are generated at this time, they tend to gather on the bonding surface of the two adhesives 5 and 5', and in this state, the interface of the adhesive with a short gelation time is flat, so that the adhesive 5 with a long gelation time cannot be cured. At the same time, air bubbles are expelled. An example of adhesives 5 and 5' that achieve this effect is adhesive 5 with a long gelling time.
is an epoxy resin adhesive with a thickness of 50 to 300 μm, and its gelling time is, for example, 16 minutes, while adhesive 5', which has a short gelling time, is 50 to 150 μm thick and has a gelling time of about 8 minutes. It was hot. The thickness of these adhesives is such that the adhesive 5', which has a short gelation time, has a short gelation time.
The adhesive 5 which is sufficiently thicker than m) and has a longer gelling time may have a thickness equal to or greater than that of the adhesive 5' which has a shorter gelling time. However, if the adhesive is too thick, the adhesive force will depend on the covalent bonding force of the molecules inside the adhesive, so it is better to be as thin as the Van der Waals force can be applied. On the other hand, the gelation time can be adjusted by finely adjusting the amount of inorganic filler (e.g. glass or mica), but it may also be adjusted by the standing time after adding a curing agent such as boron trifluoride monoethylamine. In this case, as long as the gelled lower layer can penetrate into the recesses etc. before the upper layer gels, the difference in gelation time should be several minutes or more. However, from the viewpoint of productivity, the former method, which does not have restrictions on coating time, is preferable.

以上の如く本考案は樹脂基台と、樹脂基台に積
層された導電箔と、導電箔上に載置固着された集
積回路素子と、集積回路素子を覆い接着剤にて樹
脂基台に貼着された枠体とからなり、前記接着剤
はゲル化時間の異なる複数の接着剤層からなる回
路基板であるから、廉価な樹脂基台が利用でき、
しかも完全に封止できるので信頼性が高い。
As described above, the present invention includes a resin base, a conductive foil laminated on the resin base, an integrated circuit element placed and fixed on the conductive foil, and a cover for the integrated circuit element and attached to the resin base with adhesive. Since the circuit board is made up of a plurality of adhesive layers having different gelation times, an inexpensive resin base can be used.
Moreover, it is highly reliable because it can be completely sealed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は回路基板の断面図、第2図は従来の回
路基板の要部断面図、第3図は本考案実施例の回
路基板の要部断面図である。 1,11……樹脂基台、2,2…12,12…
…導電箔、3,13……枠体、4……集積回路素
子、5,5……接着剤。
FIG. 1 is a sectional view of a circuit board, FIG. 2 is a sectional view of a main part of a conventional circuit board, and FIG. 3 is a sectional view of a main part of a circuit board according to an embodiment of the present invention. 1, 11...Resin base, 2, 2...12, 12...
...Conductive foil, 3, 13... Frame, 4... Integrated circuit element, 5, 5... Adhesive.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 樹脂基台と、樹脂基台に積層された導電箔と、
導電箔上に載置固着された積積回路素子と、集積
回路素子を覆い接着剤にて樹脂基台に貼着された
枠体とからなり、前記接着剤は枠体側より基板側
の方がゲル化時間が数分以上短かくなるような複
数の接着剤層からなる事を特徴とする回路基板。
A resin base, a conductive foil laminated on the resin base,
It consists of an integrated circuit element placed and fixed on a conductive foil, and a frame that covers the integrated circuit element and is affixed to a resin base with an adhesive. A circuit board comprising a plurality of adhesive layers whose gelation time is shortened by several minutes or more.
JP18237581U 1981-12-07 1981-12-07 circuit board Granted JPS5887350U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18237581U JPS5887350U (en) 1981-12-07 1981-12-07 circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18237581U JPS5887350U (en) 1981-12-07 1981-12-07 circuit board

Publications (2)

Publication Number Publication Date
JPS5887350U JPS5887350U (en) 1983-06-14
JPS6228762Y2 true JPS6228762Y2 (en) 1987-07-23

Family

ID=29980687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18237581U Granted JPS5887350U (en) 1981-12-07 1981-12-07 circuit board

Country Status (1)

Country Link
JP (1) JPS5887350U (en)

Also Published As

Publication number Publication date
JPS5887350U (en) 1983-06-14

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