JPS63114152A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS63114152A JPS63114152A JP25987486A JP25987486A JPS63114152A JP S63114152 A JPS63114152 A JP S63114152A JP 25987486 A JP25987486 A JP 25987486A JP 25987486 A JP25987486 A JP 25987486A JP S63114152 A JPS63114152 A JP S63114152A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- film
- metal
- circuit board
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000010409 thin film Substances 0.000 claims abstract description 15
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000853 adhesive Substances 0.000 claims abstract description 6
- 230000001070 adhesive effect Effects 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 3
- 239000011347 resin Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract 3
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000007789 sealing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発り」はリードフレームを用いてリード付は組立をし
、清面封止してなる混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit formed by assembling a leaded circuit using a lead frame and sealing the surface of the circuit.
従来のこの棟の混成集積回路は第２図の断面図に示すよ
うに、金属のリードフレームのアイランド部１ａに接着
剤４を用いて絶縁性の回路基板５を接着し、回路基板５
上に能動素子７と受動索子８を搭載し、金属細＃９によ
シ回路基板５上の回路素子と基板５および基板５とリー
ドフレームのリードｌｂとを接続した後、トランスファ
モールド封止法により外装樹脂１１で包んで封止してい
た０
〔発明が解決しようとする問題点〕
上述した従来の混成集積回路の構造では、回路基板を接
着剤を用いて金属のリードフレームのアイランドに接着
しているため、回路基板上に搭載する素子の放熱特性が
悪い。更に、回路基板も板厚が厚いので多層化にも限度
がある。従って、高集積化できにくいという欠点を持っ
ている。In the conventional hybrid integrated circuit of this building, as shown in the cross-sectional view of FIG.
After mounting the active element 7 and the passive cable 8 on the top and connecting the circuit element on the circuit board 5 to the board 5 and the lead lb of the lead frame through the metal thin #9, transfer mold sealing is performed. [Problems to be Solved by the Invention] In the conventional hybrid integrated circuit structure described above, the circuit board is attached to the island of the metal lead frame using an adhesive. Because it is bonded, the heat dissipation characteristics of the elements mounted on the circuit board are poor. Furthermore, since the circuit board is also thick, there is a limit to how many layers can be added. Therefore, it has the disadvantage that it is difficult to achieve high integration.
本発明の混成集積回路は、リードフレームのアイランド
に数ミクロンという厚さのアルミナ層を設け、この上に
数ミクロンの金属薄膜で、板厚を気にせすに回路を形成
している。更に金属薄膜に直接、放熱を必要とする素子
を搭載して放熱特性Ｅ良くし、更に金属薄膜の上に従来
の回路基板を載せ、金属薄膜２回路基板相互の接続を行
ってから外装の樹脂封止を行っている。In the hybrid integrated circuit of the present invention, an alumina layer with a thickness of several microns is provided on the island of a lead frame, and a circuit is formed on this with a thin metal film of several microns, regardless of the board thickness. Furthermore, elements that require heat dissipation are mounted directly on the metal thin film to improve the heat dissipation characteristic E. Furthermore, a conventional circuit board is placed on the metal thin film, and the two metal thin film circuit boards are connected to each other before the exterior resin is applied. It is being sealed.
つぎに本発明を実施例によシ説明する。 Next, the present invention will be explained using examples.
第１図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing one embodiment of the present invention.
第１図において、金属のリードフレームのアイランドｌ
ａ上にアルミナ層２を設け、この上に金属薄膜回路３を
形成する。更に金属膜６で回路を構成した回路基板５を
接着剤４を用いて金属薄膜回路３の上に接着する。この
回路基板５には大きな貫通穴があシ、この穴の部分を通
して、放熱性を要する能動または受動素子７を金属薄膜
回路３上に直接搭載する。回路基板５上にも能動素子ま
たは受動素子８を搭載し、金属細線９を用いて、素子と
回路基板との間および回路基板とリードフレームのリー
ドｌｂとの間を接続する。また、回路基板５と金属薄膜
回路３との接続１０は、回路基板の接着と同時に実施す
る。それから、トランスファーモールド法を用いて、樹
脂１１による外装を行う。In Figure 1, the island l of the metal lead frame
An alumina layer 2 is provided on a, and a metal thin film circuit 3 is formed thereon. Further, a circuit board 5 having a circuit formed of a metal film 6 is adhered onto the metal thin film circuit 3 using an adhesive 4. This circuit board 5 has a large through hole, and an active or passive element 7 requiring heat dissipation is directly mounted on the metal thin film circuit 3 through this hole. An active element or a passive element 8 is also mounted on the circuit board 5, and thin metal wires 9 are used to connect between the element and the circuit board and between the circuit board and the lead lb of the lead frame. Further, the connection 10 between the circuit board 5 and the metal thin film circuit 3 is performed at the same time as bonding the circuit board. Then, the exterior is covered with resin 11 using a transfer molding method.
以上説明したように本発明は、放熱特性が必要である素
子についてはリードフレームのアイランドに直接マウン
トできる構造を取ることによシ、よりハイパワーの混成
集積回路を実現できる。また、数ミクロンのアルミナ層
上に金属薄膜回路を形成し、回路基板との接続が可能に
なったことによシ多層化、高機能化にも効果がある。As described above, the present invention can realize a higher power hybrid integrated circuit by adopting a structure in which elements requiring heat dissipation characteristics can be directly mounted on the islands of the lead frame. Furthermore, by forming a metal thin film circuit on an alumina layer of several microns and making it possible to connect it to a circuit board, it is effective in multilayering and increasing functionality.
第１図は本発明の一実施例を示す断面図、第２図は従来
の混成集積回路の断面図である。
１ａ・・・・・・リードフレームのアイランド、１ｂ・
・・°°°リードフレームのリード、２・・・・・・ア
ルミナ層、３・・・・・・金属薄膜回路、４・・・・・
・接着剤、５・・・・・・回路基板、６・・・・・・金
属膜、７・・・・・・能動素子、８・・・・・・受動素
子、９・・・・・・金属細線、１０・・・・・・接続部
、１１・・・・・・封止樹脂。
第 グ ルＱ゛
羨 ２ 圓FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional hybrid integrated circuit. 1a...Lead frame island, 1b...
...°°° Lead frame lead, 2... Alumina layer, 3... Metal thin film circuit, 4...
・Adhesive, 5... Circuit board, 6... Metal film, 7... Active element, 8... Passive element, 9...・Thin metal wire, 10...Connection part, 11...Sealing resin. Group Q゛envy 2 En
Claims (1)
層を設け、その上に金属薄膜で回路を形成し、さらにそ
の上に、所要な部分に貫通穴を設けた絶縁性の回路基板
を接着剤を用いて接着し、前記金属薄膜上および回路基
板上に能動素子と受動素子を搭載し、金属細線あるいは
熱圧着法等を用いて金属薄膜、回路基板および能動素子
、受動素子間の回路を形成し、樹脂封止してなることを
特徴とする混成集積回路。A thin alumina layer is provided on the island part of the metal lead frame, a circuit is formed with a thin metal film on top of that, and an insulating circuit board with through holes in the required areas is placed on top of that using adhesive. The active element and the passive element are mounted on the metal thin film and the circuit board, and a circuit is formed between the metal thin film, the circuit board, the active element, and the passive element using a thin metal wire or thermocompression bonding method. A hybrid integrated circuit characterized by being sealed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25987486A JPS63114152A (en) | 1986-10-30 | 1986-10-30 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25987486A JPS63114152A (en) | 1986-10-30 | 1986-10-30 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63114152A true JPS63114152A (en) | 1988-05-19 |
Family
ID=17340150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25987486A Pending JPS63114152A (en) | 1986-10-30 | 1986-10-30 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63114152A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287656A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Hybrid integrated circuit |
| EP0378209A2 (en) * | 1989-01-11 | 1990-07-18 | Kabushiki Kaisha Toshiba | Hybrid resin-sealed semiconductor device |
| EP0656150A4 (en) * | 1992-08-21 | 1995-11-29 | Olin Corp | Metal electronic package incorporating a multi-chip module. |
| US7453138B2 (en) | 2002-09-24 | 2008-11-18 | Hitachi, Ltd. | Electronic circuit device and manufacturing method thereof |
| JP2015162516A (en) * | 2014-02-26 | 2015-09-07 | 株式会社ジェイデバイス | semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4994271A (en) * | 1973-01-10 | 1974-09-06 |
-
1986
- 1986-10-30 JP JP25987486A patent/JPS63114152A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4994271A (en) * | 1973-01-10 | 1974-09-06 |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287656A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Hybrid integrated circuit |
| EP0378209A2 (en) * | 1989-01-11 | 1990-07-18 | Kabushiki Kaisha Toshiba | Hybrid resin-sealed semiconductor device |
| EP0656150A4 (en) * | 1992-08-21 | 1995-11-29 | Olin Corp | Metal electronic package incorporating a multi-chip module. |
| US7453138B2 (en) | 2002-09-24 | 2008-11-18 | Hitachi, Ltd. | Electronic circuit device and manufacturing method thereof |
| JP2015162516A (en) * | 2014-02-26 | 2015-09-07 | 株式会社ジェイデバイス | semiconductor device |
| US10236231B2 (en) | 2014-02-26 | 2019-03-19 | J-Devices Corporation | Semiconductor device |
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