JPH02275655A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH02275655A JPH02275655A JP9796489A JP9796489A JPH02275655A JP H02275655 A JPH02275655 A JP H02275655A JP 9796489 A JP9796489 A JP 9796489A JP 9796489 A JP9796489 A JP 9796489A JP H02275655 A JPH02275655 A JP H02275655A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- resin
- island
- board
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000012790 adhesive layer Substances 0.000 abstract description 4
- 238000000465 moulding Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子をモールド樹脂で樹脂封止した混成
４Ａｆｉ回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid 4Afi circuit in which a semiconductor element is sealed with a molding resin.
従来、樹脂封止型の混成集積回路は、第３図（ａ）、（
ｂ）に示すように、金属製のリードフレームのアイラン
ド７に印刷回路基板８を接着剤層６を用いて接着して重
層体を形成し、半導体素子、能動素子および受動素子５
を搭載し、これを金属細線４を用いて半導体素子５と回
路基板８および回路基板８と外部リード端子ｌとを接続
することにより回路形成をし、さらにモールド樹脂２を
用いて樹脂封止を行う構造となっている。Conventionally, resin-sealed hybrid integrated circuits are shown in Fig. 3(a), (
As shown in b), a printed circuit board 8 is bonded to an island 7 of a metal lead frame using an adhesive layer 6 to form a multilayer body, and a semiconductor element, an active element, and a passive element 5 are attached.
is mounted, a circuit is formed by connecting the semiconductor element 5 and the circuit board 8 and the circuit board 8 and the external lead terminal l using the thin metal wire 4, and further resin sealing is performed using the mold resin 2. It is structured to do so.
上述した従来の混成集積回路は、アイランドのサイズが
大きく、モールド樹脂の上下の密着面積が少ないため、
温度ストレスによる樹脂強度低下が起り、樹脂クラック
および金属細線の断線等の問題があった。In the conventional hybrid integrated circuit described above, the island size is large and the contact area between the top and bottom of the mold resin is small, so
The resin strength decreased due to temperature stress, and there were problems such as resin cracks and breakage of thin metal wires.
本発明の目的は、樹脂クラックおよび金属細線の断線等
がない混成集積回路を提供することにある。An object of the present invention is to provide a hybrid integrated circuit that is free from resin cracks and breaks in thin metal wires.
本発明の混成集積回路は、外部リードを有するリードフ
レームのアイランドと回路基板とを接着剤を用いて接着
し、前記アイランドと回路基板の重層を貫通する１個以
上の貫通穴部を設け、この回路基板の貫通穴部以外の領
域に半導体素子、能動素子あるいは受動素子を搭載し、
かつ前記外部リード以外を前記貫通穴部を含めて樹脂封
止して構成されている。In the hybrid integrated circuit of the present invention, an island of a lead frame having external leads and a circuit board are bonded together using an adhesive, and one or more through holes are provided to penetrate the layered layer of the island and the circuit board. Mounting semiconductor elements, active elements, or passive elements in areas other than the through-holes of the circuit board,
In addition, everything other than the external leads including the through hole portions are sealed with resin.
次に発明について図面を参照して説明する。 Next, the invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ′線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line A-A' of a first embodiment of the present invention.
混成集積回路は、厚さ０．１５〜０．２５ｍｍのリード
フレームのアイランド７と印刷回路基板８を接着剤層６
を用いて接着して第３図の従来と同じ重層を形成する。The hybrid integrated circuit consists of an island 7 of a lead frame with a thickness of 0.15 to 0.25 mm and a printed circuit board 8 bonded to an adhesive layer 6.
to form the same multilayer as the conventional one shown in FIG.
次に、直径０．５〜３．Ｑｍｍ程度の貫通穴部３を基板
８の中央に形成し、さらに貫通穴部３以外の回路゛基板
領域に半導体素子５を搭載し、直径２５〜３ Ｑ ）ｔ
ｍの金属細線４を用いて外部リード１と内部の基板８
とをボンディングして回路形成後、モールド樹脂２によ
り樹脂封止したものである。Next, the diameter is 0.5 to 3. A through hole 3 with a diameter of approximately Q mm is formed in the center of the substrate 8, and a semiconductor element 5 is mounted in the circuit/substrate area other than the through hole 3, with a diameter of 25 to 3 Q)t.
The external lead 1 and the internal board 8 are connected using a thin metal wire 4 of m.
After bonding and forming a circuit, the circuit is sealed with mold resin 2.
貫通穴部３にもモールド樹脂２が充填するので、基板８
との密着度がよくなる。Since the through hole portion 3 is also filled with the mold resin 2, the substrate 8
The degree of adhesion will improve.
第２図は本発明の第２の実施例の断面図で、半導体素子
５の搭載部である回路基板８の１／２厚程度のザグリ９
を入れた構造を示している。FIG. 2 is a cross-sectional view of a second embodiment of the present invention, in which a counterbore 9 of about 1/2 thickness of a circuit board 8 on which a semiconductor element 5 is mounted.
It shows a structure with .
本実施例では、半導体素子５側のモールド樹脂２が例え
ばフラットのＳＯＰ等薄いパッケージのとき半導体素子
５の裏面研磨せずに搭載できる構造である。In this embodiment, when the mold resin 2 on the side of the semiconductor element 5 is a thin package such as a flat SOP, the semiconductor element 5 can be mounted without polishing the back surface.
以上説明したように本発明は、リードフレームのアイラ
ンドと回路基板とを貫通穴部を介してモールド樹脂にて
充填されたパッケージであるため、モールド樹脂の上下
の密着面積が増加し、温度ストレスにより樹脂強度低下
によるモールドクラックおよび金属細線の断線を防ぐこ
とができる効果がある。As explained above, since the present invention is a package in which the island of the lead frame and the circuit board are filled with mold resin through the through hole, the contact area between the top and bottom of the mold resin increases, and the temperature stress This has the effect of preventing mold cracks and breakage of thin metal wires due to a decrease in resin strength.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ’線断面図、第２図は本発明の第２の実施例
のＡ−Ａ’線断面図、第３図（ａ）、（ｂ）は従来の混
成Ｓ積回路の一例の平面図及びＡ−Ａ’線断面図である
。
１・・・リード端子、２・・・モールド樹脂、３・・・
貫通穴部、４・・・金属細線、５・・・半導体素子、６
・・・接着剤層、７・・・アイランド、８・・・回路基
板、９・・・ザグリ。FIGS. 1(a) and (b) are a plan view and a cross-sectional view taken along the line A-A' of the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line A-A' of the second embodiment of the present invention. 3(a) and 3(b) are a plan view and a cross-sectional view taken along the line AA' of an example of a conventional hybrid S product circuit. 1...Lead terminal, 2...Mold resin, 3...
Through hole portion, 4... Metal thin wire, 5... Semiconductor element, 6
...Adhesive layer, 7...Island, 8...Circuit board, 9...Counterbore.
Claims (1)
路基板とを接着剤を用いて接着し、前記アイランドと回
路基板の重層を貫通する１個以上の貫通穴部を設け、こ
の回路基板の貫通穴部以外の領域に半導体素子，能動素
子あるいは受動素子を搭載し、かつ前記外部リード以外
を前記貫通穴部を含めて樹脂封止することを特徴とする
混成集積回路。An island of a lead frame having an external lead and a circuit board are bonded together using an adhesive, and one or more through holes penetrating the layered layer of the island and the circuit board are provided. 1. A hybrid integrated circuit, wherein a semiconductor element, an active element, or a passive element is mounted in a region, and parts other than the external leads, including the through-hole part, are sealed with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9796489A JPH02275655A (en) | 1989-04-17 | 1989-04-17 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9796489A JPH02275655A (en) | 1989-04-17 | 1989-04-17 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02275655A true JPH02275655A (en) | 1990-11-09 |
Family
ID=14206357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9796489A Pending JPH02275655A (en) | 1989-04-17 | 1989-04-17 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02275655A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07135277A (en) * | 1993-11-11 | 1995-05-23 | Nec Corp | Semiconductor device |
| JPWO2006090827A1 (en) * | 2005-02-25 | 2008-08-07 | 京セラ株式会社 | Electronic device and manufacturing method thereof |
| JP2017170806A (en) * | 2016-03-24 | 2017-09-28 | 古河電気工業株式会社 | Composite body of metallic member and resin mold |
-
1989
- 1989-04-17 JP JP9796489A patent/JPH02275655A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07135277A (en) * | 1993-11-11 | 1995-05-23 | Nec Corp | Semiconductor device |
| JPWO2006090827A1 (en) * | 2005-02-25 | 2008-08-07 | 京セラ株式会社 | Electronic device and manufacturing method thereof |
| JP2017170806A (en) * | 2016-03-24 | 2017-09-28 | 古河電気工業株式会社 | Composite body of metallic member and resin mold |
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