JPS62285459A - Wiring method for chip-shaped electronic device - Google Patents

Wiring method for chip-shaped electronic device

Info

Publication number
JPS62285459A
JPS62285459A JP12894786A JP12894786A JPS62285459A JP S62285459 A JPS62285459 A JP S62285459A JP 12894786 A JP12894786 A JP 12894786A JP 12894786 A JP12894786 A JP 12894786A JP S62285459 A JPS62285459 A JP S62285459A
Authority
JP
Japan
Prior art keywords
resist
chip
wiring
shaped electronic
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12894786A
Other languages
Japanese (ja)
Inventor
Shinichiro Ishida
進一郎 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP12894786A priority Critical patent/JPS62285459A/en
Publication of JPS62285459A publication Critical patent/JPS62285459A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To conduct fine wirings without disconnection by filling a section between chip-shaped electronic devices with a resist, flattening the upper surface of the resist and forming a wiring pattern. CONSTITUTION:Chip-shaped electronic devices 2 are arranged adjacently on a substrate 1 and joined. A positive type resist 4 is applied on the surfaces of the devices 2 and in the clearances 3 of the devices. Only the surface layer section of the resist is exposed L and developed, the resists are left in the clearances 3, and sections among the devices 2 are flattened. When a wiring material 5 is deposited on the upper sections of the devices 2 and the clearances 3, the wiring material 5 is supported by the resists 4, and is not disconnected. The wiring material 5 is patterned, thus shaping fine wirings among each device 2. According to the constitution, mounting with high density is enabled.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〈産業上の利用分野〉 本発明は、基板にグイボンドした複数個のICチップ間
の配線または焦電素子、圧電素子、フォトダイオード等
のチップ状景子と周辺回路との配線に利用できるチップ
状電子素子の配線方法に関するものである。
Detailed Description of the Invention 3. Detailed Description of the Invention <Industrial Application Field> The present invention relates to wiring between a plurality of IC chips bonded to a substrate or chips such as pyroelectric elements, piezoelectric elements, and photodiodes. The present invention relates to a wiring method for a chip-shaped electronic element that can be used for wiring between a state-of-the-art device and a peripheral circuit.

〈従来の技術〉 例えば、複数個のICチップを相互に配線接続する場合
、ウェハからダイシングにより得られたICチップには
、ダイシングによる切断面に微細な凹凸があるため、こ
れらを互いに接合させた時にICチップ間に凹凸による
間隙が生じる。従って、これら各ICチップの表面に配
線材料をデポジションした場合に、各ICチップ間の間
隙によって配線材料が断線してしまう。叩ち、各ICチ
ップ間に直接配線を施してこれらを相互に接続すること
ができない。
<Conventional technology> For example, when interconnecting multiple IC chips, the IC chips obtained by dicing a wafer have minute irregularities on the cut surface caused by the dicing, so it is difficult to bond them together. Occasionally, gaps occur between IC chips due to unevenness. Therefore, when wiring material is deposited on the surface of each of these IC chips, the wiring material will be disconnected due to the gap between each IC chip. It is not possible to connect these IC chips to each other by wiring directly between them.

そこで、ハイブリッドによりICチップを相互に接続し
ている。即ち、配線を施しである基板上にICチップを
グイボンドし、基板上の配線を介して各ICチップ間相
互の接続を行なっている。
Therefore, IC chips are interconnected using a hybrid. That is, IC chips are bonded onto a substrate with wiring, and the IC chips are interconnected via the wiring on the substrate.

〈発明が解決しようとする問題点〉 このようにICチップ間に直接配線を施してこれらを相
互に接続することができないので、チップ状電子素子の
高密度な実装を行なうことができない。しかも、各チッ
プ間の配線長が長くなることにより浮遊容量が増大し、
電気的信頼性に欠けるという欠点がある。
<Problems to be Solved by the Invention> As described above, since it is not possible to interconnect IC chips by directly wiring them, high-density packaging of chip-shaped electronic elements cannot be performed. Moreover, as the wiring length between each chip increases, stray capacitance increases.
The disadvantage is that it lacks electrical reliability.

〈発明の目的〉 本発明は、このような従来の問題点に鑑みなされたもの
で、チップ状電子素子間に直接配線を施してこれらを相
互に電気的接続することのできるチップ状電子素子の配
線方法を提供することを目的とするものである。
<Object of the Invention> The present invention has been made in view of the above-mentioned conventional problems, and it provides a chip-shaped electronic device that can be electrically connected to each other by directly wiring between the chip-shaped electronic devices. The purpose is to provide a wiring method.

〈問題点を解決するための手段〉 本発明のチ・ノブ状電子素子の配線方法によると、互い
に近接して配置した複数個のチップ状電子素子の間隙並
びに各電子素子の表面に、感光性のレジストを塗布し、
このレジストに対し露光した後に現像を行なって前記各
電子素子間のレジストを除く他のレジストを除去し、そ
の後に前記各電子素子の表面および残存レジスト上に配
線材料を付着させるとともに、この配線材料をパターン
ニングして前記各電子素子間の配線を行なう工程を経る
ことを特徴とするものである。
<Means for Solving the Problems> According to the wiring method for chip-shaped electronic devices of the present invention, a photosensitive material is applied to the gaps between a plurality of chip-shaped electronic devices arranged close to each other and the surface of each electronic device. Apply a resist of
After exposing this resist to light, development is performed to remove the resist other than the resist between the electronic elements, and then a wiring material is attached to the surface of each electronic element and the remaining resist, and the wiring material is The method is characterized in that it includes a step of patterning and wiring between the electronic elements.

く作用、〉 前記工程を経て各チップ状電子素子間の配線を施すこと
により、各電子素子間の間隙に充填されたレジストで配
線材料が断線することなく支持され、各電子素子が直接
配線される。
By applying wiring between each chip-shaped electronic element through the above process, the wiring material is supported without disconnection by the resist filled in the gap between each electronic element, and each electronic element can be directly wired. Ru.

〈実施例〉 以下、本発明の実施例を図面に基いて詳細に説明する。<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図乃至第4図は本発明の一実施例の工程を順に示し
た説明図である。第1図に示すように、基板l上に、例
えばICチップからなるチップ状電子素子2をそれぞれ
可及的に近接した状態に配置してダイボンドする。この
時、各電子素子2間に、ダイシングによる各電子素子2
の切断面の凹凸により間隙3が存在する。
FIGS. 1 to 4 are explanatory diagrams sequentially showing the steps of an embodiment of the present invention. As shown in FIG. 1, chip-shaped electronic devices 2 made of, for example, IC chips are arranged as close as possible to each other and die-bonded onto a substrate l. At this time, each electronic element 2 by dicing is placed between each electronic element 2.
A gap 3 exists due to the unevenness of the cut surface.

次に、第2図に示すように、ディプ法またはスピン・コ
ート法を用いて、各電子素子2の表面および各電子素子
2の間隙3つまり全面に、露光部分が剥離するポジ型レ
ジスト4を塗布する。その後に、これらの上面から露光
しする。この露光量は、レジスト4の表面層部分のみが
露光されるように設定されている。
Next, as shown in FIG. 2, using a dip method or a spin coating method, a positive resist 4 whose exposed portions are peeled off is applied to the surface of each electronic element 2 and the gap 3, that is, the entire surface of each electronic element 2. Apply. After that, these are exposed from above. This exposure amount is set so that only the surface layer portion of the resist 4 is exposed.

従って、現像を行なうと、第3図に示すように、ポジ型
レジスト4の露光された部分が剥離して除去され、各電
子素子2の間隙3に充填されたレジスト4のみが残存す
る。即ち、各電子素子2の間隙3に残存するレジスト4
によって間隙3が埋められて各電子素子2間が平坦化さ
れる。ここで、レジスト4の耐環境性が問題となる場合
には、このレジスト4の上面にパッシベーション膜ヲ形
成してもよい。
Therefore, when development is performed, as shown in FIG. 3, the exposed portions of the positive resist 4 are peeled off and removed, leaving only the resist 4 filled in the gaps 3 of each electronic element 2. That is, the resist 4 remaining in the gap 3 between each electronic element 2
The gap 3 is filled and the space between each electronic element 2 is flattened. Here, if the environmental resistance of the resist 4 is a problem, a passivation film may be formed on the upper surface of the resist 4.

そして、第4図に示すように、上面に配線材料をデポジ
ションする。この上面に付着した配線材料5は、各電子
素子2間において平坦化されたレジスト4により恰も支
持される状態となって断線することがない。この配線材
料5を、露光技術を用いてパターンニングすることによ
り、各電子素子2間のWX!III配線ができ、各電子
素子2を互いに電気的接続できる。
Then, as shown in FIG. 4, a wiring material is deposited on the upper surface. The wiring material 5 attached to the upper surface is supported by the flattened resist 4 between each electronic element 2, and is not disconnected. By patterning this wiring material 5 using exposure technology, WX! III wiring is completed, and each electronic element 2 can be electrically connected to each other.

第5図乃至第6図は、本発明の他の実施例を工程順に示
した説明図であり、これらの図において、第1図乃至第
4図と同−若しくは同等のものには同一の符号を付しで
ある。前記第1図乃至第4図の実施例では露光部分が現
像により剥離するポジ型レジスト4を用いたのに対し、
この実施例では、露光部分が現像に対し残存するネガ型
レジスト6を用いた点において前記実施例と相異する。
5 to 6 are explanatory diagrams showing other embodiments of the present invention in the order of steps, and in these figures, the same reference numerals are given to the same or equivalent parts as in FIGS. 1 to 4. It is attached. In the embodiments shown in FIGS. 1 to 4, a positive resist 4 was used in which the exposed portion was peeled off by development.
This embodiment differs from the previous embodiment in that a negative resist 6 whose exposed portions remain after development is used.

叩ち、第5図に示すように、複数個のチップ状電子素子
2を、光透過性材質の基板7上に可及的に近接させた配
置でグイボンドし、第6図に示すように、ネガ型レジス
ト6を塗布した後、基板7側から露光しする。従って、
基板7の透過光により各電子素子2間のレジスト6のみ
感光され、各電子素子2の表面にそれぞれ付着している
レジスト6は、光が電子素子2を透過しないことによっ
て感光されなもく。従って、次に現像を行なった場合、
各電子素子2の表面に付着している未露光部分のレジス
ト6のみが、第7図に示すように剥離除去され、第3図
と同一の状態となる。この時、前記実施例と同様にレジ
スト6の耐環境性が問題となる場合には、レジスト6上
の上面にパフシベーション膜を形成してもよい。
As shown in FIG. 5, a plurality of chip-shaped electronic devices 2 are bonded as close as possible to a substrate 7 made of a light-transmitting material, and as shown in FIG. After applying the negative resist 6, exposure is performed from the substrate 7 side. Therefore,
Only the resist 6 between the electronic elements 2 is exposed by the light transmitted through the substrate 7, and the resist 6 attached to the surface of each electronic element 2 is not exposed because the light does not pass through the electronic element 2. Therefore, when developing next time,
Only the unexposed portions of the resist 6 adhering to the surface of each electronic element 2 are peeled off and removed as shown in FIG. 7, resulting in the same state as in FIG. 3. At this time, if the environmental resistance of the resist 6 is a problem as in the previous embodiment, a puffivation film may be formed on the upper surface of the resist 6.

この後、第8図に示すように、配線材料5を全面に付着
させ、この配線材料5に、露光技術を用いてパターンニ
ングを施すことにより、各電子素子2が相互に接続され
る。
Thereafter, as shown in FIG. 8, a wiring material 5 is deposited on the entire surface, and this wiring material 5 is patterned using an exposure technique, so that the electronic elements 2 are interconnected.

尚、本発明は、前記実施例にのみ限定されるものではな
く、請求の範囲を逸税しない限り種々の実施態様が考え
られるのは勿論であり、例えば、レジスト4.6として
は、前記実施例で用いたポジ型およびネガ型のものに限
らず、感光性の物質であれば前記実施例と同様の効果を
得ることができる。
It should be noted that the present invention is not limited only to the embodiments described above, and it goes without saying that various embodiments can be considered as long as the scope of the claims is not exceeded. It is not limited to the positive type and negative type used in the example, but any photosensitive material can achieve the same effects as in the previous example.

また、前記実施例では、ICチップ相互間の配線を行な
う場合について説明しているけれど、圧電素子、焦電素
子、フォトダイオード等のチップ状電子素子とこれの周
辺回路との間の配線等にも利用できる。
In addition, although the above embodiment describes the case of wiring between IC chips, wiring between chip-shaped electronic elements such as piezoelectric elements, pyroelectric elements, and photodiodes and their peripheral circuits, etc. Also available.

〈発明の効果〉 以上詳述したように本発明のチップ状電子素子の配線方
法によると、各チップ状電子素子間の間隙にレジストを
充填して上面を平坦化した後に、この上面に付着した配
線材料をパターンニングする工程を用いるようにしたの
で、各チップ状電子素子を直接接続する微細配線を行な
うことができ、高密度実装が可能となる。
<Effects of the Invention> As detailed above, according to the wiring method for chip-shaped electronic devices of the present invention, after filling the gaps between each chip-shaped electronic device with resist and flattening the top surface, Since the process of patterning the wiring material is used, it is possible to perform fine wiring that directly connects each chip-shaped electronic element, and high-density packaging is possible.

また、ハイブリッド化してICチップ間に配線を施す場
合に比し各チップ状電子素子間の配線長が格段に短くな
って配線に伴なう浮遊容量が大幅に低減し、この浮遊容
量による問題を解消することができる。
In addition, compared to the case of hybridization and wiring between IC chips, the wiring length between each chip-shaped electronic element is significantly shorter, and the stray capacitance associated with the wiring is significantly reduced, and problems caused by this stray capacitance can be solved. It can be resolved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は本発明のチップ状電子素子の配線方
法の実施に係る一例の工程を順に示した説明図、 第5図乃至第8図は本発明の実施に係る他側の工程を順
に示した説明図である。
1 to 4 are explanatory diagrams sequentially showing steps of an example of implementing the wiring method for a chip-shaped electronic device according to the present invention, and FIGS. 5 to 8 are explanatory diagrams showing the steps of the other side according to the implementation of the present invention. FIG.

Claims (1)

【特許請求の範囲】[Claims] (1)互いに近接して配置した複数個のチップ状電子素
子の間隙並びに各電子素子の表面に、感光性のレジスト
を塗布し、このレジストに対し露光した後に現像を行な
って前記各電子素子間のレジストを除く他のレジストを
除去し、その後に前記各電子素子の表面および残存レジ
スト上に配線材料を付着させるとともに、この配線材料
をパターンニングして前記各電子素子間の配線を行なう
ことを特徴とするチップ状電子素子の配線方法。
(1) A photosensitive resist is applied to the gaps between a plurality of chip-shaped electronic devices arranged close to each other and the surface of each electronic device, and after the resist is exposed to light, development is performed to create a gap between the electronic devices. removing the other resists except for the resist, and then depositing a wiring material on the surface of each of the electronic elements and the remaining resist, and patterning this wiring material to perform wiring between the electronic elements. Features a wiring method for chip-shaped electronic devices.
JP12894786A 1986-06-02 1986-06-02 Wiring method for chip-shaped electronic device Pending JPS62285459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12894786A JPS62285459A (en) 1986-06-02 1986-06-02 Wiring method for chip-shaped electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12894786A JPS62285459A (en) 1986-06-02 1986-06-02 Wiring method for chip-shaped electronic device

Publications (1)

Publication Number Publication Date
JPS62285459A true JPS62285459A (en) 1987-12-11

Family

ID=14997339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12894786A Pending JPS62285459A (en) 1986-06-02 1986-06-02 Wiring method for chip-shaped electronic device

Country Status (1)

Country Link
JP (1) JPS62285459A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198385A (en) * 1991-01-11 1993-03-30 Harris Corporation Photolithographic formation of die-to-package airbridge in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198385A (en) * 1991-01-11 1993-03-30 Harris Corporation Photolithographic formation of die-to-package airbridge in a semiconductor device

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