JPS62285166A - Address control system for microcomputer - Google Patents

Abstract

PURPOSE:To give accesses to plural peripheral elements just with the application of a single pair of addresses by using a flip-flop which holds the priority selection results of the peripheral elements when an interruption is accepted from a microprocessor. CONSTITUTION:In an initial setting mode the reset output 18 is set at '1' by the resetting action of a CPU 1 and flip-flops 4 and 5 are reset together with the outputs of OR circuits 8 and 9 set at '1' respectively. Under such conditions, a CPU 1 gives accesses to the peripheral elements and the port address information 19 is outputted. While the output 20 allocated to peripheral elements 2 and 3 of a decoder 6 are set at '1' and at the same time the outputs of AND circuits 10 and 11 are set at '1'. Thus it is possible to give the accesses to both elements 2 and 3 at a time.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Industrial Field of Application] This invention relates to the control of the input/output coupler addresses of the microprocessor 9 in the sixth section, and is particularly applicable to peripheral elements having a plurality of identical address configurations. The present invention relates to a suitable input/output address control method for use with a computer.

[Conventional technology]

In conventional microprocessors using direct port addressing, there are two methods for controlling a plurality of peripheral elements of the same type.

The first method is to assign an individual address to each peripheral element and control it.

A second method is to allocate a set of addresses to a group of peripheral elements and provide an external selection circuit for control. A related method of this type is, for example, Japanese Patent Application Laid-Open No. 56-92620.

Examples include JP-A-58-114222.

[The problem that the invention attempts to solve]

In the individual addressing method of the prior art described above, the addresses are different for each peripheral element, so the input/output commands are different for each peripheral element.

For this reason, when the number of peripheral elements is large or when the control procedure for the peripheral elements is complicated, the amount of programs increases, and the memory capacity for storing the programs increases.

Further, in the selection circuit method described above, since the address is the same, the increase in the amount of programming is not large, but it is necessary to control the selection circuit before accessing the peripheral elements. This increases control time. Further, in initial setting processing for peripheral elements such as when power is turned on, processing time increases in proportion to the number of peripheral elements.

For this reason, there is a limit when controlling a plurality of peripheral elements each having a limited response time using a limited memory capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a selection circuit that can control a plurality of peripheral elements using the same address without requiring selection processing by a program.

[Means for solving intersimilarities]

For some types of peripheral devices, the purpose of the above is to access the peripheral device from the microprocessor, to initialize the peripheral device at the time of initialization, and to interrupt processing requests from the peripheral device to the microprocessor. Focusing on this, we provided a flip-flop that holds the priority selection result of the peripheral element when accepting an interrupt from the microprocessor, and when the microprocessor accesses the peripheral element, the value is set in the 7 lip and 70 tug. If the peripheral element selection circuit selects only the corresponding peripheral element if the value is set in the flip-flop, and selects all peripheral elements if the value is not set in the flip-flop, then one set of peripheral elements is selected for the peripheral element. This is achieved because only addressing is required and no program processing is required for the selection@path.

[Effect]

In the above address control method, if no value is set in the flip-flop that holds the interrupt priority selection result, all peripheral elements are accessed, but only output operations are performed to set the same content. Since no input operation is performed on peripheral elements, there is no possibility of malfunction. Further, when a value is set in the flip-flop, manual operation and output operation are performed on the peripheral elements, but since only one peripheral element is selected, no malfunction occurs.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is a microprocessor, 2.3 is a peripheral element, 4 and 5 are flip-flops, 6 is a decoder,
7-9 are OR circuits, 10-14 are AND circuits, 15-1
7 each indicate a NOT circuit.

The microprocessor 1 has an interrupt request input terminal I from a peripheral element and an interrupt acceptance response output terminal I to the peripheral element NTR1.
Port address 2 output terminal A to NTA, I'71 side element
DH, and a reset output terminal R8T. An interrupt operation is performed by inputting an interrupt request signal to 1NTR, and outputting an interrupt acceptance response signal INTAK. Access operation to peripheral elements uses boat address information as ADH.
Execute by outputting to . Reset operation is performed by sending the reset signal to R.
By outputting to 3T, 5゜prefecture im general excursion is performed by MicroPro+, 1. It has an input request output terminal INT for input, a select input terminal C8 for access from the microprocessor, and a select input terminal C8. An interrupt operation to the microprocessor is performed by outputting an interrupt request signal to INT.

Access from the microprocessor is possible only when the chip select signal is input to C8.

The present invention is mainly characterized by the address selection method of the peripheral elements, and the other aspects are similar to those of ordinary microprocessors and peripheral elements, so a detailed explanation will be omitted.

Next, the operation of the configuration shown in FIG. 1 will be explained.

First, in the initial setting operation, the reset output 18 becomes 1 due to the reset processing from the microprocessor 1, the flip-flops 4 and 5 are reset, and the outputs of the OR circuits 8 and 9 become 1. When the microprocessor 1 accesses the peripheral elements in this state, the port address information 19 is output, the output 20 assigned to the peripheral elements 2 and 3 of the decoder 6 becomes 1, and the outputs of the AND circuits 10 and 11 become 1. Both become 1. Therefore, access to the peripheral elements is performed to the peripheral elements 2 and 3 at the same time.

Next, in an interrupt operation from a peripheral element, the interrupt request signals 21 and 22 of the peripheral element 2.5 are ORed by the OR circuit 7 and notified to the microprocessor 1.

The microprocessor 1 performs an interrupt operation and sets the interrupt acceptance response signal 23 to 1. Since the AND circuits 12 and 13 have a priority selection logic, the priority selection results of the interrupt requests from the peripheral elements 2 and 3 are set in the flip-flops 4.5, and the outputs of the OR circuits 8 and 9 are the priority selection logic. One of them becomes 1 according to the priority order. When microprocessor 1 accesses peripheral elements in this state, a flip occurs.
Either one of peripheral elements 2, 3 corresponding to the state of flop 4.5 is accessed.

FIG. 2 shows the above operation explanation in a table, showing the relationship between the operation contents, the state of the interrupt selection flip-flop, and access selection to peripheral elements.

〔Effect of the invention〕

According to the present invention, it is possible to access the microprocessor by only assigning one set of addresses to the peripheral elements, which has the effect of reducing the program capacity. Also 1
Since there is no need for selection processing by a program even when assigning a set of addresses, peripheral elements can be accessed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprocessor and peripheral elements according to an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between the operation contents, the state of the interrupt selection holding flip-flop, and the selection state of peripheral element access. 1...Microprocessor, 2.3...Peripheral element, 4.5...Flip frog, 6...Decoder. 1゛+-

Claims (1)

[Claims] 1. In a microcomputer consisting of a microprocessor and multiple peripheral elements of the same type that have an interrupt function for the microprocessor, when an interrupt is received from a peripheral element, priority is given to the peripheral element by an interrupt acceptance response signal from the microprocessor. A flip or flop is provided to hold the selection result, a set of addresses is assigned to a plurality of peripheral elements, and when the microprocessor accesses the peripheral element, if any of the flips or flops is 1, it corresponds. 1. An address control system for a microcomputer, characterized in that only peripheral elements are selected, and when the flips and flops are all 0, all peripheral elements are selected.