JPS62284432A - Data coupling circuit - Google Patents

Abstract

PURPOSE:To attain rapid processing of data coupling operation by executing the data coupling processing like a pipe line even if key values are outputted so as to be overlapped in a data coupling circuit to be used for data base processing or the like. CONSTITUTION:Data of strings A, B are supplied like pipe lines, and at the time of detecting the coincidence of key values, a gate 5 is opened and a coupled data string is outputted to a storage device 6. When the overlap of the key values is detected by a comparator 2, a mode register 4 is set up to an overlap mode and the address of the current string A is saved in the register 3. When the string B is set up as the succeeding data, the string A is read out by the address saved in the register 3 and the comparison of key values is restarted based on the data of the string A.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] A data combination circuit that performs data combination operations in database processing, etc., which includes a comparator that compares key values of two data strings, and one A comparator that detects duplication of key values in a data string, a mode register that indicates when a key value set is restored, and a means for storing a restart address when key value duplication occurs, and data combination processing is performed in a pipeline.

[Industrial Application Field 1] The present invention relates to a data combination circuit used in database processing and the like.

In database processing, etc., the process of creating new data by concatenating data whose designated key field values satisfy conditions from two groups of data strings is called a data join operation.

The present invention relates to speeding up data combination performance.

[Prior Art] Conventionally, data combination operations have been performed using -C commands, character comparison commands,
This was realized in software by combining character transfer commands, etc.

FIG. 3 is a flowchart showing an example of a combination operation process using conventional software.

If the keys used in the join do not have duplicate occurrences of the same value, the process is relatively simple, but! If there is more than one, it becomes complicated.

Next, an example will be described in which the software combination process of FIG. 3 is executed for the two data strings shown in FIG. 4.

Two data strings A and B have been sorted in ascending order according to the keys.

■Key AA of the first data (number AI) of data string A
A and the key AΔ of the first data (number Bl) of data string B
A is compared, and since they match, it branches to the right, and Al-B1
The combined data of is output, the address of A1 is saved,
Data A2 following data A is read out, and the F flag is turned on.

■The key AAB of A2 and the key AAA of Bl are compared, and since they do not match, the next data of B, B2, is read out, and the keys of B1 and 82 are compared. Read out.

■The key AAA of A1 and the key AAA of B2 are compared and since they match, the combined data of At-82 is output and the next data A2 of A is read. ■The key AAB of A2 and the key AAA of 82 are compared. Since they do not match, data B3 next to B is read out, and the keys of B2 and 83 are compared and there is no loss, so the F flag is turned off.

■Since the key AAB of A2 and the key AAB of B3 are compared and match, the combined data of A2-B5 is output, the address of A2 is saved, the data of the next address A3 is read, and the F flag is turned on. be done.

■Since the key ABB of A3 and the key AAB of B3 are compared and do not match, the next data B4 of B is read out, and the keys of B3 and 84 are compared and match, so the address of A2 being saved is recovered and the data is read out.

(2) Since the key AAB of A2 and the key AAB of 84 are compared and match, the combined data of A2-84 is output, and the next data of A, A3, is read out.

Thereafter, a new data string can be created by concatenating data with matching join keys one after another in the same manner. If there are duplicates in the join key values, special processing (not shown) is required to complete the process, but this is omitted here.

[Problems to be Solved by the Invention] There is a limit to the improvement of performance (processing speed) in the method described above, in which data combination operations are executed in software by combining various instructions. The only improvement is the clock rate.

The present invention seeks to provide a novel data combination circuit that overcomes these conventional limitations.

Means for Solving Problem C] FIG. 1 shows a block diagram of the principle of the data combination circuit of the present invention.

In FIG. 1, numeral 1 is a comparator that matches and compares the key values of a first data string (hereinafter referred to as string) A and string B. In FIG.

2 is a comparator that compares key values of successive data of a string on the reference side (here, string B is the reference string).

Reference numeral 3 denotes an address save register that saves the restart address for the string in the duplication mode.

4 is a mode register that stores whether the mode is duplication mode or normal mode.

Reference numeral 5 denotes a gate that outputs combined data when one loss is detected by the comparator l.

6 is a storage device that stores data of each data string.

The data of string A and string B are flown in a pipeline manner, and when a match of key values is detected by comparator 1, gate 5 is opened and a combined data string is output to storage device 6.

When the comparator 2 detects duplication of key values, the mode register 4 enters the duplication mode and saves the address of the current string A in the register 3.

When string B becomes the next data, register.

String A is read out at the address saved in star 3, and key comparison is restarted from that data.

[Operation] With the above configuration, even when key values used for data combination appear repeatedly, data combination processing is performed in a pipeline manner.

In contrast to software-based processing, which is all performed sequentially, various types of processing are performed simultaneously and in parallel. For example, comparing the key values of string A and string B, and comparing the key values of current data and subsequent data of string B,
done in parallel and at the same time.

This makes it possible to process data join operations of data strings with duplicate occurrences of join key values at extremely high speed.

゛[Examples] The present invention will be explained in more detail below with reference to Examples shown in FIGS. 1 and 2.

FIG. 1 is an embodiment block diagram which also serves as a principle block diagram of the present invention.

FIG. 2 is a state transition diagram showing mode transitions in the mode register in the embodiment of the present invention.

In this embodiment, the mode of the mode register 4 shown in FIG. 1 is changed as shown in the state transition diagram of FIG. 2 according to the current mode and the comparison results of comparators 1 and 2, and output of the combined data, as described in
Performs control for updating the current data address, saving the current data address, etc.

The meanings of the symbols used in the following explanation are as follows.

N: Normal mode, D double duplicate mode (data of the subsequent duplicate join key is being processed), A/B: data string sorted in ascending order (
The reference string used to check for duplicate keys is B) d: A value indicating whether the key of the current data of B and the key of the data immediately after are the same, d=l means one loss, d=Q means Indicates a discrepancy. d=X indicates that it may be a match or a mismatch.

e: A value indicating whether the key of the current data of A and the key of the current data of B are the same or not; e=l indicates a match, and e=Q indicates a mismatch.

KA: key of current data of A; KB: key of current data of B; mode transition and processing to be performed are controlled as shown below according to the current mode and the values of d and e.

(1) (mode, d/e) = (N, l/1
) :Mode=D.

Output the combined data of the current data of A and B or the set of identification numbers (10), Save the current data address of A, Update the current data address to .

(2) (mode, d/e) = (N, O/1
): Combined data of A and B's current data or ID0 set output, update of A's current data address.

(3) (mode, d/e) = (N, X10
): If KA<KB, update the current data address of A; if KA>KB, update the current data address of B.

(4) (mode, d/e) = (D, X/1
): Combined data of current data of A and B or output of 10 strings, update of current data address of A.

(5) (mode, d/e) = (D, l10
): Restore the save address to , update the current data address of B.

(6) (mode, d/e) = (D, 010
): Update the current data address of mode ff1N1B.

The state transition diagram in FIG. 2 shows the mode transition, and when the current mode is N mode, d/e is 0/1 and xl
No transition occurs when o, transitions to D mode when 1/1,
Further, when the current mode is D mode, no transition occurs when d/e is Ilo and x/1, and transition to N mode occurs when d/e is 010.

[Advantageous Effects of the Invention 1] As explained above, according to the present invention, it is possible to allow duplication of join keys and process the data join operation of two sorted data columns at high speed, contributing to improvement in data processing efficiency. The effect of doing so is extremely large.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a state B transition diagram showing mode transitions in an embodiment of the present invention, Fig. 3 is a flowchart showing an example of processing by conventional software, and Fig. 4 is data It is a figure which shows the example of a column. In the drawings, 1 is a first comparator, 2 is a second comparator, 3 is an address save register, 4 is a mode register, 5 is a gate means, and 6 is a storage device. Principle block diagram of the present invention Figure 1 State transition 2 showing mode transition in the embodiment of the present invention
Fig. 2 Flowchart showing an example of processing by conventional software Data string A Data string B Partial Diagram showing an example of a number data string Fig. 4

Claims (1)

[Claims] A first comparator (1) that performs a match comparison of key values of two sorted data strings; A second comparator (2) that compares the key values of the following data, and stores the address to restart for duplication processing when the second comparator (2) detects duplication of key values. mode storage means (4) for indicating a processing state when key values overlap; and gate means for combining two data strings when the first comparator (1) detects a match. (5) A data combination circuit characterized in that it is configured to continuously process a data combination operation of two data strings.