JPH05100821A - Priority encoder device - Google Patents

Abstract

PURPOSE:To provide a priority encoder device which can speedily terminate a retrieval processing and which can execute the high speed processing of an instruction in a processing which sequentially retrieves a bit position where '1' is raised and encodes it for input data in n-bit width. CONSTITUTION:A first priority encoder 1a sequentially retrieves the bit position of '1' or '0' from the high-order-side of input data and encodes/outputs it. A second priority encoder 1b retrieves the bit position of initial '1' or '0' and encodes/outputs it. A comparison circuit 3 informs an external circuit of a retrieval processing termination signal when respective encoding outputs in the first and second priority encoders 1a and 1b coincide.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a priority encoder device, and more particularly to a priority encoder device having a function of sequentially searching for bit positions of a specific logical value from the end of search data and performing encoding.

[0002]

2. Description of the Related Art FIG. 8 shows an example of an instruction code for loading or storing a plurality of registers with one instruction in a data processing device such as a microprocessor system. For details of such an instruction code, refer to TRONWARE Vol. 2 (Personal Media, 1990) P. 14-79 “TRON specification chip instruction set”.

The LDM instruction shown in FIG. 8A is an instruction for loading data stored in consecutive memory addresses into a plurality of registers. Source operand is src
It is determined based on the addressing mode designated by s31, and the destination operand is designated by the 16-bit register list 33. An extension 32 of the srcs 31 is inserted between the srcs 31 and the register list 33 as needed.

The STM instruction shown in FIG. 8B is an instruction for storing data stored in a plurality of registers in consecutive memory addresses. The source operand is specified by the 16-bit register list 36, and the destination operand is determined based on the addressing mode specified by the 8-bit dests 34. de
An expansion unit 35 of the dests 34 is inserted between the sts 34 and the register list 36 as needed.

Here, each bit position of the register lists 33 and 36 corresponds to each register number as shown in FIG. 9 (a). In FIG. 9A, Rn represents the register with the register number n. Register list 3
When "1" is set in each bit of 3 and 36, it indicates that the register corresponding to the bit position is loaded or stored, and when "0" is set, the register corresponding to the bit position is loaded, Indicates that the store will not be performed. However, when the addressing mode is stack push with the STM instruction,
As shown in (b), the bit allocation of R0 to R15 is shown in FIG.
This is the opposite of the case (a).

FIG. 4 is a block diagram showing an example of a conventional priority encoder device used for processing the instruction code as shown in FIG. Such a priority encoder device is provided inside a CPU (central processing unit) in a microprocessor system, for example. The priority encoder device shown in FIG. 4 includes a priority encoder 1 and a mask generation circuit 2. For the priority encoder 1, for example, a circuit described in JP-A-64-8437 is used.

FIG. 5 is a block diagram showing a more detailed structure of the priority encoder 1 shown in FIG. 4, and is described in, for example, Japanese Patent Laid-Open No. 64-8437. The priority encoder shown in FIG.
And a lower 2 bit encoding circuit 13 and an upper 2 bit encoding circuit 12. The 0 detection circuit 11 and the upper 2-bit encoding circuit 12 encode 16-bit input data and output the upper 2-bit output offsets Ofofs3, Ofs2. On the other hand, the lower 2 bit encoding circuit 13 encodes the 16-bit input data and outputs the lower 2 bits of the output offset Ofofs.
1, 1, Ofs0 is output. The mask generation circuit 2 shown in FIG. 4 generates a mask signal based on the output offsets Ofofs3 to Ofofs0. This mask signal is fed back to the 0 detection circuit 11 and the lower 2 bit encoding circuit 13 as input offsets Iofs0 to Iofs3. The function and operation of each circuit shown in FIG. 5 are described in detail in Japanese Patent Application Laid-Open No. 64-8437, so the description thereof will be omitted here.

FIG. 6 shows the STM instruction shown in FIG. 8B using the priority encoder device shown in FIG.
It is a figure showing processing performed at each stage when executing pipeline processing in a data processor. It is assumed that the register list 41 shown in FIG. 10 is given as the register list 36, the addressing mode is not stack push, and the bit positions and the register numbers correspond to each other as shown in FIG. 9A. In the register list 41, only the bits corresponding to R5 (register of number 5) and R10 are "1", so that in FIG.
A process of successively performing 10 stores is shown. In FIG. 6, the horizontal axis represents time. Further, consider a case where the reading of the micro instruction, the execution of the operation, and the storage of the operation result in the memory are performed in different stages using pipeline processing.

In the operation execution stage 26, the priority encoder device searches for "1" and transfers the data from the register to the memory data register based on the result. Here, the memory data register is a register for storing data to be transferred to the memory, and the contents of the memory data register are stored in the store stage 2
Stored in memory at 7.

FIG. 7 is a diagram showing only the operation of the priority encoder device shown in FIG. 4 when the data processing device performs the operation shown in FIG.

Hereinafter, with reference to FIGS. 4, 6 and 7,
The processing of the arithmetic execution stage 26 when the conventional priority encoder device is used will be described.

First, in step 1, the priority encoder device retrieves "1" from the upper side of the register list, encodes the offset value "5", and outputs it.
Since the search for "1" was successful, the microinstruction read stage 25 is notified of the continuation of the process.

Next, in step 2, R5 corresponding to the offset value "5" encoded in step 1 is transferred to the memory data register. At the same time, the priority encoder device sets “1” from the upper side of the register list in which the mask generation circuit masks 0 up to bit positions 5.
Is searched, and the offset value “10” is encoded and output. At this time, since the search for "1" has succeeded, the microinstruction read stage 25 is notified of the continuation of the processing.

Next, in step 3, R10 corresponding to the offset value "10" encoded in step 2 is transferred to the memory data register, and the priority encoder apparatus retrieves "1" from the bit position 11. The search fails because "1" does not exist. As a result, the operation execution stage 26 outputs a processing end signal to the microinstruction read stage 25 at the timing 28.
Upon receiving the processing end signal, the microinstruction read stage 25 starts reading out a microinstruction for processing the instruction following the STM instruction.

In the next step 4, since the read microinstruction has no meaning, effective arithmetic processing is not performed.

Then, in step 5, the processing of the instruction following the STM instruction is started.

[0017]

When the conventional priority encoder device is used to process the above-mentioned instruction, the priority encoder device is "1".
Even after all the bit positions with "" have been searched, encoded, and output is completed, a trial is made to search for "1" again, and as a result "1" is not found and the search fails, so the search processing ends. Had to judge. Therefore, the end determination is delayed, and the timing of notifying the external circuit of the end of the search process is delayed.

Therefore, an object of the present invention is to provide a priority encoder device capable of processing an instruction as described above at a high speed by advancing the timing of notifying the external circuit of the end of the search processing as described above. is there.

[0019]

A priority encoder device according to the present invention comprises first and second priority encoders and a comparison circuit. The first priority encoder is n (n is an integer of 2 or more)
The first bit position, which is the first logical value, is searched for from one end of the input data having the bit width, and the search result is encoded into an offset value of a predetermined number of bits and output. The second priority encoder searches the first bit position, which is the first logical value of the input data, from the other end of the input data in the direction opposite to the search direction of the first priority encoder, and determines the search result as a predetermined value. Encodes into offset value of bit number and outputs. The comparison circuit compares the offset value output by the first priority encoder with the offset value output by the second priority encoder, and outputs the comparison result.

[0020]

In the present invention, the first and second priority encoders search for "1" or "0" from both ends of the input data, and when both search results match, the comparison circuit searches the external circuit. The end of processing is notified.
Therefore, unlike the conventional priority encoder device, it is not necessary to perform useless search operation at the end of the search process, the end timing of the search process is advanced, and the instruction can be processed at high speed.

[0021]

1 is a block diagram showing the configuration of a priority encoder device according to an embodiment of the present invention. Figure 1
The priority encoder device shown in (1) includes a first priority encoder 1a, a second priority encoder 1b, a mask generation circuit 2, and a comparison circuit 3. The first and second priority encoders 1a and 1b are provided in parallel and are supplied with input data. The mask generation circuit 2 is provided in association with the first priority encoder 1a. Therefore,
The first priority encoder 1a has a function of masking bits that have already been searched. on the other hand,
The second priority encoder 1b does not have a mask function. In other respects, the first and second priority encoders 1a and 1b have the same function, and the respective configurations can be configured as shown in FIG. 5, for example.

The first priority encoder 1a searches for a "1" bit from one end of the input data, while the second priority encoder 1b moves from the other end of the input data in the opposite direction to the first priority encoder 1a. The first "1" bit is searched for.

The comparison circuit 3 is a circuit for comparing the output encoded by the first priority encoder 1a and the output encoded by the second priority encoder 1b. The mask generation circuit 2 generates a signal for masking up to the previously searched offset value to zero because the bit position once encoded and output is not output again. The first priority encoder 1a searches for the next bit position of "1" for the partially masked data.

FIG. 2 corresponds to FIG. 6 of the conventional example.
When the register list 41 shown in FIG. 10 is given as the register list 36 of the STM instruction shown in FIG. 8B by using the priority encoder device of the present embodiment shown in FIG. It is a figure showing the processing performed in each stage. It is previously checked that all the bits of the register list 36 are not "0", and it is assumed that there is at least one bit which is "1".
Further, the addressing mode is not stack push, but the bit position and the register number correspond to each other as shown in FIG. Since only the bit corresponding to R5 and R10 is "1" in the register list 41 of FIG. 10, FIG. 2 shows the process of continuously storing R5 and R10. In FIG. 2, the horizontal axis represents time. Consider the case where the reading of microinstructions, the execution of operations, and the storage of the operation results in the memory can be performed in different stages using pipeline processing. The micro instruction read stage 60, the operation execution stage 61, and the store stage 62 correspond to the respective stages in FIG.

FIG. 3 is a diagram showing only the operation of the priority encoder device of FIG. 1 when the data processing device having the priority encoder device of FIG. 1 performs the operation of FIG.

The processing of the operation execution stage 61 when the priority encoder device of the present embodiment shown in FIG. 1 is used will be described below with reference to FIGS. 1, 2 and 3.

First, in step 1, the first priority encoder 1a searches for "1" from the upper side of the register list (see FIG. 3), encodes the offset value "5" and outputs it. At this time, the second priority encoder 1b searches for "1" from the lower side of the register list, encodes the offset value "10", and outputs it. The comparison circuit 3 compares the encoded output of the first priority encoder 1a and the encoded output of the second priority encoder 1b, and detects whether they match. At this time, since the encoded outputs of the first and second priority encoders 1a and 1b do not match, the comparison circuit 3 notifies the microinstruction read stage 60 of the continuation of the processing.

Next, in step 2, R5 corresponding to the offset value "5" encoded in step 1 is transferred to the memory data register, and the first priority encoder 1a uses the mask generated by the mask generation circuit 2. "1" is searched from the upper side of the register list in which bit positions up to bit position 5 are masked by a signal, and the offset value "10" is encoded and output. At this time,
The second priority encoder 1b encodes and outputs the offset value "10". The comparison circuit 3 is
The encoded output of the first priority encoder 1a and the encoded output of the second priority encoder 1b are compared to detect whether they match. At this time, since both encoded outputs match, the comparison circuit 3
Outputs a processing end signal to the micro instruction reading stage 60 at timing 63. Upon receiving this processing end signal, the microinstruction read stage 60 ends the processing for the STM instruction and starts reading the microinstruction for processing the instruction following the STM instruction.

Next, in step 3, R10 corresponding to the offset value "10" encoded in step 2 is transferred to the memory data register.

Then, in step 4, the processing of the instruction following the STM instruction is started. As described above, in the priority encoder device of the embodiment shown in FIG. 1, the number of steps required to process the STM instruction is from 4 steps (4 clock cycles) to 3 steps (3) as compared with the conventional priority encoder device shown in FIG. Clock cycles), and data processing is speeded up.

In the above embodiment, the method of zero masking the input data by using the mask generation circuit is used as a method of preventing the bit position once output from being output again. A method of clearing up to the position to zero may be used, or another method may be used.

Further, in the above embodiment, the second priority encoder 1b is shown to stop its operation when the first "1" is searched from the lower side of the register list. However, when the bit width of the register list is long, a mask generation circuit is also provided in the second priority encoder 1b, so that the first and second priority encoders 1a and 1b sequentially have bit positions of "1" from both ends of the register list. May be configured to be searched. In this case, the encoded output of the first priority encoder 1a and the encoded output of the second priority encoder 1b may be different from each other. The search operation of either of the two priority encoders 1a and 1b may be stopped. As described above, in the embodiment in which the first and second priority encoders 1a and 1b sequentially perform the search operation from both ends of the register list, in FIG.
The data processing speed can be further increased as compared with the embodiment shown in FIG.

[0033]

As described above, according to the present invention, in the process of sequentially retrieving and encoding the bit position where "1" is set, for the data of the n-bit width, the input data is reversed. Since two priority encoders that perform a search from the direction are provided and the end of the search is determined by comparing the outputs of the two priority encoders, the end of the processing can be notified to the external circuit at a fast timing. As a result, there is an effect that the processing time can be significantly shortened in the data processing involving continuous bit search.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a priority encoder device according to an embodiment of the present invention.

2 is a diagram showing pipeline processing of an STM instruction using the priority encoder device shown in FIG.

3 is a diagram showing the operation of the priority encoder device shown in FIG. 1. FIG.

FIG. 4 is a block diagram showing an example of a configuration of a conventional priority encoder device.

FIG. 5 is a block diagram showing an example of a configuration of a priority encoder.

6 is a diagram showing pipeline processing of an STM instruction using the conventional priority encoder device shown in FIG.

7 is a diagram showing an operation of the conventional priority encoder device shown in FIG.

FIG. 8 is a diagram showing instruction formats of an LDM instruction and an STM instruction.

FIG. 9 is a diagram showing a correspondence relationship between each bit position in the register list and each register.

FIG. 10 is a diagram showing an example of a register list in an LDM instruction and an STM instruction.

[Explanation of symbols]

 1a 1st priority encoder 1b 2nd priority encoder 2 mask generation circuit 3 comparison circuit

Claims (1)

[Claims] 1. An input data having a bit width of n (n is an integer of 2 or more) is searched for a first bit position having a first logical value from one end thereof, and the search result is offset by a predetermined number of bits. A first priority encoder that encodes and outputs a value, a first bit position that is a first logical value of the input data in a direction opposite to the search direction of the first priority encoder from the other end of the input data And a second priority encoder which outputs the search result by encoding the search result into an offset value having a predetermined number of bits, and the offset value output by the first priority encoder and the second priority encoder. The priority encoder that includes a comparison circuit that compares the offset value and the output result. Apparatus.