JPS62283717A - Driving circuit for capacitive load - Google Patents

Abstract

PURPOSE:To increase a fall speed by a low current consumption, by constituting the titled circuit so that a part of a discharge current is applied to bases of the second and the third transistors for controlling an electric discharge through a current mirror circuit, when a capacitive load is discharged. CONSTITUTION:When an emitter area of an npn transistor N13 is alpha times of an emitter area of an npn transistor n12, and pnp transistors P1, P2 are of the same size, and beta denotes an emitter ground current amplification factor of the npn transistors N12, N13, a discharge current of beta (1+alpha/(1+alpha)) . I1 flows from a capacitive load COL. In this discharge current, a current of beta . alpha/(1+alpha) .I1 is fed back to base of the npn transistors N12, N13, and the discharge current is further increased. This feedback is a positive feedback, and even if a constantcurrent I1 is small, a large discharge current can be made to flow.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Industrial Application] This invention relates to a capacitive load drive circuit that achieves a fast fall speed with a circuit that consumes little steady current. .

[Conventional technology]

FIG. 2 is a diagram showing a conventional circuit in which a capacitive load is driven by a 1-tempole type output circuit in a TTL circuit. In this figure, TIN is an input terminal, Tau
are output terminals, N□ to N4 are N P N I- transistors, CoL is a capacitive load whose capacitance is CL, B is a power supply whose voltage is Vcc, and ■. is a constant current circuit that supplies constant current power.

In this circuit, when the input terminal TIN transitions from low level to high level, NPNI-transistor N + ,
N2 is turned on to discharge the capacitive load CIIL, but this discharge current increases the common emitter current amplification factor of the NPNI transistor N2 by β. Then, β. - Restricted by I. Therefore, the falling speed of the output terminal Tou is β.・It won't be faster than lloL.

[Problem that the invention seeks to solve]

In the conventional circuit as described above, in order to speed up the fall, it is sufficient to increase the value of the constant current I, but the consumption Ti
There was a problem that the flow increased.

The present invention was made to solve these problems, and an object thereof is to obtain a capacitive load drive circuit with low current consumption and a fast falling speed.

[Means for solving problems]

A capacitive load drive circuit according to the present invention includes a first transistor having a base connected to a first input terminal and an emitter connected to ground, to which a pulse input signal is applied, and a connection between the collector of the first transistor and a power supply. a second transistor whose base is connected to the collector of the first transistor, whose emitter is connected to the ground, and a third transistor whose base and emitter are commonly connected to the second transistor.
a fourth transistor whose base is connected to a second input terminal to which a pulse input signal having an inverse relationship with the pulse input signal applied to the first input terminal is applied, and whose emitter is connected to ground; A capacitive load connected between the collector of the transistor and ground, its input connected to the collector of the third transistor, its output connected to the base of the second transistor, and the collector of the second transistor connected to the capacitive property 7iffl. It consists of a current mirror circuit and a fifth transistor for charging a capacitive load via the current mirror circuit, and an output terminal is provided between the current mirror circuit and the capacitive load.

[Effect]

In this invention, when the capacitive load is discharged, a part of the discharge current is applied to the bases of the second and third transistors controlling the discharge through a current mirror circuit,
The collector-emitter current amount of these transistors increases instantaneously.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a capacitive load drive circuit according to the present invention. In this figure, the same reference numerals as in FIG. 2 indicate the same parts, T rNlp T xN2 are the first and second input terminals, N
NPNI transistor 1, which is a transistor of
I. 2 are constant currents 11. A constant current source that supplies I, M is a PNPI, and a Karen L-mirror circuit consisting of transistors P, , P2.

Next, the operation will be explained.

First, consider a case in which the first input terminal T IN 1 changes from a high level to a low level and the second input terminal TtN2 changes from a low level to a high level in a state where the capacitive load C6L is sufficiently charged. At this time, NPN transistor N
, , N, are both on, and the constant current ■ is NPN I
- Supplied to the 6th path of the run restor N12p''13.

Now, the emitter area of NPNI transistor Nll is N
p%r - 0 times the emitter area of transistor NtZ.

PNP) transistors P□ and P2 are the same size, β is N
P N l-transistor N12. If the common emitter current amplification factor is N, , then β (1
+Go-reward T) ・11 discharge current flows. Of this discharge current, β°1+α−
I.

The current of N P N I-transistor N1tpN13
is fed back to the base of the discharge current, further increasing the discharge current. This feedback is positive feedback, and even if the constant current I is small, a large f4 current can flow.

In this circuit, when the discharge of the capacitive load COL is completed and the input terminal T xNt is at a high level, T tN
@ is low level, capacitive load COL is constant current source ■2°N
The current consumption when being charged by the P N l-transistor N□ is a constant current of 11. It is only the sum of 2.

〔Effect of the invention〕

As explained above, the present invention includes a first transistor whose base is connected to a first input terminal to which a pulse input signal is applied, and whose emitter is connected to ground, and a constant current connected between the collector of this first transistor and a power supply. a second transistor having its base connected to the collector of the first transistor and its emitter connected to ground; the second transistor and the base;

a third transistor whose emitters are connected in common;
a fourth transistor having a base connected to a second input terminal and an emitter connected to ground, to which a pulse input signal having an inverse relationship with the pulse input signal applied to the input terminal of the fourth transistor is applied;
a capacitive load connected between the collector of the second transistor and ground; its input connected to the collector of a third transistor; its output connected to the base of the second transistor; It consists of a current mirror circuit connected between the current mirror circuit and a fifth transistor for charging the capacitive load via this current mirror circuit, and an output terminal is provided between the current mirror circuit and the capacitive load. This has the effect of increasing the fall speed with current consumption.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a capacitive load drive circuit according to the present invention, and FIG. 2 is a diagram showing a conventional capacitive load drive circuit. In the figure, Txul and TfNs are the first and second input terminals, T our is the output terminal, and N1□ to N□ are NP terminals.
N + - transistor, C@L is capacitive load, B is power supply,
■. 1p102 is a constant current source, and M is a current mirror circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] a first transistor having a base connected to a first input terminal to which a pulse input signal is applied and an emitter connected to ground; a constant current source connected between the collector of the first transistor and a power supply; and the first transistor. a second transistor whose base is connected to the collector of the transistor and whose emitter is connected to the ground; a third transistor whose base and emitter are commonly connected to the second transistor; and a pulse input applied to the first input terminal. a fourth transistor having a base connected to a second input terminal to which a pulse input signal having an inverse relationship with the signal is applied, and an emitter connected to the ground; and a capacitive transistor connected between the collector of the second transistor and the ground. a load, a current mirror circuit having its input connected to the collector of the third transistor, its output connected to the base of the second transistor, and connected between the collector of the second transistor and the capacitive load; a fifth for charging the capacitive load via a current mirror circuit;
A drive circuit for a capacitive load, comprising a transistor, and an output terminal is provided between the current mirror circuit and the capacitive load.