JPS62283710A - Light receiving circuit - Google Patents

Light receiving circuit

Info

Publication number
JPS62283710A
JPS62283710A JP61126881A JP12688186A JPS62283710A JP S62283710 A JPS62283710 A JP S62283710A JP 61126881 A JP61126881 A JP 61126881A JP 12688186 A JP12688186 A JP 12688186A JP S62283710 A JPS62283710 A JP S62283710A
Authority
JP
Japan
Prior art keywords
circuit
digital
control signal
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61126881A
Other languages
Japanese (ja)
Inventor
Risuke Shimodaira
理輔 下平
Kiyohisa Yamada
山田 規容久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61126881A priority Critical patent/JPS62283710A/en
Publication of JPS62283710A publication Critical patent/JPS62283710A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To realize a complicated non-linear input/output characteristic, which is extremely difficult by an analog circuit, and to execute control with a high accuracy, by providing an A/D converting circuit, a digital processing circuit, and a D/A converting circuit, and generating various control signals at a stage of a digital signal. CONSTITUTION:A digital AGC control signal which has been generated by a digital processing circuit 7 is converted to an analog signal of the correspondent level a D/A converting circuit 8, and thereafter, supplied to a control signal input terminal of an AGC amplifying circuit 3, and controls a gain of this AGC amplifying circuit 3. Also, a digital bias control signal which has been generated by the digital processing circuit 7 is converted to an analog signal of the corresponding level in a D/A converting circuit 9, and thereafter, supplied to a control signal input terminal of a variable bias applying circuit 13, and a bias value of an optical/electric converting element 1 is controlled.Also, a digital reference voltage which has been generated by the digital processor 7 is converted to an analog signal of the corresponding level in a D/A converting circuit 10, and thereafter, supplied to a reference voltage input terminal of a discriminating/reprodecing circuit 4, and its discriminating/reproducing characteristic is controlled.

Description

【発明の詳細な説明】 3、発明の詳細な説明 発明の目的 産業上の利用分野 本発明は、光通信システム内などで使用される光受信回
路に関し、特にディジタル調整制御が行われるAGC回
路に関するものである。
3. Detailed Description of the Invention Object of the Invention Industrial Application Field The present invention relates to an optical receiving circuit used in an optical communication system, and particularly relates to an AGC circuit in which digital adjustment control is performed. It is something.

従来の技術 光通信システム内に設置される光受信回路の典型的なも
のは、第2図に示すように構成されている。この光受信
回路では、受信光信号が光/電変換素子1において受光
レベルに応じたレベルの電気信号に変換され、前置増幅
回路2とAGC増幅回路3で増幅され、識別・再生回路
4に供給される。これと平行して、AGC増幅回路3の
出力のピーク値がピーク検出回路5で検出され、AGC
帰還回路11を経てAGC増幅回路3の利得制御信号入
力端子に供給され、そこの利得が制御される。また、ピ
ーク検出回路5の出力がバイアス帰還回路12を経て可
変バイアス印加回路13のバイアス制御端子に供給され
、ここから光/電変換素子1に印加されるバイアス値が
制御される。
2. Description of the Related Art A typical optical receiving circuit installed in an optical communication system is configured as shown in FIG. In this optical receiving circuit, a received optical signal is converted into an electrical signal of a level corresponding to the received light level by an optical/electrical conversion element 1, amplified by a preamplifier circuit 2 and an AGC amplifier circuit 3, and then sent to an identification/regeneration circuit 4. Supplied. In parallel with this, the peak value of the output of the AGC amplifier circuit 3 is detected by the peak detection circuit 5, and the peak value of the output of the AGC amplifier circuit 3 is detected by the peak detection circuit 5.
The signal is supplied to the gain control signal input terminal of the AGC amplifier circuit 3 via the feedback circuit 11, and its gain is controlled. Further, the output of the peak detection circuit 5 is supplied to a bias control terminal of a variable bias application circuit 13 via a bias feedback circuit 12, and the bias value applied to the photo/electrical conversion element 1 is controlled from there.

これによってAGC増幅回路3の出力振幅が安定化され
、この安定化出力が識別回路4において所定値の基準電
圧と比較され、安定な識別再生が行われる。
As a result, the output amplitude of the AGC amplifier circuit 3 is stabilized, and this stabilized output is compared with a reference voltage of a predetermined value in the identification circuit 4, thereby performing stable identification and reproduction.

発明が解決しようとする問題点 上述した従来の光受信回路では、素子定数や組立作業上
のばらつきを吸収するために、AGC帰還回路11やバ
イアス帰還回路12の特性と、識別・回路の基準電圧の
調整が必要になるが、複雑な非線型の入出力特性を実現
するために多数の可変定数素子の組合せが必要になり、
個々の調整が繁雑になるだけでなく、ある個所の調整が
他の個所の調整に影響を及ぼすため、調整の精度が低下
すると共に、全体の調整作業が極めて煩雑になるという
問題がある。
Problems to be Solved by the Invention In the conventional optical receiving circuit described above, in order to absorb variations in element constants and assembly work, the characteristics of the AGC feedback circuit 11 and the bias feedback circuit 12 and the reference voltage of the identification/circuit are However, in order to realize complex nonlinear input/output characteristics, a large number of variable constant elements must be combined.
Not only does the individual adjustment become complicated, but also the adjustment at one location affects the adjustment at other locations, resulting in a problem in that the accuracy of the adjustment decreases and the overall adjustment work becomes extremely complicated.

発明の構成 問題点を解決するための手段 本発明の光受信回路は、光信号を電気信号に変換する光
/電変換素子、この先/電変換素子に可変バイアス電圧
を印加する可変バイアス印加回路、光/電変換素子の出
力を増幅する前置増幅回路、この前置増幅回路の出力を
増幅するAGC増幅回路、このAGC増幅回路の出力を
識別・再生する識別・再生回路、AGC増幅回路の出力
のピーク値を検出゛するピーク検出回路、このピーク検
出回路の出力をディジタル信号に変換するA/D変換回
路、このA/D変換回路の出力を処理して第1゜第2.
第3のディジタル制御信号を作成するディジタル処理回
路、このディジタル処理回路の第1のディジタル制御信
号をアナログ信号に変換してAGC増幅回路の利得制御
信号入力端子に供給する第1のD/A変換回路、第2の
ディジタル制御信号をアナログ信号に変換して可変バイ
アス印加回路の制御信号入力端子に供給する第2のD/
A変換回路及び第3のディジタル制御信号をアナログ信
号に変換して識別・再生回路の基準電圧入力端子に供給
する第3のD/A変換器を備え、非線型の複雑な調整を
ディジタル処理回路において自由にかつ容易に行うよう
に構成されている。
Configuration of the Invention Means for Solving the Problems The optical receiving circuit of the present invention includes an optical/electrical conversion element that converts an optical signal into an electrical signal, a variable bias application circuit that applies a variable bias voltage to the electrical conversion element, A preamplifier circuit that amplifies the output of the photo/electric conversion element, an AGC amplifier circuit that amplifies the output of this preamplifier circuit, an identification/regeneration circuit that identifies and reproduces the output of this AGC amplifier circuit, and an output of the AGC amplifier circuit. a peak detection circuit that detects the peak value of the peak detection circuit; an A/D conversion circuit that converts the output of this peak detection circuit into a digital signal;
a digital processing circuit that creates a third digital control signal; a first D/A converter that converts the first digital control signal of this digital processing circuit into an analog signal and supplies it to the gain control signal input terminal of the AGC amplifier circuit; a second D/C circuit that converts the second digital control signal into an analog signal and supplies it to a control signal input terminal of the variable bias application circuit;
The digital processing circuit is equipped with an A conversion circuit and a third D/A converter that converts the third digital control signal into an analog signal and supplies it to the reference voltage input terminal of the identification/regeneration circuit. It is designed so that it can be carried out freely and easily.

以下、本発明の作用を実施例と共に詳細に説明する。Hereinafter, the operation of the present invention will be explained in detail together with examples.

実施例 第1図は本発明の一実施例の光受信回路の構成を示すブ
ロック図である。
Embodiment FIG. 1 is a block diagram showing the configuration of an optical receiving circuit according to an embodiment of the present invention.

第1図中、1は光/電変換素子、2は前置増幅回路、3
はAGC増幅回路、4は識別・再生回路、5はピーク検
出回路、6はA/D変換回路、7はディジタル処理回路
、8,9.10はD/A変換回路、13は可変バイアス
印加回路である。
In Figure 1, 1 is a photo/electrical conversion element, 2 is a preamplifier circuit, and 3
is an AGC amplifier circuit, 4 is an identification/regeneration circuit, 5 is a peak detection circuit, 6 is an A/D conversion circuit, 7 is a digital processing circuit, 8, 9.10 is a D/A conversion circuit, and 13 is a variable bias application circuit. It is.

この光受信回路では、受信光信号が光/電変換素子1に
おいて受光レベルに応じたレベルの電気信号に変換され
、前置増幅回路2とAGC増幅回路3で増幅されたのち
、識別・再生回路4に供給される。
In this optical receiving circuit, a received optical signal is converted into an electrical signal of a level corresponding to the received light level by an optical/electrical conversion element 1, amplified by a preamplifier circuit 2 and an AGC amplifier circuit 3, and then an identification/regeneration circuit. 4.

これと平行して、AGC増幅回路3の出力のピーク値が
ピーク検出回路5で検出され、A/D変損回路6におい
て対応のディジタル信号に変換されたのち、ディジタル
処理回路7に供給される。
In parallel with this, the peak value of the output of the AGC amplifier circuit 3 is detected by the peak detection circuit 5, converted into a corresponding digital signal by the A/D conversion circuit 6, and then supplied to the digital processing circuit 7. .

ディジタル処理回路7は、供給されたディジタル形式の
ピーク値を内蔵のプログラムに従って処理し、AGC増
幅回路3を制御するためのディジタルA c c I制
御信号、可変バイアス印加回路13を制御するためのデ
ィジタル・バイアス制御信号及び識別・再生回路4に供
給するディジタル基準電圧を作成する。
The digital processing circuit 7 processes the supplied digital peak value according to a built-in program, and generates a digital A c c I control signal for controlling the AGC amplifier circuit 3 and a digital A c c I control signal for controlling the variable bias application circuit 13 . - Create a bias control signal and a digital reference voltage to be supplied to the identification/regeneration circuit 4.

ディジタル処理回路7で作成されたディジタルAGC制
御信号は、D/A変換回路8において対応のレベルのア
ナログ信号に変換されたのち、AGC増幅回路3の制御
信号入力端子に供給され、このAGC増幅回路3の利得
を制御する。また、ディジタル処理回路7で作成された
ディジタル・バイアス制御信号は、D/A変換回路9に
おいて対応のレベルのアナログ信号に変換されたのち、
可変バイアス印加回路13の制御信号入力端子に供給さ
れ、これによって光/電変換素子1のバイアス値が制御
される。さらに、ディジタル処理装置7で作成されたデ
ィジタル基準電圧は、D/A変換回路10において対応
のレベルのアナログ信号に変換されたのち、識別・再生
回路4の基準電圧入力端子に供給され、その識別・再生
特性を制御する。
The digital AGC control signal created by the digital processing circuit 7 is converted into an analog signal of a corresponding level by the D/A conversion circuit 8, and then supplied to the control signal input terminal of the AGC amplifier circuit 3. Control the gain of 3. Further, the digital bias control signal created by the digital processing circuit 7 is converted into an analog signal of a corresponding level by the D/A conversion circuit 9, and then
The signal is supplied to the control signal input terminal of the variable bias application circuit 13, thereby controlling the bias value of the photo/electrical conversion element 1. Further, the digital reference voltage created by the digital processing device 7 is converted into an analog signal of a corresponding level in the D/A conversion circuit 10, and then supplied to the reference voltage input terminal of the identification/reproduction circuit 4, and the identification・Control playback characteristics.

発明の効果 以上詳細に説明したように、本発明の光受信回路は、A
/D変換回路、ディジタル処理回路、D/A変換回路を
備え、ディジタル信号の段階で各種の制御信号を作成す
る構成であるから、アナログ回路では極めて困難な複雑
な非線型の入出力特性を実現でき、高精度の制御が可能
になる。
Effects of the Invention As explained in detail above, the optical receiving circuit of the present invention has A
It is equipped with a /D conversion circuit, a digital processing circuit, and a D/A conversion circuit, and is configured to create various control signals at the digital signal stage, so it realizes complex nonlinear input/output characteristics that are extremely difficult to achieve with analog circuits. This enables highly accurate control.

また、ディジタル処理装置において、AGC帰還系、バ
イアス帰還系、識別・再生系の3種類の制御信号を集中
的に作成する構成であるから、各系統の制御を相互の連
係を持たせつつ実行することが可能となり、高精度の制
御が実現できる。
In addition, since the digital processing device is configured to centrally create three types of control signals: the AGC feedback system, the bias feedback system, and the identification/reproduction system, the control of each system can be executed while maintaining mutual coordination. This makes it possible to achieve highly accurate control.

特に、光受信回路の主要構成素子の素子定数をパラメー
タとするプログラムをディジタル処理回路に与えておけ
ば、個々の回路について実際の素子定数をデータ入力す
るだけで直ちに調整が終了し、調整工程を実質的に削減
することもできる。
In particular, if a program is given to the digital processing circuit that uses the element constants of the main components of the optical receiver circuit as parameters, adjustment can be completed immediately by simply inputting data of the actual element constants for each circuit, and the adjustment process can be completed quickly. It can also be substantially reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の光受信回路の構成を示すブ
ロック図、第2図は従来の光受信回路の構成を示すブロ
ック図である。 l・・光/電変換素子、2・・前置増幅回路、3・・A
GC増幅回路、4・・識別・再生回路、5・・ピーク検
出回路、6・・A/D変換回路、7・・ディジタル処理
回路、8,9.10・・D/A変換回路、13・・可変
バイアス印加回路。
FIG. 1 is a block diagram showing the configuration of an optical receiving circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional optical receiving circuit. l...Photo/electric conversion element, 2...Preamplifier circuit, 3...A
GC amplifier circuit, 4...Identification/regeneration circuit, 5...Peak detection circuit, 6...A/D conversion circuit, 7...Digital processing circuit, 8,9.10...D/A conversion circuit, 13.・Variable bias application circuit.

Claims (1)

【特許請求の範囲】[Claims] 受信光信号を電気信号に変換する光/電変換素子、この
光/電変換素子に可変バイアスを印加する可変バイアス
印加回路、前記光/電変換素子の出力を増幅する前置増
幅回路、この前置増幅回路の出力を増幅するAGC増幅
回路、このAGC増幅回路の出力を識別・再生する識別
・再生回路、前記AGC増幅回路の出力のピーク値を検
出するピーク検出回路、このピーク検出回路の出力をデ
ィジタル信号に変換するA/D変換回路、このA/D変
換回路の出力を処理して第1、第2、第3のディジタル
制御信号を作成するするディジタル処理回路、このディ
ジタル処理回路の第1のディジタル制御信号をアナログ
信号に変換して前記AGC増幅回路の利得制御信号入力
端子に供給する第1のD/A変換回路、第2のディジタ
ル制御信号をアナログ信号に変換して前記可変バイアス
印加回路の制御信号入力端子に供給する第2のD/A変
換回路及び第3のディジタル制御信号をアナログ信号に
変換して前記識別・再生回路の基準電圧入力端子に供給
する第3のD/A変換器を備えたことを特徴とする光受
信回路。
an optical/electrical conversion element that converts a received optical signal into an electrical signal; a variable bias application circuit that applies a variable bias to the optical/electrical conversion element; a preamplifier circuit that amplifies the output of the optical/electrical conversion element; an AGC amplifier circuit that amplifies the output of the amplifier circuit; an identification/regeneration circuit that identifies and reproduces the output of the AGC amplifier circuit; a peak detection circuit that detects the peak value of the output of the AGC amplifier circuit; and an output of the peak detection circuit. an A/D conversion circuit that converts the output into a digital signal; a digital processing circuit that processes the output of this A/D conversion circuit to create first, second, and third digital control signals; a first D/A conversion circuit that converts the first digital control signal into an analog signal and supplies it to the gain control signal input terminal of the AGC amplifier circuit; a second D/A conversion circuit that supplies the control signal input terminal of the application circuit; and a third D/A conversion circuit that converts the digital control signal into an analog signal and supplies it to the reference voltage input terminal of the identification/reproduction circuit. An optical receiving circuit characterized by comprising an A converter.
JP61126881A 1986-05-30 1986-05-30 Light receiving circuit Pending JPS62283710A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61126881A JPS62283710A (en) 1986-05-30 1986-05-30 Light receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61126881A JPS62283710A (en) 1986-05-30 1986-05-30 Light receiving circuit

Publications (1)

Publication Number Publication Date
JPS62283710A true JPS62283710A (en) 1987-12-09

Family

ID=14946152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61126881A Pending JPS62283710A (en) 1986-05-30 1986-05-30 Light receiving circuit

Country Status (1)

Country Link
JP (1) JPS62283710A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004222291A (en) * 2003-01-10 2004-08-05 Agilent Technol Inc Power saving method for optical fiber device, and laser system and method for adjusting threshold level for signal detection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004222291A (en) * 2003-01-10 2004-08-05 Agilent Technol Inc Power saving method for optical fiber device, and laser system and method for adjusting threshold level for signal detection
JP4527409B2 (en) * 2003-01-10 2010-08-18 アバゴ・テクノロジーズ・ファイバー・アイピー(シンガポール)プライベート・リミテッド Power saving method for optical fiber device and laser system and method for adjusting threshold level for signal detection

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