JPH09116435A - Ad conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a need or amplifiers to not only easily make a circuit into a MOSLSI but also keep AD conversion high-precision. SOLUTION: In this AD conversion circuit, variable resistances VR1 and VR2 is composed of MOSFETs 111 and 112 and to their gate electrodes a gain control signal GCNT is inputted, and a fixed resistance R2 is connected between them to constitute a resistance division circuit 11. First and second voltage followers 4 and 5 are connected to two connection points between variable resistances VR1 and VR2 and the fixed resistance R2, and output voltages are sent to an AD converter in the next sage as reference voltages. Further, a bias is given to an input analog voltage by a bias circuit 6 provided between outputs of first and second voltage followers, and the biased input analog signal is sent to the AD converter 1 in the next stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD conversion circuit having the same function as an AGC (auto gain control) circuit for keeping the signal level of an input analog signal at an optimum value.

[0002]

2. Description of the Related Art When performing digital signal processing, it is a very important step in performing subsequent signal processing to accurately convert an input analog signal into a digital signal. Therefore, normally, an AGC circuit is arranged in the preceding stage of the AD converter, and the amplitude level of the analog signal is automatically controlled before the AD conversion so that the peak value of the input analog signal becomes the maximum value of the digital data. ing. In particular, when performing signal processing related to broadcasting or communication, it is essential to keep the analog signal level within a certain range because loss on the transmission path is expected.

Therefore, an example of an AD conversion circuit having a conventional AGC circuit is shown in FIG. 4 and will be described. In FIG. 4, the AGC circuit 2 is provided before the full flash AD converter 1.
The AGC circuit 2 includes a fixed multiplication amplifier 20 that amplifies an input signal to a fixed multiplication, and a fixed multiplication amplifier 20.
Of the attenuator 21 for attenuating the signal level of the gain control signal GCNT generated in another block.

Further, a resistor R is provided between the power supply voltage VDD and the ground potential.
A resistance divider circuit 3 composed of R1, R2 and R3 is provided, and a voltage follower 4 is connected to the connection point of the resistors R1 and R2, and its output is supplied to the AD converter 1 as the top level TPref of the reference voltage, and the resistor R2 and The voltage follower 5 is connected to the connection point of R3 and its output is supplied to the AD converter 1 as the bottom level BTMref of the reference voltage. Further, a resistor R4 is provided between the top level TPref and the bottom level BTMref of the reference voltage.
And a resistor divider circuit 6 composed of R5 and R5 are connected to form resistors R4 and R5.
The voltage VB at the connection point A of 5 is applied as a bias voltage to the analog signal input via the AGC circuit 2 and the coupling capacitor 10.

As described above, after the signal level of the input analog signal is adjusted by the AGC circuit 2 and the bias voltage is applied, each comparator 7 of the AD converter 1 is processed.
0, ..., 71, 72, 73 are input. The other end of each comparator 70, ..., 71, 72, 73 has a top level TPref and a bottom level BT of the reference voltage.
Each voltage obtained by dividing Mref by the resistance dividing circuit 8 V0, ..., V
m-2, Vm-1, and Vm are supplied, and m (m = 2 n
The result of comparison by the comparators 70, ..., 71, 72, 73 is multiplied by the decoder 9 and n-bit digital data is output.

With the above configuration, as shown in FIG. 5, the maximum analog value within a certain time (time constant that determines the AGC response) becomes the top level TPref of the reference voltage at the AD converter input section. AG so that it becomes equal to the difference of the bottom level BTMref.
C operates to adjust the input analog signal level.

[0007]

With respect to the hardware of the digital signal processing circuit, the MOS process is optimum in that the chip area can be made small, and the AGC circuit and the subsequent digital circuits can be integrated into one chip by the MOS process. If it can be realized, it will become a system-on-chip, and an LSI that is easy to use and has a cost advantage will be completed.

However, the amplifier manufactured by the current MOS process has a drawback in that it cannot obtain a sufficient gain for an AC signal of several MHZ or more above the HF band. Therefore, the amplifier of the AGC circuit is conventionally used. Only the part has been attached externally, or only the AGC circuit part has to be divided into different chips.

[0009]

SUMMARY OF THE INVENTION According to the present invention, first and second variable resistors whose resistance values change according to an input gain control signal, and serially inserted between the first and second variable resistors. And a fixed resistor that forms a resistance division circuit, and the fixed resistor and the first and second variable resistors.
First and second voltage followers each connected to one of the connection points and transmitting the output voltage as a reference voltage; and a bias circuit connected between the outputs of the first and second voltage followers to bias the input analog signal. The AD conversion circuit is configured by an AD converter that AD-converts the biased input analog signal based on the reference voltage to solve the above problem.

Further, according to the present invention, the first and second variable resistors are constituted by MOSFETs for inputting the gain control signal to a gate electrode.

[0011]

1 is a circuit diagram showing the configuration of the present invention, and the same components as those of the conventional example shown in FIG. 4 are designated by the same reference numerals. This configuration differs from the conventional example in that the AGC circuit 2 does not exist and the input analog signal is directly input to the coupling capacitor 10, and that a variable resistor is used instead of the resistor divider circuit 3 using a fixed resistor. The variable reference level generator 12 is realized by adopting the resistance dividing circuit 11 that has been used.

That is, in the resistance division circuit 11, FETs 111 and 112 for inputting the gain control signal GCNT to the gate electrodes are connected instead of the fixed resistances R1 and R3 in the resistance division circuit 3, respectively. The variable resistor VR1 whose resistance value changes according to the gain control signal GCNT.
And VR2. Variable resistors VR1 and VR2
When the resistance value of the reference voltage changes, the top level TPref and the bottom level BTMref of the reference voltage output from the voltage followers 4 and 5 change.

Therefore, as shown in FIG. 2, the input analog voltage is not adjusted by the gain control signal GCNT, but the top level TPref and the bottom level BTMref of the reference voltage are the gain control signal GC.
Adjusted by NT, within a certain time (AG
The reference voltage is adjusted so that the maximum value of the analog value (in the time constant that determines the response of C) becomes equal to the difference between the top level TPref and the bottom level BTMref of the reference voltage. Then, in the AD converter 1 in the next stage, the input analog signal is converted into a digital signal based on the adjusted reference voltage, so that the adjustment result is reflected in the AD conversion result.

Next, an example in which the present invention is applied to a digital audio demodulation circuit for satellite broadcasting is shown in FIG. Currently, satellite audio broadcasting in Japan uses digital audio signals of 5.72.
QPSK modulation is performed on a 72 MHz carrier.
The K modulation signal is input as an input analog signal. Then, the inputted QPSK modulated signal is AD-converted by the AD converter 1, and after conversion, QPSK demodulation is performed by digital processing to obtain the baseband signals I and Q. QP
The SK demodulator 30 is composed of an I detector 31, a Q detector 32, and low-pass filters 33 and 34 connected to the respective detectors. Then, by inputting the baseband signals I and Q to the level sensor 36 via the adder 35,
The signal level of the baseband signal is monitored by this sensor, the result is DA converted by the PWM generator 37, and the output is smoothed by the low pass filter 38 to obtain the gain control signal GCNT.

In this example, the QPSK modulation signal input to the AD converter 1 has different signal levels depending on the state of the transmission path and each channel, and the bit error rate of the demodulated baseband data is usually such a signal. Highly dependent on level fluctuations. However, according to the present invention, the reference level is adjusted even if the input signal level fluctuates, so that the conversion accuracy of the AD converter 1 is suppressed below a certain level, and the error rate of the demodulated baseband data deteriorates. Is prevented.

[0016]

As described above, according to the present invention, the amplification amplifier which has been conventionally required is not required, so that the MOS LSI can be easily realized and the AD conversion can be maintained with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an AD conversion circuit of the present invention.

FIG. 2 is a waveform diagram for explaining the circuit operation of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a waveform diagram for explaining a circuit operation of a conventional example.

FIG. 5 is a circuit diagram showing an example in which the AD conversion circuit of the present invention is applied to a digital demodulation circuit.

[Explanation of symbols]

 1 AD converter 2 AGC circuit 3, 6, 8, 11 Resistance division circuit 4,5 Voltage follower 9 Decoder 10 Coupling capacitor 111, 112 MOSFET 12 Variable reference level generator 20 Amplifier 21 Attenuator 30 QPSK demodulator 31 I detector 32 Q detector 33, 34, 38 Low-pass filter 35 Adder 36 Level sensor 37 PWM generator 70, ..., 71, 72, 73 Comparator

Claims (2)

[Claims] 1. A first variable resistor and a second variable resistor, the resistance values of which are changed by an input gain control signal, and the first variable resistor.
And a fixed resistor that forms a resistance division circuit by being inserted in series between the fixed resistor and the second variable resistor, and is connected to two connection points of the fixed resistor and the first and second variable resistors, respectively, and outputs A first and a second voltage follower for transmitting a voltage as a reference voltage, a bias circuit connected between the outputs of the first and the second voltage follower to bias the input analog signal, and the biased input analog signal And an AD converter that performs AD conversion on the basis of the reference voltage. 2. A MOSF for inputting the gain control signal to a gate electrode of the first and second variable resistors.
The AD according to claim 1, wherein the AD is formed of ET.
Conversion circuit.