JPH08102682A - Apc circuit - Google Patents

Apc circuit

Info

Publication number
JPH08102682A
JPH08102682A JP23908394A JP23908394A JPH08102682A JP H08102682 A JPH08102682 A JP H08102682A JP 23908394 A JP23908394 A JP 23908394A JP 23908394 A JP23908394 A JP 23908394A JP H08102682 A JPH08102682 A JP H08102682A
Authority
JP
Japan
Prior art keywords
circuit
signal
voltage
arithmetic processing
apc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23908394A
Other languages
Japanese (ja)
Inventor
Koji Nakamura
康治 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23908394A priority Critical patent/JPH08102682A/en
Publication of JPH08102682A publication Critical patent/JPH08102682A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Transmitters (AREA)

Abstract

PURPOSE: To obtain an APC circuit capable of reducing circuit space and power consumption by executing arithmetic processing for a reference signal and radio wave voltage by the use of digital values. CONSTITUTION: The output signal level from an RF amplifier circuit 2 for amplifying an RF signal passed through a variable gain amplifier 1 is detected by a detecting circuit 3 and the digital value of the detected voltage and the digital value of a reference signal to be a digital signal are arithmetically processed by an arithmetic processing circuit 7 and obtained APC voltage is fed back to the amplifier 1 to control its gain.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、携帯電話機等に用いら
れるRF信号増幅器のAPC(AutomaticPower Control)
回路に関するものである。
BACKGROUND OF THE INVENTION The present invention relates to an APC (Automatic Power Control) of an RF signal amplifier used in a mobile phone or the like.
It is about circuits.

【0002】[0002]

【従来の技術】図2は従来のAPC回路の構成例であ
り、1は利得可変増幅器、2はRF増幅回路、3は前記
RF増幅回路2の出力信号レベルを検波する検波回路、
4はディジタル信号である基準信号をアナログ信号に変
換するD/A変換器、5は、前記検波回路3および前記
D/A変換器4の出力信号を入力し、その差分を増幅し
た値を出力する演算処理回路である。なお、T1はRF
信号入力端子、T2は基準信号入力端子である。
2. Description of the Related Art FIG. 2 shows a configuration example of a conventional APC circuit, in which 1 is a variable gain amplifier, 2 is an RF amplification circuit, 3 is a detection circuit for detecting the output signal level of the RF amplification circuit 2,
Reference numeral 4 is a D / A converter for converting a reference signal which is a digital signal into an analog signal, and 5 is an input signal of the output signals of the detection circuit 3 and the D / A converter 4, and outputs a value obtained by amplifying the difference. It is an arithmetic processing circuit that does. Note that T 1 is RF
A signal input terminal, T 2 is a reference signal input terminal.

【0003】次にその動作を説明する。まず、RF信号
入力端子T1から入力されたRF信号は利得可変増幅器
1,RF増幅回路2を通り、その出力信号の一部は検波
回路3に入力されてその信号レベルが検波され、検波電
圧として演算処理回路5に取り込まれる。一方、基準信
号入力端子T2から入力され、D/A変換器4にてアナ
ログ信号に変換された基準信号も前記演算処理回路5に
入力されており、この基準信号と前記検波電圧は比較さ
れてその差分が増幅され、APC電圧として出力され
る。このAPC電圧を、前記利得可変増幅器1の制御端
子に帰還することにより、その利得は制御される。以上
の帰還ループによってRF増幅回路2の出力信号レベル
は、規定値に精度良く保持されることになる。
Next, the operation will be described. First, the RF signal input from the RF signal input terminal T 1 passes through the variable gain amplifier 1 and the RF amplification circuit 2, and a part of the output signal thereof is input to the detection circuit 3 to detect the signal level thereof and the detected voltage. Is taken into the arithmetic processing circuit 5. On the other hand, the reference signal input from the reference signal input terminal T 2 and converted into an analog signal by the D / A converter 4 is also input to the arithmetic processing circuit 5, and the reference signal and the detected voltage are compared. The difference is amplified and output as an APC voltage. The gain is controlled by feeding back the APC voltage to the control terminal of the variable gain amplifier 1. With the above feedback loop, the output signal level of the RF amplifier circuit 2 is accurately maintained at the specified value.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このA
PC回路では演算処理をアナログ信号で行うため、ある
程度の大きさのアナログ回路が必要であり、APC回路
使用機器の小型化の支障となるという問題が生じる。ま
た、APC信号生成のための検波回路の検波電圧が0V
付近の電圧値となる場合があるため、演算処理回路の電
源として負電圧が必要となり、その分だけ消費電力が大
きくなるという問題もある。
However, this A
Since the PC circuit performs arithmetic processing with an analog signal, an analog circuit of a certain size is required, which causes a problem of hindering downsizing of equipment using the APC circuit. Also, the detection voltage of the detection circuit for generating the APC signal is 0V.
There is also a problem that a negative voltage is required as a power source of the arithmetic processing circuit because the voltage value may be a voltage value in the vicinity, and power consumption increases correspondingly.

【0005】本発明は、このような従来の問題を解決す
るものであり、回路スペースの小型化および低消費電力
化に寄与するAPC回路を提供することを目的とする。
The present invention solves such conventional problems, and an object thereof is to provide an APC circuit which contributes to downsizing of a circuit space and reduction of power consumption.

【0006】[0006]

【課題を解決するための手段】本発明は、検波回路の出
力にA/D変換器を設けて基準信号と検波電圧とをディ
ジタル値で演算処理し、その演算結果であるAPC電圧
をD/A変換器を介して利得可変増幅器に帰還するよう
にしたものである。
According to the present invention, an A / D converter is provided at the output of a detection circuit, a reference signal and a detection voltage are arithmetically processed by digital values, and the APC voltage which is the arithmetic result is D / D. The feedback is made to the variable gain amplifier via the A converter.

【0007】[0007]

【作用】上記構成により、基準信号と検波電圧とがディ
ジタル値で演算処理されるため、回路スペースが小さく
なるほか、消費電力も少なくなる。
With the above construction, since the reference signal and the detected voltage are processed by digital values, the circuit space is reduced and the power consumption is reduced.

【0008】[0008]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。なお、前記従来の回路と同一の部
分については同一符号を付すものとする。図1は本発明
のAPC回路の一実施例を示す回路構成図であり、図
中、1はAPC電圧によって利得を可変できる利得可変
増幅器、2は前記利得可変増幅器1の出力信号を増幅す
るRF増幅回路、3は前記RF増幅回路2の出力信号レ
ベルを検波する検波回路、6は前記検波回路3で検波さ
れた検波電圧をディジタル値に変換するA/D変換器、
7は基準信号と前記A/D変換器6の出力を取り込み演
算処理する演算処理回路、8は前記演算処理回路7の出
力をアナログ信号に変換するD/A変換器である。な
お、T1はRF信号入力端子、T3は基準信号入力端子で
ある。
An embodiment of the present invention will be described below with reference to the drawings. The same parts as those of the conventional circuit are designated by the same reference numerals. FIG. 1 is a circuit configuration diagram showing an embodiment of an APC circuit of the present invention, in which 1 is a variable gain amplifier whose gain can be varied by the APC voltage, and 2 is an RF which amplifies the output signal of the variable gain amplifier 1. An amplifier circuit 3, a detection circuit for detecting the output signal level of the RF amplification circuit 2, 6 is an A / D converter for converting the detection voltage detected by the detection circuit 3 into a digital value,
Reference numeral 7 is an arithmetic processing circuit that takes in a reference signal and the output of the A / D converter 6 to perform arithmetic processing, and 8 is a D / A converter that converts the output of the arithmetic processing circuit 7 into an analog signal. Note that T 1 is an RF signal input terminal and T 3 is a reference signal input terminal.

【0009】次にその動作を説明する。まず、RF信号
入力端子T1から入力されたRF信号は利得可変増幅器
1,RF増幅回路2を通り、その出力信号の一部は検波
回路3に入力されて信号レベルが検波され、その検波電
圧は直ちにA/D変換器6によりディジタル値に変換さ
れる。このディジタル値に変換された検波電圧と、基準
信号入力端子T3から入力された元々ディジタル信号で
ある基準信号は、演算処理回路7に取り込まれ、ディジ
タル値のまま演算処理される。演算処理された結果は、
D/A変換器8にてアナログ信号に変換され、APC電
圧として利得可変増幅器1に帰還され、その利得を制御
する。
Next, the operation will be described. First, the RF signal input from the RF signal input terminal T 1 passes through the variable gain amplifier 1 and the RF amplification circuit 2, and a part of the output signal is input to the detection circuit 3 whose signal level is detected and its detection voltage. Is immediately converted into a digital value by the A / D converter 6. The detection voltage converted into the digital value and the reference signal which is originally a digital signal input from the reference signal input terminal T 3 are taken into the arithmetic processing circuit 7 and are arithmetically processed as the digital value. The result of the arithmetic processing is
It is converted into an analog signal by the D / A converter 8 and fed back to the variable gain amplifier 1 as an APC voltage to control its gain.

【0010】このように、演算処理をディジタル値で行
うことによって、演算処理回路7を、例えば他のディジ
タル制御回路ICに統合でき、回路をより高集積化しや
すくなる。また、演算処理回路7に負電源の必要性がな
くなるため、低消費電力化に寄与できる。
As described above, by performing the arithmetic processing with a digital value, the arithmetic processing circuit 7 can be integrated with, for example, another digital control circuit IC, and the circuit can be easily highly integrated. Further, since the arithmetic processing circuit 7 does not need a negative power source, it can contribute to lower power consumption.

【0011】[0011]

【発明の効果】本発明は、上記実施例から明らかなよう
に、演算処理をディジタル値で行うことによって、演算
処理回路を、例えば他のディジタル制御回路ICに統合
でき、回路をより高集積化しやすくなるので回路スペー
スの小型化を図ることができ、また演算処理回路に負電
源の必要性がなくなるため、低消費電力化にも寄与でき
るという効果がある。
As is apparent from the above embodiments, the present invention makes it possible to integrate an arithmetic processing circuit with, for example, another digital control circuit IC by performing arithmetic processing with a digital value, and the circuit is highly integrated. Since it becomes easier, the circuit space can be downsized, and the need for a negative power supply in the arithmetic processing circuit is eliminated, which can contribute to lower power consumption.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のAPC回路の一実施例を示す回路構成
図である。
FIG. 1 is a circuit configuration diagram showing an embodiment of an APC circuit of the present invention.

【図2】従来のAPC回路の一例を示す回路構成図であ
る。
FIG. 2 is a circuit configuration diagram showing an example of a conventional APC circuit.

【符号の説明】[Explanation of symbols]

1…利得可変増幅器、 2…RF増幅回路、 3…検波
回路、 4,8…D/A変換器、 5,7…演算処理回
路、 6…A/D変換器、 T1…RF信号入力端子、
2,T3…基準信号入力端子。
1 ... variable gain amplifier, 2 ... RF amplifier, 3 ... detector, 4, 8 ... D / A converter, 5,7 ... processing circuit, 6 ... A / D converter, T 1 ... RF signal input terminal ,
T 2 , T 3 ... Reference signal input terminals.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 RF信号を入力とし、制御電圧により利
得制御される利得可変増幅器と、前記利得可変増幅器の
出力信号を増幅し、RF信号を出力するRF増幅回路
と、前記RF増幅回路の出力信号レベルを検波する検波
回路と、前記検波回路の出力電圧を特定のタイミングで
A/D変換するA/D変換器と、前記A/D変換器出力
信号および基準信号を入力し、演算処理する演算処理回
路と、前記演算処理回路の出力として得られるAPC電
圧をD/A変換するD/A変換器とを備え、前記D/A
変換器より出力されるAPC電圧を前記利得可変増幅器
に帰還することを特徴とするAPC回路。
1. A variable gain amplifier which receives an RF signal as an input and whose gain is controlled by a control voltage, an RF amplifier circuit which amplifies an output signal of the variable gain amplifier and outputs an RF signal, and an output of the RF amplifier circuit. A detection circuit for detecting a signal level, an A / D converter for A / D converting an output voltage of the detection circuit at a specific timing, an output signal of the A / D converter and a reference signal are inputted and arithmetically processed. The D / A converter includes an arithmetic processing circuit and a D / A converter for D / A converting an APC voltage obtained as an output of the arithmetic processing circuit.
An APC circuit which feeds back an APC voltage output from a converter to the variable gain amplifier.
JP23908394A 1994-10-03 1994-10-03 Apc circuit Pending JPH08102682A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23908394A JPH08102682A (en) 1994-10-03 1994-10-03 Apc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23908394A JPH08102682A (en) 1994-10-03 1994-10-03 Apc circuit

Publications (1)

Publication Number Publication Date
JPH08102682A true JPH08102682A (en) 1996-04-16

Family

ID=17039579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23908394A Pending JPH08102682A (en) 1994-10-03 1994-10-03 Apc circuit

Country Status (1)

Country Link
JP (1) JPH08102682A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003009481A1 (en) * 2001-07-17 2003-01-30 Mitsubishi Denki Kabushiki Kaisha Transmission power control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003009481A1 (en) * 2001-07-17 2003-01-30 Mitsubishi Denki Kabushiki Kaisha Transmission power control circuit
US6788138B2 (en) 2001-07-17 2004-09-07 Mitsubishi Denki Kabushiki Kaisha Transmission power control circuit

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