JPS622835Y2 - - Google Patents

Info

Publication number
JPS622835Y2
JPS622835Y2 JP12538381U JP12538381U JPS622835Y2 JP S622835 Y2 JPS622835 Y2 JP S622835Y2 JP 12538381 U JP12538381 U JP 12538381U JP 12538381 U JP12538381 U JP 12538381U JP S622835 Y2 JPS622835 Y2 JP S622835Y2
Authority
JP
Japan
Prior art keywords
voltage dividing
resistor
power supply
dividing resistors
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12538381U
Other languages
Japanese (ja)
Other versions
JPS5830338U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12538381U priority Critical patent/JPS5830338U/en
Publication of JPS5830338U publication Critical patent/JPS5830338U/en
Application granted granted Critical
Publication of JPS622835Y2 publication Critical patent/JPS622835Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は、マルチプレクサ用駆動回路の改良に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a multiplexer drive circuit.

電効効果トランジスタ(以下FET)をスイツ
チ素子として用いたマルチプレクサの従来例とし
て、第1図のようなものがある。第1図におい
て、Q11,Q21,…Qo1は、複数の信号e1,e2,…
oの経路にそれぞれ直列に設けられたFETであ
つて、それぞれトランジスタQ12,Q22,…Qo2
よびインバータI1,I2,…Ioからなる駆動回路に
よつて駆動されて、それぞれの信号経路を断続す
るようになつている。各FETQi1(i=1〜n)
はデプレツシヨン型のものであり、そのゲートは
抵抗Ri1によつてソースに接続されるとともに、
ダイオードDiとキヤパシタCiの並列回路を通じ
て、それぞれの駆動回路の出力端に接続されるよ
うになつている。駆動回路は、オープンコレクタ
型のインバータIiとトランジスタQi2の縦続接続
からなるものであり、前段のインバータIiをマ
ルチプレクサ制御信号によつてオンにすることに
より、トランジスタQi2をオンにして、それまで
電圧V2側にあつてダイオードDiを順バイアスし
ていたコレクタ電位を、反対の電圧V1側に変位
させてダイオードDiを逆バイアスするようにな
つている。FETQi1はデプレツシヨン型なので、
ダイオードDiのバイアスの順および逆によつ
て、それぞれオフおよびオンとなる。各駆動回路
は、所定のタイミングで順次に動作して各FET
を一時に1つずつオンにする。
A conventional example of a multiplexer using a field effect transistor (hereinafter referred to as FET) as a switch element is shown in FIG. In FIG. 1, Q 11 , Q 21 , . . . Q o1 represent a plurality of signals e 1 , e 2 , .
These FETs are respectively provided in series in the paths of e o , and are driven by drive circuits consisting of transistors Q 12 , Q 22 , ...Q o2 and inverters I 1 , I 2 , ... I o , respectively. The signal path is designed to be intermittent. Each FETQi 1 (i=1~n)
is of the depletion type, its gate is connected to the source by a resistor Ri 1 , and
It is connected to the output end of each drive circuit through a parallel circuit of a diode D i and a capacitor C i . The drive circuit consists of an open collector type inverter I i and a transistor Qi 2 connected in cascade, and by turning on the previous stage inverter I i by a multiplexer control signal, the transistor Qi 2 is turned on. The collector potential, which had been on the voltage V2 side and forward biased the diode D i , is shifted to the opposite voltage V1 side, thereby reverse biasing the diode D i . FETQi 1 is a depletion type, so
Depending on the order and reverse of the bias of the diode D i , it is turned off and on, respectively. Each drive circuit operates sequentially at a predetermined timing to drive each FET.
Turn on one at a time.

このような従来のマルチプレクサにおいて、駆
動回路のトランジスタQi2は、飽和駆動されてス
イツチング動作をするので、そのストレージの影
響で高速のマルチプレクシングをすることができ
ない。その対策の1つとしては、トランジスタQ
i22に、別にストレージ吸収用のトランジスタを
組合わせることが考えられるが、トランジスタQ
i22は、マルチプレクサの信号点数と同じだけあ
るので、それらに組合わせるストレージ吸収用ト
ランジスタも同じ数だけ必要になり、経済的でな
い。
In such a conventional multiplexer, the transistor Qi 2 of the drive circuit is driven to saturation and performs a switching operation, so high-speed multiplexing cannot be performed due to its storage. One of the countermeasures is the transistor Q
It is possible to combine i22 with a separate transistor for storage absorption, but transistor Q
Since there are the same number of i22 as the number of signal points of the multiplexer, the same number of storage absorption transistors to be combined with them are also required, which is not economical.

また、第1図の回路は、駆動回路の故障などに
より、複数のトランジスタが同時にオンになる
と、オンになつた数に比例して、駆動回路の消費
電流がふえて、電力損失が増加する欠点がある。
Additionally, the circuit shown in Figure 1 has the disadvantage that if multiple transistors are turned on at the same time due to a failure in the drive circuit, the current consumption of the drive circuit increases in proportion to the number of transistors turned on, resulting in an increase in power loss. There is.

本考案の目的は、簡単な回路構成で、マルチプ
レクシングの高速化と、同時オン時の電力損失の
増加防止とを果すマルチプレクサ用駆動回路を提
供することにある。
An object of the present invention is to provide a multiplexer drive circuit that has a simple circuit configuration and achieves high-speed multiplexing and prevents increase in power loss when turned on simultaneously.

本考案は、全駆動回路のトランジスタのエミツ
タに共通のエミツタ抵抗を設けてこのエミツタ抵
抗の電圧降下による負帰還作用を利用して、トラ
ンジスタを定電流動作させるとともに、同時オン
時の電源電流瑠の制御をも行うようにしたもので
ある。
In this invention, a common emitter resistor is provided at the emitters of the transistors in all the drive circuits, and by utilizing the negative feedback effect caused by the voltage drop of this emitter resistor, the transistors are operated at a constant current, and the power supply current when turned on at the same time is It is also designed to perform control.

以下、図面によつて本考案を詳細に説明する。
第2図は、本考案実施例の電気的接続図である。
第2図において、第1図と同様な部分には同一の
記号を付けてある。第1図と異なるところは、各
駆動回路のトランジスタQi22のエミツタが、共
通の抵抗R2によつて電源電圧V1の印加点に接続
されていることと、トランジスタQi22のベース
が、その前段のインバータIiの出力プルアツプ
抵抗の分割点に接続されていることである。
Hereinafter, the present invention will be explained in detail with reference to the drawings.
FIG. 2 is an electrical connection diagram of the embodiment of the present invention.
In FIG. 2, parts similar to those in FIG. 1 are given the same symbols. The difference from Fig. 1 is that the emitter of the transistor Q i22 of each drive circuit is connected to the application point of the power supply voltage V 1 by a common resistor R 2 , and the base of the transistor Q i22 is It is connected to the dividing point of the output pull-up resistor of the inverter I i in the previous stage.

このように構成された回路において、例えば、
第1の駆動回路のインバータI1が駆動されてオン
になると、その出力プルアツプ抵抗の他端がコモ
ン点に接続されることにより、電圧V1の分圧値
がトランジスタQ12のベースにバイアス電圧とし
て与えられる。このためトランジスタQ12は導通
して出力電流を生じるが、抵抗R2の電圧降下に
よる負帰還作用があるため、抵抗R2の電圧降下
がベースのバイアス電圧にほぼ等しくなる点で平
衝に達し、出力電流が一定化される。この出力電
流がコレクタ抵抗を流れてその電圧降下が増加す
ることにより、ダイオードD1が逆バイアスさ
れ、FETQ11がオンとなり信号e1の経路が開く。
In a circuit configured in this way, for example,
When the inverter I1 of the first drive circuit is driven and turned on, the other end of its output pull-up resistor is connected to the common point, so that the divided value of the voltage V1 is applied to the base of the transistor Q12 as a bias voltage. given as. Therefore, transistor Q 12 conducts and produces an output current, but due to the negative feedback effect due to the voltage drop across resistor R 2 , equilibrium is reached at the point where the voltage drop across resistor R 2 is approximately equal to the base bias voltage. , the output current is made constant. As this output current flows through the collector resistor and its voltage drop increases, diode D1 is reverse biased, FETQ11 is turned on, and a path for signal e1 is opened.

トランジスタQ12は、抵抗R2の負帰還作用によ
つて不飽和動作をするので、ストレージ効果を生
じることがなく、したがつて高速のマルチプレク
シングが行える。他の駆動回路の出力トランジス
タも同様な動作をする。
Since the transistor Q12 operates in an unsaturated state due to the negative feedback effect of the resistor R2 , no storage effect occurs, and therefore high-speed multiplexing can be performed. The output transistors of other drive circuits also operate in a similar manner.

抵抗R2は全トランジスタに共通なので、何ら
かの理由で、複数のトランジスタが同時にオンに
なつても、それらトランジスタの電流の総和は、
トランジスタが1つだけ導通したときと同じ一定
値になるので、電力損失がふえるということがな
い。
Since the resistor R 2 is common to all transistors, even if multiple transistors are turned on at the same time for some reason, the sum of the currents of those transistors is
Since the value is the same as when only one transistor is conductive, power loss does not increase.

以上のように、本考案は、全駆動回路のトラン
ジスタのエミツタに共通のエミツタ抵抗を設け
て、このエミツタ抵抗の電圧降下による負帰還作
用を利用して、トランジスタを定電流動作させる
とともに、同時オン時の電源電流の制限をも行う
ようにした。このため、本考案によれば、簡単な
回路構成で、マルチプレクシングの高速化と、同
時オン時の電力損失の増加防止とを果すマルチプ
レクサ用駆動回路が実現できる。
As described above, the present invention provides a common emitter resistor to the emitters of the transistors in all drive circuits, and utilizes the negative feedback effect due to the voltage drop of this emitter resistor to operate the transistors at a constant current and turn them on at the same time. It also limits the power supply current. Therefore, according to the present invention, with a simple circuit configuration, it is possible to realize a multiplexer drive circuit that achieves high-speed multiplexing and prevents increase in power loss when simultaneously turned on.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来のマルチプレクサの電気的接続
図、第2図は、本考案実施例の電気的接続図であ
る。 Qi21……電効果トランジスタ、Ri1……抵抗、
i……ダイオード、Ci……キヤパシタ、Qi22
……トランジスタ、Ii……インバータ、R2……
抵抗。
FIG. 1 is an electrical connection diagram of a conventional multiplexer, and FIG. 2 is an electrical connection diagram of an embodiment of the present invention. Q i21 ... field effect transistor, Ri 1 ... resistance,
D i ... diode, C i ... capacitor, Q i22
...transistor, I i ...inverter, R 2 ...
resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電源の一方の端子に一端が接続された共通抵
抗、電源の一方の端子に一端が接続された複数の
分圧抵抗、これら分圧抵抗と対にして設けられマ
ルチプレクサ制御信号に従つて動作して対の分圧
抵抗の分圧抵抗の他端をそれぞれ電源電圧のコモ
ン点に接続する複数のオープンコレクタ型のイン
バータ、および、前記複数の分圧抵抗と対にして
設けられ対の分圧抵抗の分圧点にベースがそれぞ
れ接続され前記共通抵抗の他端にエミツタが接続
されコレクタがそれぞれの抵抗を通じて電源の他
方の端子に接続されコレクタの電位をマルチプレ
クサ駆動信号として出力する複数のトランジスタ
を具備するマルチプレクサ駆動回路。
A common resistor with one end connected to one terminal of the power supply, a plurality of voltage dividing resistors having one end connected to one terminal of the power supply, and a plurality of voltage dividing resistors provided in pairs with these voltage dividing resistors and operated according to a multiplexer control signal. A plurality of open collector inverters each having the other end of the voltage dividing resistor connected to a common point of the power supply voltage, and a pair of voltage dividing resistors provided in pairs with the plural voltage dividing resistors. A plurality of transistors each having a base connected to a voltage dividing point, an emitter connected to the other end of the common resistor, a collector connected to the other terminal of the power supply through each resistor, and outputting the potential of the collector as a multiplexer drive signal. Multiplexer drive circuit.
JP12538381U 1981-08-25 1981-08-25 multiplexer drive circuit Granted JPS5830338U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12538381U JPS5830338U (en) 1981-08-25 1981-08-25 multiplexer drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12538381U JPS5830338U (en) 1981-08-25 1981-08-25 multiplexer drive circuit

Publications (2)

Publication Number Publication Date
JPS5830338U JPS5830338U (en) 1983-02-28
JPS622835Y2 true JPS622835Y2 (en) 1987-01-22

Family

ID=29919225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12538381U Granted JPS5830338U (en) 1981-08-25 1981-08-25 multiplexer drive circuit

Country Status (1)

Country Link
JP (1) JPS5830338U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3334735A1 (en) * 1983-09-26 1985-04-18 Gerhard Prof. Dr.-Ing. 8012 Ottobrunn Flachenecker DETECTOR FOR DISPLAYING MULTIPLE-WAY RECEPTION ERRORS

Also Published As

Publication number Publication date
JPS5830338U (en) 1983-02-28

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