JP2591320B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit configured as an analog switch circuit.

[Conventional technology]

As shown in FIG. 3, an example of a semiconductor integrated circuit constituting a conventional analog switch circuit is a transistor integrated circuit.
Forming a voltage follower circuit, including a differential pair consisting of Q ₁₁ , Q ₁₂ and transistors Q ₉ , Q ₁₀ and resistors 11, 12, including an active load connected to the collector of the differential pair. I have. Then, the operating current of the voltage follower circuit, from the constant current source 13, is supplied through the current switch by a differential pair composed of transistors Q _13, Q _14. Also, the other output of the current switch is connected to a connection point between the emitter and the resistor 12 of the output-side current source transistor Q ₁₀ of the voltage follower circuit. The conventional example shown in FIG.
As an example, this is an example of a circuit when used for a sample-and-hold switch, and a hold capacitor 14 is connected to an output terminal 65. During the sampling period (when the switch is turned on and the input signal of terminal 61 is transmitted to output terminal 62 in a similar manner), the voltage follower circuit is turned on so that the terminal is turned on.
Control signals are applied to 62 and 63. The current of the constant current source 13 is set to I ₀
Expressed and, in the turned-on voltage follower circuit, by performing feedback via an active load, performs charge and discharge by the driving currents up to I _0, with respect to a wide range of input voltage, terminal a small output of the offset amount
Can be obtained from 65. Hold (the switch is turned off and the charge in the hold capacitor 14 is held)
In the period, a control signal is applied to terminals 62 and 63 so that the operating current of the voltage follower circuit is turned off.
Current switch is switched, first pull the current I ₀ from the resistor 12, the base-emitter is reverse biased, the transistor Q ₁₀ is turned off. In the step of operating current decreases sufficiently, transistor Q ₁₂ becomes a high impedance, the output terminal 65 as seen from the hold capacitor 14 becomes high impedance.

[Problems to be solved by the invention]

Since the conventional analog switch circuit described above employs a configuration in which the voltage follower circuit of the active load drives the output,
The driving capability is determined by the current of the constant current source 13, and if the driving capability is to be improved without changing the load, there is a disadvantage that the steady current consumption increases and it is difficult to reduce the power consumption. . Also, if the switching of the current switch is insufficient during the hold period and a small amount of operating current of the voltage follower circuit is supplied, the output does not become high impedance, the voltage follower circuit continues to operate, and the waveform There is a drawback that the hold operation becomes incomplete, for example, an abnormality such as sag occurs.

[Means for solving the problem]

The semiconductor integrated circuit of the present invention transmits a signal similar to the input signal to the output terminal when the level of the predetermined control signal is “ON”, and the level of the control signal is “OFF”.
In the state, in the semiconductor integrated circuit configured as an analog switch circuit having a function of making the output terminal high impedance, an emitter follower is formed as the analog switch circuit,
An output buffer circuit composed of first and second transistors of different conductivity types, whose emitters are connected to each other, and a series connection between the bases of the first and second transistors, respectively, and a forward bias And third and fourth diodes acting to reverse bias, and corresponding to the "on" and "off" states of the control signal, Current switching means for switching the direction of current flowing into the first and second diodes and the third and fourth diodes.

〔Example〕

Next, the present invention will be described with reference to the drawings. First
FIG. 2 is a circuit diagram of the first embodiment of the present invention. As shown in FIG. 1, this embodiment includes a signal input terminal 51, switching control terminals 52 and 53, a power supply terminal 54, and an output terminal 55.
Corresponding to the constant current sources 1 to 4 and the transistors Q _{1 to} Q
₅ and diodes D _{1 to} D ₅ and a hold capacitor 5.

In FIG. 1, with different conductivity types, each of which forms an emitter follower, constituting the output buffer by the transistor Q ₄ and Q ₅ having an emitter connected to one another. In a direction to bias the transistor Q _4, Q ₅ in the opposite direction, diodes D ₃ and D ₄ are connected in series. Each series-connected diodes D ₁ and D ₂ of the connection point, of the connection point and D ₃ and D _4, the output of the input buffer circuit comprising an emitter-follower of the constant current source 1 and the transistor Q ₁ is connected. The constant current sources 2 and 3 are connected to the two outputs of the differential amplifier including the transistors Q ₂ and Q ₃ and the constant current source 4, respectively. The current output terminals are connected to the bases of the transistors Q ₄ and Q ₅ . Connected to each other.

Next, an operation when the switch is used as a sample-and-hold switch, as in the conventional example, will be described.

Here, it is assumed that when the current of the constant current source 4 is 2I ₀ , the currents of 2 and 3 are respectively I ₀ .

First, in the sampling (switch on) period, the control terminal 52 and 53, control signals V ₅₂ and V ₅₃ are applied, respectively. If V ₅₂ <V ₅₃ , transistor Q ₃
But on, Q ₂ is turned off, current I ₀ of the constant current source 2 through the diodes D _1, D _2, and joins the current I ₀ of the constant current source 3 flows into the collector of the transistor Q _3. As a result, the bases of the transistors Q ₄ and Q ₅ are forward-biased, and a voltage lower than the input voltage of the terminal 51 by the base-emitter voltage (hereinafter, referred to as V _BE ) of the transistor Q ₁ appears in the hold capacitor 5. Then, charging and discharging are performed.

In the present embodiment, the factor that limits the charge / discharge current is the rate of change of the base voltage of the transistors Q ₄ and Q ₅ .
With respect to the base voltage which draws a charge / discharge curve such as a junction capacitance or a substrate capacitance of a transistor and a diode connected to the base line, ΔV _B / Δt (where Δt
Is a sufficiently short time from a certain moment, ΔV _B is a change of the base voltage at Δt).
The rate of change of the emitter voltage of the transistor through which the charge / discharge current flows does not exceed the rate of change of its base voltage, and becomes almost equal except for a short period between the start and end of charge / discharge.

Therefore, assuming that the capacitance value of the hold capacitor 5 is C _H (F), the charge / discharge current i is substantially Therefore, the charge / discharge current i is Is represented as Here, ΔQ is the charge / discharge charge at Δt.

Next, during the hold (switch off) period,
A control signal _satisfying V ₅₂ > V ₅₃ is applied to the control terminals 52 and 53, a reverse bias is applied between the bases of the transistors Q ₄ and Q ₅ , and the transistors Q ₄ and Q ₅ are turned off. This circuit viewed from the output side is high
It becomes impedance and the voltage of the hold capacitor 5 is held. However, a change in the input signal during the hold period limits that either Q ₄ or Q ₅ does not turn on, and if these transistors are off, almost no current flows in the output buffer circuit. Absent.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. This embodiment is different from the first embodiment in that the npn-type transistor Q ₁ ,
Q ₂ and Q ₃ are replaced with pnp transistors Q ₆ , Q ₇ and Q ₈ respectively. Description of operation, the polarity of the control signals V ₅₇ and V ₅₈ is applied to the control terminals 57 and 58, V _57> V ₅₈ is in the sampling period, V ₅₇ is in the hold period
<V ₅₈ is the same as the first embodiment except that
The description is omitted because it is duplicated.

〔The invention's effect〕

As described above, the present invention provides an output buffer circuit,
By forming two emitter-followers, each of which forms an emitter follower and the emitters of which are connected to each other, no current flows to the output buffer circuit during the switch-on period, thereby reducing power consumption. In addition, when the drive capability is to be improved, the operating current of the current switch that switches the current direction of the diode that biases the output buffer circuit is increased, and the rise and fall of the base voltage between the bases of the output buffer circuit are increased. Has an effect that the driving capability can be improved with a small increase in power.

The output buffer is switched by means for switching the direction of the current flowing through the diode, which is connected so as to bias the bases of the transistors of the output buffer circuit in the forward or reverse direction in accordance with the ON / OFF state of the control signal. By doing so, even if the switching of the current switch by the differential pair is incomplete, the output buffer circuit is more stably biased in the forward or reverse direction, for example, the effect that the hold operation can be performed more stably. There is.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional example. In the figure, 1 to 4, 6 to 10, 13 ... constant current source, 5, 10, 14 ...
… Hold capacitance, 11, 12… Resistance, Q _{1 to} Q ₁₄ … Transistor, D _{1 to} D ₈ … Diode.

Claims (1)

(57) [Claims] When the level of a predetermined control signal is "on", a signal similar to the input signal is transmitted to an output terminal, and when the level of the control signal is "off", the output signal is transmitted. In a semiconductor integrated circuit configured as an analog switch circuit having a function of setting a terminal to high impedance, an emitter follower is formed as each of the analog switch circuits, and each of the conductive switches has a different conductive type. An output buffer circuit composed of first and second transistors, first and second diodes connected in series between the bases of the first and second transistors, respectively, and acting to bias forward; And third and fourth diodes acting to bias in the reverse direction; And current switching means operable to switch the direction of current flowing into the first and second diodes and the third and fourth diodes in response to the “off” state. Characteristic semiconductor integrated circuit.