JPS62279478A - Logarithmic conversion circuit - Google Patents
Logarithmic conversion circuitInfo
- Publication number
- JPS62279478A JPS62279478A JP12213686A JP12213686A JPS62279478A JP S62279478 A JPS62279478 A JP S62279478A JP 12213686 A JP12213686 A JP 12213686A JP 12213686 A JP12213686 A JP 12213686A JP S62279478 A JPS62279478 A JP S62279478A
- Authority
- JP
- Japan
- Prior art keywords
- dark current
- logarithmic conversion
- circuit
- image sensor
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 238000010586 diagram Methods 0.000 description 4
- 230000009466 transformation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 235000006693 Cassia laevigata Nutrition 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
[産業上の利用分野〕
本発明は、CCD (電荷結合素子)等を用いた蓄積型
イメージセンサの信号出力を高精度に対数変換する対数
変換回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logarithmic conversion circuit that logarithmically converts the signal output of a storage type image sensor using a CCD (charge coupled device) or the like with high accuracy.
[従来の技術]
CCD等のイメージセンサにより画像を光電的に読取る
場合、イメージセンサの出力信号が低輝度側で著しく小
さくなり、検出精度が悪くなる欠点がある。そこで、高
輝度から低輝度までの広いダイナミックレンジに渡って
、略同じ精度で画像信号を得るために、イメージセンサ
の出力信号を対数変換することが考えられる。[Prior Art] When an image sensor such as a CCD is used to photoelectrically read an image, there is a drawback that the output signal of the image sensor becomes significantly small on the low luminance side, resulting in poor detection accuracy. Therefore, in order to obtain image signals with substantially the same precision over a wide dynamic range from high brightness to low brightness, it is conceivable to logarithmically transform the output signal of the image sensor.
従来のこの種の対数変換回路では、予め一定の基準信号
レベルを決め、この基準信号レベル以上の信号が入力す
るように構成されていた。Conventional logarithmic conversion circuits of this type are configured so that a certain reference signal level is determined in advance and a signal higher than this reference signal level is input.
第3図はこのような従来の対数変換回路の構成例を示す
。ここで、ISはCCD等の蓄積型イメージセンサ、D
VはイメージセンサIsを駆動するセンサ駆動用制御回
路(ドライバー)である。また、1は抵抗R1〜R4と
演算増幅器、o p 1とから構成された差動増幅回路
であり、イメージセンサISからの信号出力と、その出
力と同相のノイズを除去するための参照信号との差をと
り、その結果、同相ノイズの除去された信号出力が演算
増幅器aplの出力側に生ずる。FIG. 3 shows an example of the configuration of such a conventional logarithmic conversion circuit. Here, IS is an accumulation type image sensor such as CCD, D
V is a sensor drive control circuit (driver) that drives the image sensor Is. Further, 1 is a differential amplifier circuit composed of resistors R1 to R4 and an operational amplifier, op 1, which outputs a signal from the image sensor IS and a reference signal for removing noise in phase with the output. As a result, a signal output from which common mode noise has been removed is produced at the output of the operational amplifier apl.
RFはイメージセンサIsの暗電流信号レベルに相等す
る基準電圧VRFを可変抵抗VR1を介して発生する基
準電圧発生回路であり、この基準電圧VRFと演算増幅
器aplの信号電圧の差が抵抗R5と対数変換素子LD
Iと演算増幅回路op2から成る対数変換回路2で信号
電流に変換され、対数変換される。RF is a reference voltage generation circuit that generates a reference voltage VRF equivalent to the dark current signal level of the image sensor Is via a variable resistor VR1, and the difference between this reference voltage VRF and the signal voltage of the operational amplifier apl is equal to the logarithm of the resistor R5. Conversion element LD
The signal current is converted into a signal current by a logarithmic conversion circuit 2 consisting of I and an operational amplifier circuit op2, and is subjected to logarithmic conversion.
演算増幅器op2から出力する対数変換信号は、抵抗R
6と温度補償用対数変換素子LD2とから成る温度補償
回路3で温度補償された後に、抵抗R7と演算増幅器o
p3とから成るバッファ増幅回路4で出力インピーダン
スの変換がなされる。The logarithmically converted signal output from the operational amplifier op2 is connected to the resistor R.
6 and a temperature compensation logarithmic conversion element LD2, the resistor R7 and the operational amplifier o
The output impedance is converted in the buffer amplifier circuit 4 consisting of p3.
第4図は上述の第3図の従来回路の主要部の出力信号の
波形例を示す。第4図において、φS□はセンサ駆動用
制御回路DVから供給されるイメージセンサIsの画像
情報読み出し用シフトパルスであり、このシフトパルス
φSHの高レベルパルス信号でイメージセンサISの情
報の読み出しが開始される。また演算増幅器oplの出
力E1〜E3はイメージセンサ25のセンサ部のない空
送り信号部、これに続<DI、D2は遮光画素信号部、
これに続<St〜SNは有効感光信号部、これに続<D
3.D4はダミー画素信号部であり、時刻t3でイメー
ジセンサISの信号の読み出しが完了する。また、演算
増幅器aplの最後の出力E4〜E9は、次の信号の読
み出しが始まるまでの信号蓄積中の空送り信号部である
。FIG. 4 shows an example of the waveform of the output signal of the main part of the conventional circuit shown in FIG. 3 described above. In FIG. 4, φS□ is a shift pulse for reading image information of the image sensor Is supplied from the sensor drive control circuit DV, and reading of information from the image sensor IS is started with the high level pulse signal of this shift pulse φSH. be done. Further, the outputs E1 to E3 of the operational amplifier opl are a blank feed signal section without a sensor section of the image sensor 25, followed by <DI, D2 is a light-shielded pixel signal section,
Following this <St~SN is an effective photosensitive signal section, following this <D
3. D4 is a dummy pixel signal section, and reading of the signal from the image sensor IS is completed at time t3. Further, the last outputs E4 to E9 of the operational amplifier apl are the idle feed signal portion during signal accumulation until the next signal readout begins.
[発明が解決しようとする問題点]
しかしながら、このような従来の対数変換回路では、イ
メージセンサIsの信号を対数変換する場合に、イメー
ジセンサIsの特性のばらつきにより基準信号レベル以
下の信号が入力されることもあるので、良好なる対数変
換が出来ないことが多々あった。[Problems to be Solved by the Invention] However, in such a conventional logarithmic conversion circuit, when logarithmically converting the signal of the image sensor Is, a signal below the reference signal level may be input due to variations in the characteristics of the image sensor Is. Therefore, it was often impossible to perform a good logarithmic transformation.
例えば、RFで生ずる基準電圧レベルが■□、の一定値
に設定されているとすると、各画素毎の暗電流のむらに
より小入力信号時に対数変換出力信号に著しい誤差が発
生した。For example, if the reference voltage level generated by RF is set to a constant value of ■□, a significant error occurs in the logarithmically converted output signal when the input signal is small due to uneven dark current for each pixel.
本発明は、上述のような問題点を解消し、蓄積型イメー
ジセンサの信号出力の高精度で良好なる対数変換出力を
得ることのできる対数変換回路を提供することを目的と
する。SUMMARY OF THE INVENTION An object of the present invention is to provide a logarithmic conversion circuit capable of solving the above-mentioned problems and obtaining a highly accurate and good logarithmic conversion output of a signal output of a storage type image sensor.
E問題点を解決するための手段1
かかる目的を達成するために、本発明は蓄積型イメージ
センナから出力される信号出力を対数変換する対数変換
回路において、イメージセンサを遮光状態にして複数回
有効感光画素の暗電流を読み出す第1の回路と、第1の
回路から読み出された暗電流の各画素毎の平均値を求め
、平均値を対数変換の基準電圧値として各画素毎に発生
する第2の回路とを具備したことを特徴とする。Means for Solving Problem E 1 In order to achieve the above object, the present invention provides a logarithmic conversion circuit that logarithmically converts the signal output output from the storage type image sensor, in which the image sensor is placed in a light-shielded state and the image sensor is activated multiple times. A first circuit reads out the dark current of the photosensitive pixel, and the average value of the dark current read out from the first circuit is determined for each pixel, and the average value is used as a reference voltage value for logarithmic conversion and is generated for each pixel. The present invention is characterized by comprising a second circuit.
[作 用]
本発明では、イメージセンサの遮光時のR’に流の各画
素毎の平均値を対数変換の基準電圧値とするようにした
ので、イメージセンサ出力の高精度の対数変換が出来る
。[Function] In the present invention, since the average value for each pixel of R' when the image sensor is shaded is used as the reference voltage value for logarithmic conversion, highly accurate logarithmic conversion of the image sensor output is possible. .
[実施例]
以下、図面を参照して本発明の実施例を詳細に説明する
。[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第1図は本発明対数変換回路の一実施例の構成を示す。FIG. 1 shows the configuration of an embodiment of the logarithmic conversion circuit of the present invention.
なお、第3図の従来例と同様な機能の部所には同一の符
号を付して説明する。Note that parts having the same functions as those of the conventional example shown in FIG. 3 will be described with the same reference numerals.
第1図において、ADCは差動増幅回路1の演算増幅器
aplのアナログ出力信号をデジタル信号に変換するア
ンログ・デジタル(AD)コンバータ、cpuはADコ
ンバータADCのデジタル出力値の各画素毎の平均値を
算出する演算回路、DACは演算回路cpuの出力平均
値信号をアナログ信号に変換するデジタル・アナログ(
DA)コンバータであり、このDAコンバータDACの
出力は基準電圧として対数変換回路2Aの演算増幅器o
p2の反転入力端子に人力する。In FIG. 1, ADC is an analog-to-digital (AD) converter that converts the analog output signal of the operational amplifier apl of the differential amplifier circuit 1 into a digital signal, and CPU is the average value for each pixel of the digital output value of the AD converter ADC. The arithmetic circuit that calculates DAC is a digital/analog (DAC) that converts the output average value signal of the arithmetic circuit CPU into an analog signal.
DA) converter, and the output of this DA converter DAC is used as a reference voltage to the operational amplifier o of the logarithmic conversion circuit 2A.
Apply power to the inverting input terminal of p2.
まず、イメージセンサISを遮光状態にして、センナ駆
動用制御回路DVにより複数回有効感光画素の暗電流信
号を読み出してADCコンバータでAD変換し、変換さ
れたデジタル暗電流信号を基に演算回路CPUで各画素
毎に暗電流の平均値をデジタル演算し、この演算結果の
各画素毎の暗電流情報をDAコンバータDACでDA変
換して、このDA変換データを対数変換用演算増幅器o
p2の非反転入力側に、基準電圧横報として人力する。First, the image sensor IS is placed in a light-shielded state, and the sensor drive control circuit DV reads out the dark current signal of the effective photosensitive pixel multiple times, and the ADC converter performs AD conversion.Based on the converted digital dark current signal, the arithmetic circuit CPU digitally calculates the average value of the dark current for each pixel, converts the dark current information for each pixel as a result of this calculation from DA to DA converter DAC, and converts this DA converted data to an operational amplifier for logarithmic conversion.
Manually input the reference voltage information to the non-inverting input side of p2.
この場合には、各画素毎に@電流の平均値に基づいて対
数変換の基準レベルの設定が可能なので、第4図に示す
ようなイメージセンサIsの暗電流にむら(ばらつき)
があっても、対応する暗電流の設定が適切に出来、それ
により高精度の対数変換出力を得ることが出来る。In this case, it is possible to set the reference level for logarithmic conversion based on the average value of the @ current for each pixel, so there is no unevenness (variation) in the dark current of the image sensor Is as shown in Figure 4.
Even if there is a problem, the corresponding dark current can be set appropriately, and a highly accurate logarithmic conversion output can thereby be obtained.
また、各画素毎の暗電流信号は平均値を検知しているの
で、イメージセンサ■Sのランダムノイズの影響を著し
く低下させることが出来る。Furthermore, since the average value of the dark current signal for each pixel is detected, the influence of random noise of the image sensor 2 can be significantly reduced.
第2図は本発明の他の実施例構成を示す。第2図におい
て、DAは差動増幅回路であり、演算増幅器aplの出
力とDAコンバータDACの各画素毎の暗電流の平均値
信号との差をとり、イメージセンサIsの出力信号をT
レベルを基準とする信号に変換する。この差動増幅回路
DAの出力は抵抗R5を介して;レベルを基準電圧にし
た対数変換用演算増幅器op2の非反転入力端子に人力
する。その他の構成は第1回の実施例と同様である。FIG. 2 shows the configuration of another embodiment of the present invention. In FIG. 2, DA is a differential amplifier circuit, which takes the difference between the output of the operational amplifier apl and the average value signal of the dark current for each pixel of the DA converter DAC, and converts the output signal of the image sensor Is to T.
Convert to a level-based signal. The output of the differential amplifier circuit DA is input via a resistor R5 to a non-inverting input terminal of a logarithmic conversion operational amplifier op2 whose level is set as a reference voltage. The other configurations are the same as in the first embodiment.
以上の構成において、第1図の実施例と同様にして検出
した各画素毎の暗電流情報のDA変換値と、イメージセ
ンサISの出力値との差を差動増幅回路DAでとり、こ
の差分信号を一定の電圧レベル、例えば実施例では;レ
ベル(グランドレベル)を基準の値にした信号に変換し
て、;レベルを基準電圧とした対数変換用演算増幅器o
p2に人力する。In the above configuration, the differential amplifier circuit DA calculates the difference between the DA conversion value of the dark current information for each pixel detected in the same manner as in the embodiment shown in FIG. 1 and the output value of the image sensor IS. A signal is converted to a signal with a constant voltage level, for example, a level (ground level) as a reference value in the embodiment, and an operational amplifier for logarithmic conversion with the level as a reference voltage is used.
Manpower p2.
本実施例でも、第1図の実施例と同様に、イメージセン
サISの@電流むらの影響を除去した高精度の対数変換
出力を得ることが出来るという顕著な効果がある。Similar to the embodiment shown in FIG. 1, this embodiment also has the remarkable effect of being able to obtain a highly accurate logarithmic conversion output that eliminates the influence of current unevenness of the image sensor IS.
[発明の効果コ
以上説明したように、本発明によれば、イメージセンサ
の遮光時の暗電流の各画素毎の平均値を対数変換の基準
電圧値とするようにしたので、イメージセンサ出力の高
精度の対数変換が出来る。これにより、高輝度から低輝
度の広いダイナミックレンジに渡って、良好な画像信号
を得ることが可能となる。[Effects of the Invention] As explained above, according to the present invention, the average value of the dark current for each pixel during light shielding of the image sensor is used as the reference voltage value for logarithmic transformation, so that the output of the image sensor is High-precision logarithmic transformation is possible. This makes it possible to obtain a good image signal over a wide dynamic range from high brightness to low brightness.
【図面の簡単な説明】
第1図は本発明の一実施例の対数変換回路の構成を示す
回路図、
第2図は本発明の他の実施例の対数変換回路の構成を示
す回路図、
第3図は従来の対数変換回路の構成例を示す回路図、
第4図は第3図の回路の主要部の出力波形の一例を示す
波形図である。
Is・・・蓄積型イメージセンサ、
DV・・・センナ駆動用制御回路、
ADC・・・アナログ・デジタルコンバータ、DAC・
・・デジタル・アナログコンバータ、CPU・・・演算
回路、
DA・・・差動増幅器、
apl、op2.op3・・・演算増幅器、LDI、L
D2・・・対数変換素子、
1・・・差動増幅回路、
2.2A、2B・・・対数変換回路、
3・・・温度補償回路、
4・・・バッファ増幅回路。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram showing the configuration of a logarithmic conversion circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a logarithmic conversion circuit according to another embodiment of the present invention, FIG. 3 is a circuit diagram showing an example of the configuration of a conventional logarithmic conversion circuit, and FIG. 4 is a waveform diagram showing an example of output waveforms of the main parts of the circuit shown in FIG. Is...Storage type image sensor, DV...Senna drive control circuit, ADC...Analog/digital converter, DAC/
...Digital-to-analog converter, CPU...arithmetic circuit, DA...differential amplifier, apl, op2. op3... operational amplifier, LDI, L
D2... Logarithmic conversion element, 1... Differential amplifier circuit, 2.2A, 2B... Logarithmic conversion circuit, 3... Temperature compensation circuit, 4... Buffer amplifier circuit.
Claims (1)
数変換する対数変換回路において、 前記イメージセンサを遮光状態にして複数回有効感光画
素の暗電流を読み出す第1の回路と、該第1の回路から
読み出された前記時電流の各画素毎の平均値を求め、該
平均値を対数変換の基準電圧値として各画素毎に発生す
る第2の回路と を具備したことを特徴とする対数変換回路。 2)特許請求の範囲第1項記載の回路において、 前記第2の回路で得られた前記基準電圧値を対数変換増
幅器の非反転入力側に供給することを特徴とする対数変
換回路。 3)特許請求の範囲第1項記載の回路において、 前記第2の回路で得られた前記基準電圧値と前記イメー
ジセンサの出力値との差分を対数変換増幅器に供給する
ことを特徴とする対数変換回路。[Scope of Claims] 1) A logarithmic conversion circuit that logarithmically converts a signal output output from an accumulation type image sensor, comprising: a first circuit that reads out the dark current of an effective photosensitive pixel a plurality of times with the image sensor in a light-shielded state; , a second circuit that calculates the average value of the current read out from the first circuit for each pixel, and generates the average value for each pixel using the average value as a reference voltage value for logarithmic conversion. A logarithmic conversion circuit featuring: 2) The circuit according to claim 1, wherein the reference voltage value obtained by the second circuit is supplied to a non-inverting input side of a logarithmic conversion amplifier. 3) The circuit according to claim 1, wherein the difference between the reference voltage value obtained by the second circuit and the output value of the image sensor is supplied to a logarithmic conversion amplifier. conversion circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12213686A JPS62279478A (en) | 1986-05-29 | 1986-05-29 | Logarithmic conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12213686A JPS62279478A (en) | 1986-05-29 | 1986-05-29 | Logarithmic conversion circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62279478A true JPS62279478A (en) | 1987-12-04 |
Family
ID=14828503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12213686A Pending JPS62279478A (en) | 1986-05-29 | 1986-05-29 | Logarithmic conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62279478A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60189372A (en) * | 1984-03-08 | 1985-09-26 | Dainippon Screen Mfg Co Ltd | Picture input device |
-
1986
- 1986-05-29 JP JP12213686A patent/JPS62279478A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60189372A (en) * | 1984-03-08 | 1985-09-26 | Dainippon Screen Mfg Co Ltd | Picture input device |
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