JPH0556356A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To operate an analog signal processing with a high precision almost without increasing a circuit scale by constituting a signal processing circuit so that the output of a sample-and-hold circuit can be one input of an arithmetic amplifier. CONSTITUTION:This signal processing circuit is constituted of a differential circuit 4 which searches a difference between an output signal from a sensor 1 and the signal held by a sample-and-hold circuit 5 after D/A converting output data stored in a memory 10, and a serial comparison type A/D converter 6 constituted of a converter 7 which converts the analog output signal of the differential circuit 4 into the digital signal, D/A converter 9, and shift register 8 for a serial comparison. Then, the operations of both one part of an A/D converter which converts the analog output signal of the arithmetic amplifier into the digital signal, and the D/A converter which converts the digital signal into the analog signal, are attained by the serial comparison type A/D converter 6. Therefore, the analog signal processing with the high precision can be attained almost without increasing the circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention eliminates variations in offset output between pixels in a solid-state imaging device such as a lisensor or area sensor having a plurality of photoelectric conversion elements, that is, fixed pattern noise. The present invention relates to a signal processing circuit for A / D converting a signal component corresponding to the light amount of each pixel.

[0002]

2. Description of the Related Art Generally, as an approach for increasing the sensitivity of a solid-state image pickup device such as a licensor or an area sensor, SIT,
Amplified solid-state imaging devices such as AMI, CMD, BASIS, and FGA have been proposed. Each of these amplification type solid-state imaging devices has high sensitivity because it has an amplification element for each pixel, but there is a problem of fixed pattern noise due to variations in the amplification element.

In order to solve this problem, conventionally, FIG.
There is known a fixed pattern noise suppression circuit including an A / D converter, a memory, a differential circuit and the like as shown in FIG. The principle of operation of this fixed pattern noise suppression circuit is that the switch SW1 is first connected to the DARK side, the sensor 101 is set in the light-shielded state, and the dark output data of the sensor 101 is digitalized by the A / D converter 103 via the amplifier 102. Memory converted to data
Memorize in 104. After that, when the light shielding state of the sensor 101 is released and the subject is photographed, switch SW1 is switched to SIG.
Connected to the output side of the sensor 101, the digital signal obtained by A / D converting the output signal of the sensor 101 and the dark output data previously stored in the memory 104 are digitally differentiated by the differential circuit 105, and the data is output as a signal. It is what

However, this fixed pattern noise suppression circuit has the following problems. That is, for example, as shown in FIG. 9, when the fixed pattern noise b is larger than the signal component a, assuming that the A / D converter has 8 bits, the signal component including the fixed pattern noise in the input range of this A / D converter. Since c is assigned, the maximum signal component is 7
You can only get sub-bit accuracy. Further, in reality, even if the brightness of the subject changes, it is necessary to allocate the levels with a margin so that the A / D converter does not saturate the signal.
/ N gets worse. The only way to improve this is to raise the precision of the A / D converter to 10 bits or 12 bits, but raising the precision of the A / D converter leads to an increase in cost.

On the other hand, in order to solve the above problems,
As shown in FIG. 10, there is known a fixed pattern noise suppression circuit having a configuration in which a D / A converter is further added. This circuit
Similar to the circuit shown in FIG. 8, the switches SW1 and SW2 are connected to the DARK side to output the dark output data to the amplifiers 108 and A /.
It is taken into the memory 104 via the D converter 103. In this case, the initial data (0) is input via the switch SW2. At this time, the difference from the circuit shown in FIG. 8 is that as shown in the signal waveform diagram of FIG.
A fixed pattern noise component is assigned to the entire input range of the / D converter 103. After that, when the subject is imaged, by connecting the switches SW1 and SW2 to the SIG side, the dark output data stored in the memory 104 is sent to the D / A converter 106 and converted into an analog signal. The differential circuit 102 performs the difference between the dark signal and the output signal at the time of imaging the subject. When this output is converted to an appropriate gain through the amplifier 107 and A / D converted by the A / D converter 103, the signal output can obtain an accuracy close to 8 bits as shown in FIG. Note that FIG. 11B is a diagram showing a signal waveform obtained by adding the subject signal and the fixed pattern noise when the subject is imaged. However, this fixed pattern noise suppression circuit uses a D / A converter in addition to the A / D converter.
Since a converter is required, there is a problem that the circuit scale becomes large. In addition, this circuit configuration has a problem that the quantization error increases when the linearity of the A / D converter and the D / A converter do not match.

[0006]

As described above, in the conventional fixed pattern noise suppression circuit, a signal containing fixed pattern noise is digitally fixed by using an A / D converter and a memory. When removing the pattern noise, there is a problem that the accuracy of the actual signal becomes worse than the accuracy of the A / D converter.
When a converter is added and analog difference is taken to remove fixed pattern noise, the accuracy is improved, but the addition of the D / A converter increases the circuit scale.

The present invention has been made in order to solve the above problems in the conventional fixed pattern noise suppression circuit, and it is a signal processing that can be processed with high accuracy in an analog manner without increasing the circuit scale. The purpose is to provide a circuit.

[0008]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an operational amplifier for performing an operation on a plurality of input signals, and an analog signal output from the operational amplifier for converting the analog signal into a digital signal. , A successive approximation A / D converter including a comparator, a D / A converter, and a successive approximation shift register, and a sample hold for holding the output of the D / A converter included in the A / D converter And a circuit, and the signal processing circuit is configured so that the output of the sample and hold circuit is one input of the operational amplifier.

In the signal processing circuit thus constructed, the D / A converter constituting the successive approximation A / D converter is one of the A / D converters for converting the analog output signal of the operational amplifier into a digital signal. And the D / A converter that converts a digital signal into an analog signal,
It is possible to perform signal processing with high accuracy in an analog manner without increasing the circuit scale. Further, since the linearity of the A / D converter and the linearity of the D / A converter are the same, the distortion caused by the D / A conversion after the A / D conversion is quantized by the A / D conversion. Only noise and no other extra distortion.

[0010]

EXAMPLES Next, examples will be described. FIG. 1 is a circuit configuration diagram showing an embodiment of a signal processing circuit according to the present invention.
In this embodiment, the present invention is applied to a fixed pattern noise suppression circuit of a sensor. In the figure, 1 is a sensor,
Reference numeral 2 is a buffer, 3 is a sample and hold circuit that samples and holds the output of the sensor 1, and 4 is a differential circuit that samples and holds the output of the sample and hold circuit 3 and the output of a D / A converter 9 described later. The difference from the output of the sample and hold circuit 5 is output. Reference numeral 6 is a successive approximation type A / D converter that performs A / D conversion on the differential output of the differential circuit 4, and includes a comparator 7 and a successive approximation shift register 8
And a D / A converter 9. In this successive approximation type A / D converter 6, while the digital input of the D / A converter 9 is scanned by the successive approximation shift register 8 from the upper bits of the D / A converter 9 one by one, While the output voltage of the converter 9 and the signal input voltage are compared by the comparator 7, the upper bit is quantized, and the complete quantized code is obtained when the scanning is completed up to the lower bit. In this embodiment, this successive approximation A / D
The converter 6 has 8 bits, and its digital output line is shown as 8 bits in the figure. As a matter of course, there is no problem even if the number of bits is changed depending on the usage of the system used.

The digital output of the A / D converter 6 is input to the memory 10. The memory 10 is for writing output data of the sensor 1 in the dark, that is, fixed pattern noise data. The output data of the memory 10 is input to the D / A converter 9 via the switch SW1. This switch SW1 is
The switch SW1 is used to switch between the case where the D / A converter 9 is used as a part of the successive approximation A / D converter 6 and the case where the data in the memory 10 is converted into an analog signal. Is connected to the terminal A / D side, the former operation is performed, and when the switch SW1 is connected to the terminal D / A side, the latter operation is performed. As described above, the input signal to the successive approximation A / D converter 6 is the differential between the voltage obtained by sampling and holding the signal of the sensor 1 and the voltage obtained by D / A converting the data in the memory 10 and holding it. 2 and 3, which are differences obtained through the circuit 4, one configuration example of the sample and hold circuits 3 and 5 and one configuration example of the differential circuit 4. 2, 11 and 12 are buffers, and 13 is an operational amplifier in FIG.

Next, the operation of the fixed pattern noise suppressing circuit configured as described above will be described with reference to the timing chart shown in FIG. In each of the output signals of the sensor output and sample / hold circuits 3 and 5, and the differential circuit 4, the time when the dark output of the sensor 1 is taken in is shown by a broken line, and the output when light is incident is shown by a solid line. ..
The dark output of the sensor 1 can be obtained not only by blocking the incident light or by reducing the diaphragm, but also by sufficiently shortening the accumulation time in the sensor 1.

As a sensor output, a signal voltage corresponding to each pixel is output at a constant cycle T ₀ . Select the period in which the pixel signal appears in this sensor output and set the switch SW1 to D /
It connects to the A side and outputs the data in the memory 10. This memory data is reset to 0 when the dark output is fetched, and when the optical signal is A / D converted, the dark output A / D converted data corresponding to each pixel is output. Keep it. In FIG. 4, when the pulse of the switch SW1 is at the “H” level (period T ₁ ), it corresponds to the period in which the memory data is output from the D / A converter 9. During this T ₁ , the signal φ _SH
Is set to the "H" level to perform sample and hold, the signal output of the sensor is held at the S / H1 output of the sample and hold circuit 3, and the sample and hold circuit 5
The analog value of the memory data output is held in the S / H2 output of the.

In the case of darkness, since the memory data is 0, that is, the analog signal is 0 level, the signal corresponding to the sensor signal appears in the output of the differential circuit 4, that is, the fixed pattern noise in darkness remains as it is. Is output. Period T ₂
Switch SW1 is connected to the A / D side with
A / D conversion is performed in the D converter 6, and the dark fixed pattern noise data is stored in the memory 10.

In this manner, once the dark fixed pattern noise data has been fetched into the memory 10, the sensor 1 then performs optical integration to output a bright signal. Like the dark, the sensor signals and D / A converted signal and sample-and-hold for a period of T _1, performs A / D conversion in a period T _2. In the case of bright time, the fixed pattern noise signal taken in in the dark is output from the sample and hold circuit 5, so that a signal from which the fixed pattern noise is removed appears in the output of the differential circuit 4. This signal is converted into a digital signal by the A / D converter 6 and output.

As described above, in this embodiment, the D / A converter 9 included in one successive approximation A / D converter 6 is used.
As a result, the fixed pattern noise data is converted into an analog signal, so that the circuit scale does not become large as compared with the conventional fixed pattern noise suppression circuit shown in FIG. Even if the D / A converter has some non-linear characteristics,
Since the characteristics of D conversion and the characteristics of D / A conversion are the same, factors of characteristic deterioration other than quantization noise are canceled out, an analog output of fixed pattern noise with good reproducibility is obtained, and fixed pattern noise can be removed accurately. ..

In the above-described embodiment, a sample-and-hold circuit is added by using the successive approximation A / D converter to perform the fixed pattern noise removing operation with high accuracy similar to that of the suppressing circuit shown in FIG. But next, this sample
FIG. 5 shows a second embodiment in which the hold section and the differential section have a simpler configuration. In this embodiment, the structure of the rear part is the first
Same as the embodiment, but the differential part is composed of the series-parallel capacitors C ₁ and C _2, and the sample and hold part is composed of the switches SW2, SW3 and SW4, and the circuit structure is considerably simplified. .. In the figure, both 2-1 and 2-2 are buffers.

Next, the operation of the second embodiment thus constructed will be described with reference to the timing chart shown in FIG. Sensor output and serial-parallel capacitor C shown in FIG.
_In the signal waveforms of the input side node N1 and the output side node N2 of ₁ and C ₂ , the level when the dark output of the sensor 1 is taken in is shown by the broken line, and the level when light is incident is shown by the solid line. ing. When the switch SW1 is at "H" level, it is switched to the D / A mode, the D / A converter 9 generates the D / A conversion output of the memory data, and "L".
When the level is reached, the mode is switched to A / D mode and D / A
The converter 9 operates as a part of the successive approximation A / D converter 6. When the switch SW1 is at "H" level, the switches SW3 and SW4 are first turned on to hold the D / A conversion output in the series capacitor C ₂ . Next, the switches SW3, SW
4 is turned off, the switch SW2 is turned on, and the sensor output is held in the parallel capacitor C ₁ . Capacitor C ₁ ,
If the capacitances of C ₂ are equal, a sensor output appears at the node N 1, and a differential output obtained by subtracting the potential of the series capacitor C ₂ , that is, the potential of the D / A conversion output from the sensor output appears at the node N _2. .. This difference output is A / D converted in the period T ₃ .

The D / A converter 9 is used for capturing the output in the dark.
Always set to 0 the output from the node in the period T ₃ N2
Since the sensor output directly appears in the, the sensor output is A / D converted by the successive approximation type A / D converter 6 and taken into the memory 10 as dark output data. Then when the optical integrator output uptake sensor 1, the series capacitor C ₂ in period T _1,
When the dark output data previously fetched in the memory 10 is held via the D / A converter 9 and the sensor output is held in the parallel capacitor C ₁ during the period T ₂ , the fixed pattern noise amount in the dark at the node N2. The signal with the removed signal appears. The signal appearing at the node N2 is A / D converted in the period T ₃ and output as output data.

In each of the above embodiments, the fixed pattern noise suppressing circuit using the successive approximation type A / D converter is shown. However, instead of this successive approximation type A / D converter, the D / A converter is internally provided. It is also possible to use a serial-parallel type A / D converter having FIG. 7 is a circuit configuration diagram showing a third embodiment of the present invention using the serial / parallel A / D converter 20. This serial-parallel type A / D converter 20 includes a high-order A / D converter 21 and a D / A converter.
It is composed of 22, the lower A / D converter 23 and the differential circuit 24, and can remove fixed pattern noise at the same timing as the timing chart of the first embodiment shown in FIG. However, the D / A converter 22 normally included in the serial / parallel type A / D converter 20 has an accuracy of higher bits, and an 8-bit A / D converter has an accuracy of 4 to 5 bits. Therefore, the fixed pattern noise can be removed only by the accuracy. Therefore, in order to remove the fixed pattern noise more accurately, it is necessary to further perform digital subtraction.
Since the analog signal is once roughly subtracted, the input range of the A / D converter can be effectively used.

[0021]

As described above on the basis of the embodiments,
According to the present invention, since signal processing can be performed on an analog signal without increasing the circuit scale, the A / D converter input range can be effectively used and signal processing can be performed with high accuracy.
Further, since the characteristics such as the linearity of the A / D converter and the D / A converter are the same, there is an advantage that quantization noise is not unnecessarily superimposed.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a signal processing circuit according to the present invention.

FIG. 2 is a diagram showing a configuration example of a sample hold circuit in the embodiment shown in FIG.

FIG. 3 is a diagram showing a configuration example of a differential circuit in the embodiment shown in FIG.

FIG. 4 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 5 is a circuit configuration diagram showing a second embodiment.

FIG. 6 is a timing chart for explaining the operation of the second embodiment.

FIG. 7 is a circuit configuration diagram showing a third embodiment.

FIG. 8 is a circuit configuration diagram showing a configuration example of a conventional fixed pattern noise suppression circuit.

9 is a signal waveform diagram for explaining the operation of the fixed pattern noise suppression circuit shown in FIG.

FIG. 10 is a circuit configuration diagram showing another configuration example of a conventional fixed pattern noise suppression circuit.

11 is a signal waveform diagram for explaining the operation of the fixed pattern noise suppression circuit shown in FIG.

[Explanation of symbols]

 1 sensor 2 buffer 3, 5 sample and hold circuit 6 successive approximation A / D converter 7 comparator 8 successive approximation shift register 9 D / A converter 10 memory 20 serial-parallel A / D converter

Claims (3)

[Claims] 1. An operational amplifier for operating a plurality of input signals, and a successive approximation including a comparator, a D / A converter, and a successive approximation shift register for converting an analog signal output from the operational amplifier into a digital signal. Type A / D converter and a sample / hold circuit for holding the output of the D / A converter included in the A / D converter, the output of the sample / hold circuit being one of the operational amplifiers. A signal processing circuit characterized by being input. 2. The signal processing circuit according to claim 1, wherein
Instead of the operational amplifier, a capacitor that holds an input signal and a capacitor that holds the output of the D / A converter are provided, and a circuit that performs a difference operation by calculating the difference between the charges accumulated in them is used. Signal processing circuit. 3. The signal processing circuit according to claim 1, wherein
A serial / parallel A / D converter including an A / D converter for upper bits, an A / D converter for lower bits, and a D / A converter for upper bits instead of the successive approximation A / D converter Using
A signal processing circuit characterized in that the output of a sample hold circuit for holding the output of the D / A converter for the upper bits of the serial-parallel type A / D converter is one input of an operational amplifier.