JP4469989B2 - N-bit A / D converter - Google Patents

Description

  The present invention relates to an N-bit A / D converter.

Non-Patent Document 1 describes a cyclic A / D converter integrated in an image sensor column. Patent Document 1 describes an A / D conversion array for an image sensor. According to this A / D conversion array, the number of amplifiers and capacitors can be reduced as compared with the conventional cyclic A / D converter, and noise generated in the pixels of the image sensor can be canceled. Non-Patent Document 2 applies to a cyclic A / D converter for readout of a CMOS image sensor having a wide dynamic range. The cyclic A / D converter is integrated in the column of the pixel array of the image sensor.
S. Decker, RD Mcgrath, K. Brehmer, CG Sodini, “A 256 x 256 CMOS imaging array with wide dynamic rangepixels and column parallel digital output,” IEEE J. Solid-State Circuits, vol.33, no. 12, pp 2081-2091, Dec. 1998. M. Mase, S. Kawahito, M. Sasaki, Y. Wakamori, A 19.5b Dynamic Range CMOS Image Sensor with 12b Column-ParallelCyclic A / D Converters, Dig. Tech. Papers, Int.Solid-Sate Circuits Conf., No .19.3 (2005). JP 2005-136540 A (Japanese Patent Application No. 2003-368340)

  In the cyclic A / D converter of Non-Patent Document 1, three amplifiers are required per channel together with an amplifier for canceling noise generated in the pixel portion of the image sensor. For this reason, the area occupied by the A / D converter is large, and its power consumption is also large. On the other hand, according to the A / D converter of Patent Document 1, noise cancellation and cyclic A / D conversion can be performed using a single amplifier. Further, as described in Non-Patent Document 2, this cyclic A / D converter is integrated in a column of a CMOS image sensor to achieve 12-bit resolution.

  As described above, the cyclic A / D converter can realize a relatively high speed operation with a relatively small circuit scale and is suitable for high resolution. Other configuration examples include the following. In this example, cyclic A / D conversion is performed using a circuit in which unit circuits are connected in two stages and a first stage input is connected to a second stage output via a feedback path. Each unit circuit amplifies the input signal twice and adds or subtracts a reference voltage according to the conversion result from the comparator. Since the unit circuits are connected in cascade in two stages, it is possible to generate an A / D conversion value of 2 bits per clock. For example, if A / D conversion is repeated five times, a 10-bit A / D conversion value can be obtained. The cyclic A / D converter described in Non-Patent Document 2 is the world's first 12-bit resolution as an A / D converter integrated in a CMOS image sensor column.

  However, in order to further improve the resolution in the cyclic A / D converter, it is necessary to prevent deterioration in A / D conversion accuracy due to variation (mismatch) of capacitors used in the circuit. In addition, it is necessary to prevent deterioration in A / D conversion accuracy due to the fact that the gain of the operational amplifier circuit of the cyclic A / D converter is a finite value. If accuracy deterioration cannot be improved due to these factors, it is difficult to realize a resolution exceeding 12 bits.

  The present invention has been made in view of such circumstances, and an object thereof is to provide an N-bit A / D converter capable of reducing deterioration in A / D conversion accuracy caused by circuit elements.

One aspect of the present invention provides an N-bit A / D converter capable of correcting a conversion error caused by a circuit element. The N-bit A / D converter includes (a) an input for receiving an analog signal, an output, and a gain stage including an operational amplifier circuit having the input and output, and a digital signal corresponding to the signal from the output of the gain stage An A / D conversion comparison circuit that provides a control signal, a logic circuit that generates a control signal in response to the digital signal, and a D / A conversion circuit that provides a voltage signal to the gain stage in response to the control signal A cyclic A / D conversion circuit including the bit string generated from the digital signal from the cyclic A / D conversion circuit together with a digital coefficient stored for the conversion error caused by the gain stage. And a digital circuit for generating a corrected digital value by correcting the conversion error on the digital signal. The conversion error includes at least one of a mismatch error of capacitance values of capacitors of the gain stage and a finite gain error of the operational amplifier circuit, and the gain stage includes a first capacitor and a second capacitor. The first capacitor receives the analog signal during a first period, and receives the analog signal between the D / A conversion circuit and the input of the operational amplifier circuit in a second period after the first period. And connected to the output of the operational amplifier circuit in a third period after the second period, and the second capacitor receives the analog signal during the first period At the same time, it is connected between the input and the output of the operational amplifier circuit in the second and third periods.
In the N-bit A / D converter according to one aspect of the present invention, the output of the operational amplifier circuit is connected to one end of the first capacitor in the third period, and the gain stage includes the gain stage, Further included is a third capacitor connected to the output of the operational amplifier circuit in a second period and connected to the first input of the operational amplifier circuit in the third period. The digital circuit includes a first circuit for correcting a conversion error caused by the mismatch error, and a second circuit for correcting a conversion error caused by the finite gain error. The first circuit includes a plurality of first registers for storing a bit string corresponding to the number of bits to be corrected, a second register for storing a first digital coefficient value for correcting the mismatch error, and the first circuit. A first adder for adding a digital value of one register to generate an added value; and a first multiplier for multiplying the first digital coefficient value by the added value to generate a first multiplied value And a vessel. The second circuit includes a plurality of third registers for storing a bit string corresponding to the number of bits to be corrected, a fourth register for storing a second digital coefficient value for correcting the finite gain error, A second adder that adds the digital values of the third register to generate an added value; and a second adder that multiplies the second digital coefficient value and the added value to generate a second multiplied value. And a multiplier. The digital circuit includes a third adder that adds the first multiplication value and the second multiplication value. The A / D conversion comparison circuit provides the digital signal during the first to third periods. The D / A conversion circuit provides the voltage signal to the first capacitor of the gain stage during the second period, and supplies the voltage to the third capacitor of the gain stage during the third period. Provide a signal.
In the N-bit A / D converter according to one aspect of the present invention, the output of the operational amplifier circuit is connected to one end of the first capacitor in the third period, and the gain stage includes the gain stage, Further included is a third capacitor connected to the output of the operational amplifier circuit in a second period and connected to the first input of the operational amplifier circuit in the third period. The digital circuit includes a first circuit for correcting a conversion error caused by the mismatch error. The first circuit includes a plurality of first registers for storing a bit string corresponding to the number of bits to be corrected, a second register for storing digital coefficient values for correcting the mismatch error, and the first register. An adder for adding the digital values to generate an added value, and a multiplier for multiplying the digital coefficient value by the added value. The A / D conversion comparison circuit provides the digital signal during the first to third periods. The D / A conversion circuit provides the voltage signal to the first capacitor of the gain stage during the second period, and supplies the voltage to the third capacitor of the gain stage during the third period. Provide a signal.
In the N-bit A / D converter according to one aspect of the present invention, the output of the operational amplifier circuit is connected to one end of the first capacitor in the third period, and the gain stage includes the gain stage, The digital circuit further includes a third capacitor connected to the output of the operational amplifier circuit in a second period and connected to the first input of the operational amplifier circuit in the third period. A second circuit for correcting a conversion error caused by the finite gain error; The second circuit includes a plurality of first registers that store a bit string corresponding to the number of correction target bits, a second register that stores a digital coefficient value for correcting the finite gain error, and the first circuit An adder for adding the digital values of the registers to generate an added value; and a multiplier for multiplying the digital coefficient value by the added value. The A / D conversion comparison circuit provides the digital signal during the first to third periods. The D / A conversion circuit provides the voltage signal to the first capacitor of the gain stage during the second period, and supplies the voltage to the third capacitor of the gain stage during the third period. Provide a signal.

  According to this N-bit A / D converter, the gain stage samples the analog signal during the first period, and generates an arithmetic value at the output of the operational amplifier circuit during the second and third periods. Sample the computed value for the next computation. In addition, the digital circuit performs conversion error correction on the digital signal from the cyclic A / D conversion circuit using the digital coefficient for conversion error caused by the gain stage stored in the digital circuit. Corresponding corrected digital values are obtained. In addition, since the gain stage uses a single operational amplifier circuit for cyclic A / D conversion, the circuit for correcting the conversion error is simplified.

  In the N-bit A / D converter according to the present invention, the output of the operational amplifier circuit is connected to one end of the first capacitor during the third period. The A / D conversion comparison circuit provides the digital signal during the first and third periods, and the D / A conversion circuit provides the voltage signal to the gain stage during the second period. .

  In this N-bit A / D converter, the gain stage includes the operational amplifier circuit and the first and second capacitors as main components, so that the circuit for correcting the conversion error becomes very simple. In the second period, an arithmetic value is generated at the output of the operational amplifier circuit and A / D conversion is performed. In the third period, the operation value generated at the output of the operational amplifier circuit is sampled for the next operation.

  In the N-bit A / D converter according to the present invention, the output of the operational amplifier circuit is connected to one end of the first capacitor during the third period, and the gain stage includes the second stage A third capacitor connected to the output of the operational amplifier circuit in a period and connected to the first input of the operational amplifier circuit in the third period, and further comprising the comparison circuit for A / D conversion Provides the digital signal in the first to third periods, and the D / A converter circuit provides the voltage signal to the first capacitor of the gain stage in the second period; The voltage signal is provided to the third capacitor of the gain stage during the third period.

  In this N-bit A / D converter, the gain stage includes the operational amplifier circuit and the first to third capacitors as main components, so that the circuit for correcting the conversion error is simplified. In the second period, the first and second capacitors are used to generate a calculation value at the output of the operational amplifier circuit, and A / D conversion is performed on this value, and the calculation value generated at the output of the operational amplifier circuit Is sampled into a third capacitor for the next operation. Further, during the third period, the second and third capacitors are used to generate a calculation value at the output of the operational amplifier circuit, and this value is A / D converted and generated at the output of the operational amplifier circuit. The computed value is sampled on the first capacitor for further computations.

  In the N-bit A / D converter according to the present invention, the digital circuit may include a first circuit for correcting a conversion error caused by the mismatch error, and a conversion caused by the finite gain error. A second circuit for correcting the error may be included. The first circuit includes a plurality of first registers for storing a bit string corresponding to the number of bits to be corrected, a second register for storing a first digital coefficient value for correcting the mismatch error, and the first circuit. A first adder for adding a digital value of one register to generate an added value; and a first multiplier for generating a first multiplied value by multiplying the second digital coefficient value by the added value Including The second circuit includes a plurality of third registers for storing a bit string corresponding to the number of bits to be corrected, a fourth register for storing a second digital coefficient value for correcting the finite gain error, A second adder for adding the digital values of the third register to generate an added value; and a second adder for multiplying the second digital coefficient value and the added value to generate a second multiplied value. And a multiplier. The digital circuit further includes a third adder that adds the first multiplication value and the second multiplication value.

  According to the N-bit A / D converter, when the digital circuit includes the first circuit, the digital circuit uses a bit string corresponding to the number of bits for mismatch error correction and a digital coefficient value for mismatch error correction. Thus, the conversion error due to the mismatch error can be corrected. A bit string corresponding to the number of correction target bits is stored in a plurality of first registers in the first circuit, and a digital coefficient value for mismatch error correction is stored in a second register. In this N-bit A / D converter, after adding the digital value of the first register using the first adder, the corresponding digital coefficient value and this added value are multiplied using the first multiplier. To do. A corrected digital value corresponding to the analog signal is generated using the first multiplication value.

  Further, according to the N-bit A / D converter, when the digital circuit includes the second circuit, the digital circuit includes a bit string corresponding to the number of bits subject to finite gain error correction and a digital function for finite gain error correction. The conversion error due to the finite gain error can be corrected using the numerical value. A bit string corresponding to the number of bits to be corrected is stored in a plurality of third registers in the first circuit, and a digital coefficient value for mismatch error correction is stored in a fourth register. In this N-bit A / D converter, after adding the digital value of the first register using the second adder, the corresponding digital coefficient value and this added value are multiplied using the second multiplier. To do. A corrected digital value corresponding to the analog signal is generated using the second multiplication value.

  Furthermore, according to the N-bit A / D converter, when the digital circuit includes the first and second circuits, both the conversion error caused by the mismatch error and the conversion error caused by the finite gain error can be corrected. . For this purpose, the digital circuit includes an arithmetic circuit that adds a correction calculation value for each error factor, and further includes, for example, a third adder that adds the first multiplication value and the second multiplication value. Using this added value, a corrected digital value corresponding to the analog signal is generated.

  In the N-bit A / D converter according to the present invention, the gain stage repeats the operations in the second and third periods in the fourth period. According to the N-bit A / D converter, a digital value having a desired number of bits can be obtained repeatedly, and an upper digital value having a desired number of bits can be corrected.

  In the N-bit A / D converter according to the present invention, the digital operation in the digital circuit is performed using a redundant binary representation, and the corrected digital value generated by the digital circuit is represented in a redundant binary representation, The N-bit A / D converter may include a circuit that converts a redundant binary representation of the corrected digital value into a non-redundant binary representation.

  Alternatively, the N-bit A / D converter according to the present invention may include a circuit that converts a redundant binary representation of an uncorrected digital value into a non-redundant binary representation. it can. Digital operations in the digital circuit are performed using a non-redundant binary representation, and the digital circuit generates a corrected digital value represented in the non-redundant binary representation.

  The N-bit A / D converter according to the present invention can be used for an image sensor, for example. The image sensor includes a pixel array including a plurality of pixels arranged in an array, and each pixel generates a first signal when the floating diffusion layer of the pixel is in a reset state, and the floating of the pixel A second signal is generated when the diffusion layer is in a photo-induced charge accumulation state, and the image sensor includes a plurality of circuits each of which is directly connected to the column line of the pixel array as described above. And an A / D converter. The pixel generates a first signal when the floating diffusion layer of the pixel is in a reset state, and generates a second signal when the floating diffusion layer of the pixel is in a photo-induced charge accumulation state. Including elements.

  According to the N-bit A / D converter, an analog signal from a pixel of the image sensor can be converted into a digital signal.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, an N-bit A / D converter capable of reducing deterioration in A / D conversion accuracy caused by circuit elements is provided.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Next, embodiments of the N-bit A / D converter according to the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

(First embodiment)
FIG. 1 is a diagram illustrating an image sensor. FIG. 2 is a diagram illustrating an N-bit A / D converter. FIG. 3 is a diagram showing a cyclic A / D converter. FIG. 4 is a diagram showing a timing chart for the cyclic A / D converter.

  Referring to FIG. 1, in the CMOS image sensor 1, a vertical shift register 3 is connected to a row of the cell array 2, and an A / D converter array 4 is connected to a column of the cell array 2. The A / D converter array 4 includes a plurality of A / D converters arranged in an array. A cyclic A / D converter circuit 11 can be used as each A / D converter. The N-bit A / D converter 11 is used in the CMOS image sensor 1 and can correct conversion errors caused by circuit elements. In the cell array 2 of the CMOS image sensor 1, for example, CMOS image sensor pixels 2a are arranged in the row direction and the column direction. FIG. 1 shows an example of the CMOS image sensor pixel 2a. The pixel 2a generates the first signal S1 in the reset state and the second signal S2 in the light induced signal output. An input 13 of the A / D converter 11 is connected to the pixel 2a. A data register 5 is connected to the A / D converter array 4, and an A / D conversion value corresponding to a signal from the pixel 2 a is stored in the data register 5. The data register 5 provides an A / D conversion value to the digital circuit 12 for correcting a conversion error caused by the circuit element of the cyclic A / D conversion circuit 11 in response to a signal from the horizontal shift register 6. The digital circuit 12 generates a corrected digital signal for the N-bit digital code, and this corrected digital signal is provided to the redundant representation-nonredundant representation conversion circuit 7. The redundant expression / non-redundant expression conversion circuit 7 generates a digital code of non-redundant expression corresponding to the signal from the pixel 2a.

In the pixel 2a, the photodiode _DF receives light for one pixel (Optical Signal) related to the image. The gate of the selection transistor M _S is connected to the row select line Si extending in the row direction. The gate of the reset transistor M _R is connected to a reset line Ri. The gate of the transfer transistor M _T is connected to the transfer selection line extending in the row direction. One end of the photodiode D _F is connected to the floating diffusion layer FD via the transfer transistor M _T. Floating diffusion layer FD is connected to a reset potential line Reset via the reset transistor M _R, is connected to the gate of the transistor M _A. One current terminal (for example, drain) of the transistor M _A is connected to the column line 8 via the selection transistor M _S. Transistor M _A is provided in the column line through the selection transistor M _S a potential corresponding to the charge amount of the floating diffusion layer FD.

In the pixel having this structure, the noise canceling operation is performed as follows. First, to provide a reset control signal R to the reset transistor M _R, it resets the floating diffusion layer FD. Through the amplification transistor M _A, read out the reset level. The pixel 2a generates the first signal S1 when the floating diffusion layer FD is in the reset state. Then, a charge transfer control signal TX is supplied to the transfer transistor M _T, is transferred from the photodiode D _F photoinduced signal charges to the floating diffusion layer FD. Thereafter, through the transistor M _A, reading the signal level. The second signal S2 is generated when the floating diffusion layer FD of the pixel 2a is in a photo-induced charge accumulation state. An N-bit A / D converter 4 can be used to convert an analog signal from the pixel 2a of the image sensor 1 into a digital signal.

  Referring to FIGS. 1 and 2, the N-bit A / D converter 4a is connected to a cyclic A / D converter circuit 11 that receives an analog signal and an analog signal connected to the cyclic A / D converter circuit 11. And a digital circuit 12 for generating a digital signal corresponding to.

Referring to FIG. 3, the cyclic A / D converter circuit 11 has an input 11 _in and an output 11 _out for receiving an analog signal, a gain stage 15, an A / D conversion comparator circuit 17, A logic circuit 19 and a D / A conversion circuit 21 are included. The gain stage 15 has an operational amplifier circuit 23, and the operational amplifier circuit 23 has an input 23a and an output 23b. The gain stage 15 samples the analog signal _VIN during the first period T1, generates an operation value at the output 23b of the operational amplifier circuit 23 during the second and third periods T2 and T3, and outputs the operation amplifier circuit 23. The operation value generated in 23b is sampled for the next operation. The gain stage 15 includes, for example, a first capacitor 25 and a second capacitor 27. The first capacitor 25 receives the analog signal _VIN in the first period T1 and D / A in the second period T2. It is connected between the conversion circuit 21 and the input 23a of the operational amplifier circuit 23, and is connected between the output 23b of the operational amplifier circuit 23 and the D / A conversion circuit 21 in the third period T3. The second capacitor 27 receives the analog signal _VIN in the first period T1, and is connected between the input 23a and the output 23c of the operational amplifier circuit 23 in the second and third periods T2 and T3.

The A / D conversion comparison circuit 17 provides a digital signal _SDIG having a predetermined expression (for example, redundant binary expression) corresponding to the signal from the output 23b of the gain stage 23. The logic circuit 19 generates a control signal S _CONT in response to the digital signal _SDIG . The D / A conversion circuit 21 provides a voltage signal −V _R , + V _R or zero to the input 15 c of the gain stage 23 according to the control signal S _CONT . The digital circuit 12 stores a digital value for a conversion error caused by the gain stage 15 and corrects the conversion error to a bit string composed of the digital value _SDIG from the A / D conversion comparison circuit 17. A correction digital value S _OUT corresponding to the analog signal _VIN is generated. The conversion error includes at least one of a mismatch error of the capacitance value of the capacitor of the gain stage 15 and a finite gain error of the operational amplifier circuit 15.

  The gain stage 15 repeats the operations in the second and third periods T2 and T3 in the fourth period T4. According to the cyclic A / D converter 11, a digital value having a desired number of bits can be obtained repeatedly and a desired higher number of bits can be corrected.

The A / D conversion comparison circuit 17 provides the digital signal _SDIG in the first and third periods T1 and T3. The D / A conversion circuit 21 provides the voltage signal S _{A / D} to the input 15c of the gain stage 15 in the second period T2. In the second period T2, an arithmetic value is generated at the output 23b of the operational amplifier circuit 23 and A / D conversion is performed. In the third period T3, the arithmetic value generated at the output of the operational amplifier circuit is Sampling for computation. Since the gain stage 15 uses a single operational amplifier circuit 23 for cyclic A / D conversion, a circuit for correcting conversion errors is simplified.

  The clock signal for the switch shown in FIG. 3 and the clock signal shown in the timing chart of FIG. 4 are generated by a clock generator 35.

ゲインステージのディジタル信号は「−１」、「０」、「＋１」の３値を取るので、一ゲインステージあたり１．５ビットのＡ／Ｄ変換を行っていると考えることができる。 Reference values + V _R / 4 and −V _R / 4 are supplied to the comparators 17 a and 17 b in the A / D conversion circuit 17. As shown in FIG. 5, the A / D conversion circuit 17 outputs digital values (+1, 0,...) To the output value V _O generated at the output 15 b of the gain stage 15 for three input voltage V _i regions. -1) is assigned. The output 15b of the gain stage 15 is connected to the capacitor end 27b.

Since the digital signal of the gain stage takes the three values “−1”, “0”, and “+1”, it can be considered that 1.5-bit A / D conversion is performed per gain stage.

The logic circuit 19 generates control signals φ ₀ , φ _P , and φ _N for controlling the first to third switches 51a to 51c, respectively. The values of the digital signals D1, D0 determine which of the control signals φ ₀ , φ _P , φ _N is active. A ternary A / D conversion is performed on these three areas to assign digital codes of “−1”, “0”, and “+1”. The first code is the most significant digit (MSB).

The D / A converter 21 provides a predetermined voltage corresponding to the control signals φ ₀ , φ _P , and φ _N to the capacitor end 25 b and the capacitor end 27 b in the gain stage 15. The D / A converter 21 has an output 21 a connected to the input 15 c of the gain stage 15. The first voltage source 49a provides a voltage + _{V R.} Second voltage source 49b provides a voltage -V _R. The output of the first voltage source 49a is connected to the output 21a via the switch 51a, and the output of the second voltage source 49b is connected to the output 21a via the switch 51b. The output 21a is connected to the ground via the switch 51c.

That is, the output of the A / D conversion circuit 17 provides a redundant digital code, and in response to the redundant digital code, the control circuit 19 generates a control signal S _CONT for controlling the D / A conversion circuit 21. To do. For example, in order to obtain an A / D conversion value having a resolution of 12 bits in the cyclic A / D conversion operation, 11 cyclic operations are required.

According to the N-bit A / D converter 4, the digital circuit 12 is stored in the gain stage 23 and uses a digital value for a conversion error caused by the gain stage 23, and the A / D conversion comparison circuit 17. Since the conversion error correction is directly performed on the digital signal _SDIG from, a corrected digital value _SOUT corresponding to the analog signal _VIN is obtained. Further, since the gain stage 15 uses a single operational amplifier circuit 23 for cyclic A / D conversion, a circuit for correcting conversion errors is simplified. The configuration of the cyclic A / D converter 11 includes one gain stage or two gain stages.

  In the cyclic A / D converter including one gain stage, the analog signal Vin is received at one end 25a, 27a of the first and second capacitors 25, 27 in the first period T1, and the other end 25b is The operational amplifier circuit 23 is connected to a first input (for example, an inverting input) 23a. Since the second input 23c (for example, non-inverting input) of the operational amplifier circuit 23 is connected to the ground (virtual ground in the fully differential configuration), the input 23a and the output 23b of the operational amplifier circuit 23 are connected. The potential of the other end 25b is substantially equal to the potential of the input 23c of the operational amplifier circuit 23. In the second period T2, one end 25a of the first capacitor 25 is connected to the D / A conversion circuit 21, and the other end 25b is connected to the input 23a of the operational amplifier circuit 23. One end 27 a of the second capacitor 27 is connected to the output 23 c of the operational amplifier circuit 23, and the other end 27 b is connected to the input 23 a of the operational amplifier circuit 23. In the third period T3, one end 25a of the first capacitor 25 is connected to the output 23b of the operational amplifier circuit 23, and the other end 25b is connected to the ground. One end 27 a of the second capacitor 27 is connected to the output 23 c of the operational amplifier circuit 23, and the other end 27 b is connected to the input 23 a of the operational amplifier circuit 23. That is, in the third period T3, the output 23b of the operational amplifier circuit 23 is connected to one ends 25a and 27a of the first and second capacitors 25 and 27, and the other end 25b is input to the operational amplifier circuit 23. 23a. The main components of the gain stage 15 are a single operational amplifier circuit 23 and first and second capacitors 25 and 27 for cyclic A / D conversion. To be simple.

  Next, an analog signal (for example, a read signal from a pixel of an image sensor) is converted into a digital signal by this operation for explaining the operation of the cyclic A / D converter with reference to FIGS. 3, 4, and 6. A method is provided.

FIG. 6A is a diagram showing connection of main circuit elements in the first sampling step. In the circuit diagram of FIG. 3, the switches 31a, 33, 35a, and 37 are closed in response to clocks φ _sd , φ ₂ , φ ₃ , and φ _s . In response to the clock φ ₃ _B, the switch 35b is opened. Open the other switches 39 and 41. In the first period T1, the capacitor end 25a is connected to the input 15a via the switch 31a, and the capacitor end 25b is connected to the input 23a of the operational amplifier circuit 23 via the switch 33. The capacitor end 27 a is connected to the input 15 a via the switch 35 a, and the capacitor end 27 b is connected to the input 23 a of the operational amplifier circuit 23. The charge Q 1 corresponding to the signal _VIN is sampled in the first capacitor 25 via the switch 31. Further, the charge Q2 corresponding to the signal _VIN is also stored in the second capacitor 27 via the switch 35a.

The A / D conversion comparison circuit 17 compares the signal _VIN with the first and second reference values (reference values −V _R / 4 and + V _R / 4 in the comparators 17a and 17b) and outputs a digital value. Is generated. That is, the first A / D conversion operation is performed using the two comparators 17a and 17b to generate the digital signal _SDIG .

と表される。キャパシタンス比Ｃ_２／Ｃ_１＝１であり、シンボルＤは、最初のＡ／Ｄ変換値に対応したディジタル値に応じて決定される値であり、（＋１、０、−１）のいずれかである。このステップにおいて、Ａ／Ｄ変換器の基本演算動作を行う。基本演算動作としては、サンプルされた信号を２倍増幅し、Ｄ／Ａ変換回路からの電圧信号をゲインステージに印加する。 FIG. 6B is a diagram showing connection of main circuit elements in the A / D conversion step. In the circuit diagram of FIG. 3, the switches 33 and 35b responding to the clocks φ ₂ and φ ₃ _B are closed. The other switches 31a, 35a, 37, 39, 41 are opened. In the third period T3, the capacitor end 25b is connected to the inverting input 23a of the operational amplifier circuit 23. The D / A conversion circuit 21 applies a voltage signal to one end 25 a of the capacitor 25. The voltage signal S _{A / D} from the D / A conversion circuit 21 is determined according to a digital value corresponding to the first A / D conversion value. In response to this application, the first and second charges Q1 and Q1 are rearranged to generate a calculated value at the output 23b of the operational amplifier circuit 23. Voltage _{V O} of the output 23b of the operational amplifier circuit 23,

It is expressed. The capacitance ratio C ₂ / C ₁ = 1, and the symbol D is a value determined according to the digital value corresponding to the first A / D conversion value, and is any one of (+1, 0, −1) is there. In this step, the basic arithmetic operation of the A / D converter is performed. As a basic arithmetic operation, the sampled signal is amplified twice and the voltage signal from the D / A conversion circuit is applied to the gain stage.

FIG. 6C is a diagram showing connection of main circuit elements in the second sampling step. In the circuit diagram of FIG. 3, the switches 39, 41, and 35b that respond to the clocks φ ₁ , φ _1d , and φ ₃ _B are closed. The other switches 31a, 35a, 33, 37 are opened. The third period T3, connect the capacitor terminal 25a to the output 23b of the operational amplifier circuit 23, by connecting the capacitor terminal 27a to the output 23b of the operational amplifier circuit 23, the first and the charges corresponding to the calculated value _{V O} Store in the second capacitors 25, 27. A signal for subsequent A / D conversion for the lower bits can be stored in the capacitors 25 and 27. Further, the signal V _O is compared with the first and second reference values (reference values −V _R / 4 and V _R / 4 in the comparators 17a and 17b) to generate a digital value. That is, the A / D conversion operation for the next bit of the MSB is performed using the two comparators 17a and 17b.

であり、キャパシタンス比Ｃ_２／Ｃ_１＝１であり、シンボルＤ_０は、Ａ／Ｄ変換値に対応したディジタル値に応じて決定される（＋１、０、−１）値のいずれかである。所望の回数の繰り返しにより、所望の分解能の多ビットのＡ／Ｄ変換を行うことができる。 In this method, the A / D conversion step and the second sampling step can be repeated. In each A / D conversion step in the repetition, the output of the operational amplifier circuit 23 is

And the capacitance ratio C ₂ / C ₁ = 1, and the symbol D ₀ is one of the (+1, 0, −1) values determined according to the digital value corresponding to the A / D conversion value. . By repeating the desired number of times, multi-bit A / D conversion with a desired resolution can be performed.

Referring again to FIG. 2, the digital circuit 12 is shown. As described above, the digital circuit 12 is used to directly correct the conversion error caused by the gain stage 23 on the digital signal _SDIG from the A / D conversion comparison circuit 17 to respond to the analog signal _VIN . The corrected digital value S _OUT is obtained.

となる。
Ｖ_Ｏ／Ｖ_Ｒ＝（２＋ｅ_ｍ）×Ｖ_ＩＮ／Ｖ_Ｒ−（１＋ｅ_ｍ）×Ｄ_０において、値Ｖ_Ｏ／Ｖ_ＲをＡ／Ｄ変換したときに得られるディジタル値Ｘ_１を表すと、

とあり、ここで、シンボルＸ_０は、入力信号Ｖ_ＩＮをディジタル値に変換したときの、ミスマッチ誤差を含まない真値である。誤差は（Ｘ_０−Ｄ_０）×ｅ_ｍである。 このＡ／Ｄ変換において、ディジタル値Ｘ_１に対するミスマッチ起因誤差Ｅ_１は、

である。ここで、シンボルＥ_ｍは、ミスマッチをディジタル値として測定した値である。
式（６）は、真値Ｘ_０が得られれば、この誤差を正確に計算できることを示している。しかし、実際にはミスマッチ誤差を含むＡ／Ｄ変換値を用いることになるが、これに含まれる誤差が十分小さければ、ディジタル補正を行うための十分な精度で誤差を求めることができる。 The capacitor ratio of the gain stage 15 is desirably 1, but the ratio C ₂ / C ₁ deviates from ₁ due to manufacturing variations and the like. This deviation _{△ C 21 = C 2 -C 1} , e m = △ C 21 / C 1
It expresses. Considering the capacitor mismatch, the output value of the operational amplifier circuit 23 for the input _VIN is

It becomes.
_{V O / V R = (2} + e m) × V IN / V R - In _{(1 + e m) × D} 0, to represent the digital value _{X 1} obtained values _V O / _{V R} when converted A / D,

That there is, where the symbol X ₀ is the time obtained by converting the input signal V _IN to a digital value, the true value does not contain a mismatch error. Error is _{(X 0 -D 0) × e} m. In this A / D conversion, the mismatch caused error _{E 1} for the digital value _{X 1} is

It is. Here, the symbol E _m is a value obtained by measuring the mismatch as a digital value.
Equation (6), as long obtain the true values X _0, it indicates that the error can be accurately computed. However, in practice, an A / D conversion value including a mismatch error is used. If the error included in the A / D conversion value is sufficiently small, the error can be obtained with sufficient accuracy for performing digital correction.

が得られる。更に巡回型Ａ／Ｄ変換を行うと、ｉ−１番目には、同様にして

が得られる。このキャパシタミスマッチによる誤差をｉ回目の出力で観測した場合、

である。Ｍ回の巡回Ａ／Ｄ変換を行ったとき誤差の総和は、入力に換算したとき、

と表される。ディジタル値Ｘ_ｉ−１は誤差を含まない値である。しかしながら、誤差を含まない真値は実際には得られないので、ディジタル値Ｘ_ｉ−１をＡ／Ｄ変換によって得られた値で近似する。つまり、

である。式（１１）を用いて式（１０）を整理すると、

となる。この誤差Ｅ_{ｔｏｔａｌ}を計算して、出力ディジタル値から差し引くことにより、ミスマッチ誤差補正が行える。 By subsequent A / D conversion of the lower bits,

Is obtained. Further, when cyclic A / D conversion is performed, the i-1th is similarly performed.

Is obtained. When the error due to this capacitor mismatch is observed at the i-th output,

It is. When M cyclic A / D conversions are performed, the total error is converted into input when

It is expressed. The digital value X _i−1 is a value that does not include an error. However, since a true value that does not include an error cannot actually be obtained, the digital value X _i-1 is approximated by a value obtained by A / D conversion. That means

It is. When formula (10) is rearranged using formula (11),

It becomes. The error E _total is calculated and subtracted from the output digital value, whereby mismatch error correction can be performed.

である。シンボルＧ_ＦＧはループゲインである。式（１３）を書き換えると

となり、ここで、ｅ_ｆｇ＝（Ｃ_１＋Ｃ_２＋Ｃ_ｉ）／（Ｃ_２×Ｇ_ＦＧ）であり、キャパシタンスＣ_ｉは仮想接地点におけるキャパシタンスを示す。これをディジタル値で表すと

となる。同様に、ｉ回目の巡回Ａ／Ｄ変換のディジタル値は、

である。この誤差成分のうち、演算増幅回路の有限利得による誤差をｉ回目のＡ／Ｄ変換値で観測した場合、

である。従って、この誤差として、１回目からＭ回までの各巡回Ａ／Ｄ変換の総和Ｅ_{ｔｏｔａｌ}を求めると、入力に換算すれば次式となる。

これまでの説明から理解されるように、ディジタル値Ｘ_ｉ−１は誤差を含まない値であるが、値Ｘ_ｉ−１をＡ／Ｄ変換によって得られた値で近似する。つまり、

を得る。式（１９）、（２０）を式（１８）に代入して整理すると、

を得る。 Similarly, digital correction when the operational amplifier circuit has a finite gain error will be described. The first round operation is given by the following equation.

It is. Symbol G _FG is a loop gain. Rewriting equation (13)

Where e _fg = (C ₁ + C ₂ + C _i ) / (C ₂ × G _FG ), and capacitance C _i indicates the capacitance at the virtual ground point. This can be expressed as a digital value.

It becomes. Similarly, the digital value of the i-th cyclic A / D conversion is

It is. Among these error components, when the error due to the finite gain of the operational amplifier circuit is observed by the i-th A / D conversion value,

It is. Therefore, when the total E _total of the cyclic A / D conversions from the first time to the M times is obtained as this error, the following equation is obtained when converted to the input.

As understood from the above description, the digital value X _i−1 is a value that does not include an error, but the value X _i−1 is approximated by a value obtained by A / D conversion. That means

Get. Substituting Equations (19) and (20) into Equation (18) and rearranging,

Get.

を得る。 The equation (22) indicating the finite gain error and the equation (12) indicating the mismatch error are combined,

Get.

  This equation shows that error correction can be performed by calculating the error and subtracting it from the output digital value. At this time, the digital value to be used can be cut to a finite digit when the capacitor mismatch error and the finite gain error are sufficiently small. In addition, the accuracy of error correction can be improved by finely adjusting the coefficient value related to the digit that has been cut off.

を得る。図７は、補正式（２３）を実現するディジタル補正回路を用いたときの微分非直線性誤差（補正有り）を示す。一方、図８は、ディジタル補正回路を使用しないときの微分非直線性誤差（補正無し）を示す。このように、利用するディジタル値は、有限の桁（式（２３）では８桁）で打ち切ることができる。打ち切った桁にかかる係数の値を微調整することで、より高い精度で誤差補正を行うことができる。具体的には、８ビット分の補正を行うとき、ディジタル補正値Ｅ_{ｔｏｔａｌ}は、例えば、下記の補正式を用いる。

式（２４−１）を整理すると、式（２４−２）が得られる。 For example, in the 14-bit A / D conversion, when e _m = −0.001 (0.1%) and e _fg = −0.0005 (0.05%), the error correction formula is

Get. FIG. 7 shows a differential nonlinearity error (with correction) when a digital correction circuit that realizes the correction formula (23) is used. On the other hand, FIG. 8 shows a differential nonlinearity error (no correction) when the digital correction circuit is not used. In this way, the digital value to be used can be cut off with a finite number of digits (eight digits in equation (23)). By finely adjusting the value of the coefficient applied to the truncated digit, error correction can be performed with higher accuracy. Specifically, when correcting for 8 bits, the digital correction value E _total uses, for example, the following correction formula.

When formula (24-1) is arranged, formula (24-2) is obtained.

  FIG. 9 shows a differential nonlinearity error (after correction) when a digital correction circuit that realizes the correction formula (24-1) is used. 8 and 9, the use of the correction formula (24) provides a better A / D conversion result than the use of the correction formula (23). FIG. 10 shows the integral nonlinearity error before correction. FIG. 11 shows an integral nonlinearity error when a digital correction circuit that realizes the correction equation (24) is used. From the comparison between FIG. 10 and FIG. 11, the integral nonlinearity error is also set to a sufficiently small value.

  When cyclic A / D conversion is performed in the N-bit A / D converter 4a, an error due to the mismatch is included in each cyclic. However, since the A / D conversion circuit 11 includes only one set of capacitors, the cause of the mismatch is the same. For this reason, the correction formula is expressed by a simple formula. Therefore, there is an advantage that the correction circuit can be simplified. Further, since the A / D conversion circuit 11 includes only one operational amplifier circuit, the cause of the finite gain error is the same. For this reason, the error due to the finite gain of the operational amplifier circuit can also be corrected.

と表すと、

と表される。式（２９）は、複数回の加算（例えば、３回）と複数回の乗算（例えば、２回）で補正値を計算できることを示している。補正のための回路は、例えば図２に示されたディジタル回路によって実現される。 Formula (24-2) is

And

It is expressed. Expression (29) indicates that the correction value can be calculated by a plurality of additions (for example, three times) and a plurality of multiplications (for example, two times). The correction circuit is realized by, for example, a digital circuit shown in FIG.

Referring to FIG. 2, the N-bit A / D converter 4a is provided to process a signal from a certain column. The digital circuit 12 includes a storage circuit 51 (for example, a register that stores digital values D _{0 to} D ₁₃ ) that stores all digital values for each cyclic A / D conversion from the cyclic A / D converter 11. The digital circuit 12 can include a first circuit 53 for correcting a conversion error caused by a mismatch error. The first circuit 53 includes a plurality of first storage circuits (for example, two values for the values X _m1 and X _m2 ) that store a bit string according to the number of correction target bits (for example, the digital values D _{0 to} D ₇ ). Registers) 55a, 55b, a first adder 57 that adds the digital values of the first storage circuits 55a, 55b to generate an added value SUM1 (X _m1 + X _m2 ), and the cyclic A / D converter. second memory circuit 59 (e.g. a register for coefficients E _m), the first digital coefficient value and the addition value for storing a first digital coefficient value for mismatching error correction (e.g., coefficient E _m) in 11 ( X _m1 + X _m2 ) to generate a first multiplication value (E _m × (X _m1 + X _m2 )) to generate a first multiplication value MP1.

Further, the digital circuit 12 can include a second circuit 63 for correcting a conversion error due to a finite gain error. The second circuit 63 includes a plurality of third storage circuits (for example, two values for the values X _g1 and X _g2 ) that store a bit string corresponding to the number of correction target bits (for example, the digital values D _{0 to} D ₇ ). Registers) 65a, 65b, a second adder 67 for adding the digital values of the third storage circuits 65a, 65b to generate an added value SUM2 (X _g1 + X _g2 ), and the above cyclic A / D converter second digital coefficient value for the finite gain error correction in 11 (e.g. factor E _fg) and a fourth storage circuit 69 for storing (e.g. registers for factor E _fg), the second digital coefficient value and the addition value and a _(X g1 _{+ X g2)} and a second multiplier 71 for generating a second multiplier to generate a second multiplier MP2 by multiplying _{(E fg × (X g1 +} X g2)) a.

The digital circuit 12 includes a third adder 73 that adds the first multiplication value MP1 and the second multiplication value MP2 to generate an addition value MP3. The digital circuit 12 includes an adder 77 that adds a digital value (for example, D _{0 to} D ₁₃ ) from the storage circuit 51 and a correction value (for example, coefficient E ₀ ) stored in the storage circuit 75 to generate an addition value SUM4. The added value SUM4 is added to the added value SUM3 by the adder 79. The adder 79 generates a corrected digital value S _OUT . The digital value S _OUT is input to the redundant binary non-redundant binary conversion circuit 7. Non-redundant binary representation digital values are stored in registers. The coefficient E ₀ for this column indicates a value for offset correction. This coefficient E ₀ is effective in removing vertical stripe noise due to offset variations when A / D conversion is performed in an array in a column in a CMOS image sensor.

The digital values X _m1 , X _m2 , X _g1 , X _g2 are, for example, redundant binary numbers, and the addition of the digital values X _m1 + X _{m2 and} the addition of X _g1 + X _g2 are added in redundant binary numbers and An error correction value can be obtained by multiplying each of E _m and E _fg . This arithmetic circuit has a simpler circuit configuration than an arithmetic circuit that directly realizes the original equation (24). Further, the addition in equation (29) can be performed by a redundant binary adder. Since the redundant binary adder has one stage of carry propagation, high-speed addition can be performed. Further, as a multiplier, X _m1 + X _m2 and X _g1 + X _g2 are represented by a redundant binary expression, and coefficients E _m and E _fg are represented by a non-redundant binary expression (for example, a two's complement expression), thereby providing redundant 2 A multiplier can be used that provides an output of a hexadecimal representation. At this time, high-speed multiplication is possible by calculating with redundant binary numbers. Thereafter, the redundant binary number is converted into a non-redundant binary number to obtain a corrected digital output.

Alternatively, the N-bit A / D converter 4a can include a circuit 7 that converts a digital value in a redundant binary representation into a digital value in a non-redundant binary representation prior to digital correction. In the circuit of this example, the cyclic A / D converter 11 is connected to the input of the redundant binary-nonredundant binary representation conversion circuit 7, and the cyclic A / D from the cyclic A / D converter 11. All digital values for each conversion are stored in a register in the conversion circuit 7. The output of this circuit 7 is connected to the input of the digital circuit 12. At this time, the digital operation in the digital circuit 12 is performed using the non-redundant binary expression, and the corrected digital value generated by the digital circuit 12 is expressed in the non-redundant binary expression. The digital circuit 12 includes a storage circuit for storing all digital values from the conversion circuit 7, and digitally corrects these values. The digital values X _m1 , X _m2 , X _g1 , and X _g2 are non-redundant binary numbers, and the addition of the digital values X _m1 + X _{m2 and} the addition of X _g1 + X _g2 is added in a non-redundant binary number and these added values The error correction value can be obtained by multiplying E _m and E _fg respectively. This arithmetic circuit has a simpler circuit configuration than an arithmetic circuit that directly realizes the original equation (24).

In a circuit (as shown in FIG. 1) that processes the digital values from the N-bit A / D converter 4a in the A / D converter array 4 using a single digital circuit 12, the storage of the digital circuit 12 Circuits 59 and 75 (storage circuit 69 if necessary) store correction coefficients E _m and E ₀ (coefficient E _fg if necessary) for each cyclic A / D converter, respectively. Can be memory. These memories provide appropriate coefficients for performing digital correction in response to a control signal from the controller 81. For this purpose, the controller 81 generates a signal (for example, an address signal) in response to the column selection signal _SEXT . The memory in the storage circuits 59 and 75 (the storage circuit 69 if necessary) provides the stored contents at the address corresponding to the address signal. Therefore, appropriate digital correction is provided using the correction coefficient for each cyclic A / D converter.

  When performing error correction of any one of the capacitor mismatch error and the finite gain error, a circuit (for example, a first circuit or a second circuit) that performs a desired correction from the digital circuit 12 shown in FIG. The digital value of the storage circuit 51 may be corrected using the correction value.

  By incorporating such a high-accuracy A / D converter in the peripheral circuit of the CMOS image sensor, a high-performance image sensor with a wider dynamic range and lower noise than a CCD image sensor can be realized. For example, the N-bit A / D converter in this embodiment includes one operational amplifier circuit, two capacitors, a switch for controlling them, one or more comparators, and a register for storing an A / D conversion result Consists of. The digital correction circuit adjusts the arrangement of several bits on the upper side of the A / D conversion result and stores them in two or four registers. By adjusting the arrangement, a calculation for obtaining a correction value can be performed using addition and multiplication in a redundant binary representation (using a redundant binary adder and a redundant binary multiplier). When this is applied to the column of the image sensor, the cyclic A / D converters are arranged in an array in the column. The A / D conversion value (before correction) from the cyclic A / D converter is read out by horizontal scanning. After this reading, the above digital correction is performed to obtain a corrected digital value.

  Conventionally, an A / D converter realized by integrating it in a column of a CMOS image sensor has the highest 12 bits. However, the digital correction of the present invention makes it possible to realize a 14-bit A / D converter. . Recently, a high-speed readout function has attracted attention as a feature that makes CMOS image sensors superior to CCDs. In order to read a high-quality signal with low noise while performing this high-speed reading, A / D conversion in the column is effective. However, the A / D conversion in the column has a resolution of only 10 bits, and at most 12 bits. In the embodiment of the present invention, an A / D converter having a 14-bit resolution can be provided. As a result, the value of the CMOS image sensor can be increased at once.

(Second Embodiment)
The error correction as described above is not limited to the cyclic A / D converter 11, but can be used for the following cyclic A / D converter 11a, for example. FIG. 12 is a diagram illustrating a cyclic A / D converter. FIG. 13 is a drawing showing a timing chart for the cyclic A / D converter. FIG. 14A is a diagram showing connection of main circuit elements in the first sampling step. FIG. 14B is a diagram showing connection of main circuit elements in the A / D conversion and the second sampling step. FIG. 14C is a diagram showing connection of main circuit elements in the second sampling and second A / D conversion steps.

Referring to FIG. 12, the cyclic A / D converter 11 a includes a gain stage 14, an A / D conversion circuit 17, a logic circuit 19, and a D / A conversion circuit 21. The gain stage 14 further includes a third capacitor 45 in addition to the circuit elements included in the gain stage 15. As will be described later with reference to FIGS. 13 and 14, the gain stage 14 can perform the same operation as that of the first period T <b> 1 and the second period T <b> 2 of the gain stage 15. The output 14b of the gain stage 14 is connected to the capacitor end 27b. The A / D conversion circuit 17 assigns a digital value (+1, 0, −1) to the output value V _O generated at the output 14 b of the gain stage 14.

  The third capacitor 45 samples the operation value of the output 23b of the operational amplifier circuit 23 in the second period T2. In the third period T3, the basic arithmetic operation of the A / D converter is performed on the arithmetic value sampled in the third capacitor 45 using the second and third capacitors 327 and 45 and the operational amplifier circuit 23. . In the basic arithmetic operation, the sampled signal is amplified twice and the voltage signal from the D / A conversion circuit is applied to the gain stage. As a result, an operation value corresponding to this basic operation is generated at the output 23b of the operation amplifier circuit 23. The calculated value of the operational amplifier circuit 23 is sampled in the first capacitor 25 in the third period T3.

Since the third capacitor 55 used for sampling is added, the D / A converter 21 includes an additional circuit for applying a voltage signal thereto. The D / A converter 21 provides a predetermined voltage corresponding to the control signals φ ₀₁ , φ _P1 and φ _N1 to the first capacitor end 25a, and controls the control signals φ ₀₂ and φ _{P2 to} the third capacitor end 45a. provides a predetermined voltage corresponding to phi _N2. The D / A converter 21 has outputs 21a and 21b connected to the inputs 14c and 14d of the gain stage 14, respectively. The first voltage source 49a provides a voltage + _{V R.} D / A converter 21, a second voltage source 49b provides a voltage -V _R. In addition to the circuit portion for the capacitor 25, a circuit portion for the capacitor 45 is included. In the D / A converter 21, the output of the first voltage source 49a is connected to the output 21b via the switch 52a, and the output of the second voltage source 49b is connected to the output 21b via the switch 52b. Has been. The output 21b is connected to the ground via the switch 52c.

  The clock signal for the switch shown in FIG. 12 and the clock signal shown in the timing chart of FIG. 13 are generated by a clock generator 36. Although the gain stage 14 includes only one operational amplifier circuit 23, both the basic arithmetic operation and sampling of the A / D converter are performed in each of the second period T2 and the third period T3. . For the operations in the second period T2 and the third period T3, the circuit elements are connected as follows. The gain stage 14 has a substantially two-stage configuration.

With the operation shown in FIGS. 13 and 14, the A / D converter samples the pixel output signal _{VIN in} the period T1.

  In the second period T3, one end 45a of the third capacitor 45 is connected to the non-inverting output 23c via the switch 41b, and the other end 45b is connected to the ground via the switch 39b. In the third period T3, the other end 45b of the third capacitor 45 is connected to the inverting input 23a via the switch 33b, and one end 45a of the third capacitor 45 is connected to the D / A conversion circuit 21. .

The A / D conversion circuit 17 provides the digital signal _SDIG during the first to third periods T1, T2, and T3. The D / A conversion circuit 21 provides a voltage signal to the first capacitor 25 of the gain stage 14 in the second period T2, and supplies a voltage signal to the third capacitor 45 of the gain stage 14 in the third period T3. provide.

  According to the cyclic A / D converter 11a, the signal for the subsequent A / D conversion for the lower bits can be stored in the third capacitor 45 in the second period T2. In addition, during the third period T3, the A / D conversion of the signal stored in the third capacitor 45 is performed, and the output of the operational amplifier circuit 23 is used for the subsequent A / D conversion for further lower bits. The calculated value generated in 23 b is stored in the first capacitor 25. The gain stage 23 repeats the operations in the second and third periods T2 and T3 in the fourth period T4.

FIG. 14A is a diagram showing connection of main circuit elements in the first sampling step. First, in the circuit diagram of FIG. 12, the switch 31a responding to the clock PX_SIG is closed, and the switches 33, 37, and 35a responding to the clocks PHI2, PHIS, and PHI4_B are closed. The other switches 39, 33b, 41b and 35b are opened. In the first period T1, the capacitor end 25a is connected to the column line 8 of the image sensor 1 via the switch 31a, and the charge Q1 corresponding to the signal _VIN is sampled in the first capacitor 25. The non-inverting input 23c of the operational amplifier circuit 23 is connected to the ground. The charge Q2 corresponding to the signal _VIN is also stored in the second capacitor 27 via the switch 35a. These calculated values are compared with reference values −V _R / 4 and + V _R / 4 using the comparator 17, and the comparator 17 generates a digital value. This A / D conversion operation provides a digital value for the MSB.

FIG. 14B is a diagram showing connection of main circuit elements in the second sampling and the first A / D conversion step. In the circuit diagram of FIG. 12, the switches 33, 39b, 35b, and 41b that respond to the clocks PHI2, PHI4, and PHI5 are closed. The other switches 31a, 39, 41, and 35a are opened. In the second period T2, the capacitor end 25b is connected to the inverting input 23a via the switch 33. By applying a voltage signal corresponding to the digital value to the terminal 25a of the first capacitor 25 via the input 14c, the charges Q1 and Q2 are rearranged to generate an operation value on the non-inverted output 23b. As a basic arithmetic operation, the sampled signal is amplified twice and the voltage signal from the D / A conversion circuit is applied to the gain stage. The calculated value is compared with reference values −V _R / 4 and + V _R / 4 using the comparators 17a and 17b to generate a digital value, and an A / D conversion operation is performed.

FIG. 14C is a diagram showing connection of main circuit elements in the third sampling and second A / D conversion steps. In FIG. 12, the switches 33b, 39, 35b, 41 responding to the clocks PHI1, PHI2, PHI3, PHI4 are closed. The other switches 31a, 35a, 33, 39b, 37 are opened. In the third period T3, the capacitor terminal 45b is connected to the inverting input 23a via the switch 33b. By applying a voltage signal corresponding to the digital value to the terminal 45a of the third capacitor 45 via the input 14d, charge rearrangement is performed, and an arithmetic value is generated in the non-inverted output 23b. That is, the basic arithmetic operation of the A / D converter is performed. The calculated value is compared with reference values −V _R / 4 and + V _R / 4 using the comparators 17a and 17b to generate a digital value, and an A / D conversion operation is performed.

Similarly, the digital value sequence of the A / D converter 11a according to the embodiment of the present invention can be subjected to the above digital correction to obtain a corrected digital value. In the digital circuit 12, the number of several storage circuits that store a bit string corresponding to the number of bits to be corrected is changed as necessary. Further, the number of adders and multipliers for calculating these stored values is also changed as necessary. For example, the digital circuit 12 receives a correction target bit of the cyclic A / D conversion digital value from the cyclic A / D converter 11 and performs a first operation on a plurality of bit strings generated from the correction target bit. A first calculation value is generated, and a second calculation value is generated on the first calculation value by performing a second calculation on the digital coefficient value. The digital coefficient value is prepared according to the conversion error to be corrected. Examples of the correction target include a finite gain of the operational amplifier circuit and / or a mismatch between a plurality of capacitor pairs. Explaining by way of example, the A / D converter 11a alternately uses two sets of capacitors for A / D conversion. Accordingly, two capacitors corresponding to two sets of capacitors due to capacitor mismatch are correspondingly used. Coefficients E _m1 and E _m2 are prepared. These coefficients are also stored in the memory, and are selected in accordance with signals indicating odd-numbered and even-numbered cyclic A / D conversion. This signal is also generated by the controller 81. With these changes, an A / D converter having a 14-bit resolution can be provided as an A / D converter realized by being integrated in a column of a CMOS image sensor.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. For example, although a plurality of cyclic A / D conversion circuits are connected to a single digital circuit via a data register in FIG. 1, a digital circuit may be provided for each cyclic A / D conversion circuit. . Further, for example, a fully differential circuit can be used for a circuit configured using a single-ended circuit. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1 is a diagram illustrating an image sensor. FIG. 2 is a diagram illustrating an N-bit A / D converter. FIG. 3 is a diagram showing a cyclic A / D converter. FIG. 4 is a diagram showing a timing chart for the cyclic A / D converter. FIG. 5 is a diagram showing the relationship between the three input voltage V _i regions of the A / D conversion circuit and the assigned digital values (+1, 0, −1). FIG. 6 is a diagram showing connection of main circuit elements in the first sampling step, the A / D conversion step, and the second sampling step. FIG. 7 is a drawing showing a differential nonlinearity error (after correction) when a digital correction circuit that realizes the correction formula (23) is used. FIG. 8 is a diagram showing a differential nonlinearity error (before correction) when the digital correction circuit is not used. FIG. 9 is a diagram showing a differential nonlinearity error (after correction) when a digital correction circuit that realizes the correction formula (24) is used. FIG. 10 shows the integral nonlinearity error before correction. FIG. 11 is a drawing showing an integral nonlinearity error when a digital correction circuit that realizes the correction equation (24) is used. FIG. 12 is a diagram illustrating a cyclic A / D converter. FIG. 13 is a timing chart for the cyclic A / D converter. FIG. 14 is a drawing showing connection of main circuit elements in the first sampling step, the A / D conversion and second sampling step, the second sampling and second A / D conversion step.

Explanation of symbols

4a: N-bit A / D converter, 11, 11a: Cyclic A / D converter circuit, 12: Digital circuit, 14, 15: Gain stage, 17: Comparison circuit for A / D conversion, 19: Logic circuit, 21 ... D / A conversion circuit, 23... Operational amplifier circuit, 23a... Input of operational amplifier circuit, 23b... Output of operational amplifier circuit, 23c... Output of operational amplifier circuit, 25. , 55 ... third capacitor, 35, 36 ... clock generator, 51, 55a, 55b, 59, 65a, 65b, 69 ... memory circuit, 53 ... first circuit, 63 ... second circuit, 57, 67 73, 77, 79 ... adders, 61, 71 ... multipliers, S _DIG ... digital signals in redundant binary representation, S _CONT ... control signals, -V _R , + V _R ... voltage reference signals, V _IN ... analog signals , _{S OU} ... correction digital value

Claims (4)

An N-bit A / D converter capable of correcting a conversion error caused by a circuit element,
A gain stage including an input that receives an analog signal, an output, and an operational amplifier circuit having an input and an output; an A / D conversion comparison circuit that provides a digital signal according to a signal from the output of the gain stage; A cyclic A / D conversion circuit including a logic circuit that generates a control signal in response to a digital signal, and a D / A conversion circuit that provides a voltage signal to the gain stage according to the control signal;
The digital signal is corrected for the conversion error using a digital coefficient stored for the conversion error caused by the gain stage and a bit string generated from the digital signal from the cyclic A / D conversion circuit. And a digital circuit for generating a corrected digital value by
The conversion error includes at least one of a mismatch error of a capacitance value of a capacitor of the gain stage and a finite gain error of the operational amplifier circuit,
The gain stage includes a first capacitor and a second capacitor, wherein the first capacitor receives the analog signal during a first period and in a second period after the first period. It is connected between the D / A conversion circuit and the input of the operational amplifier circuit, and is connected to the output of the operational amplifier circuit in a third period after the second period. The capacitor receives the analog signal during the first period, and is connected between the input and the output of the operational amplifier circuit during the second and third periods ,
The output of the operational amplifier circuit is connected to one end of the first capacitor in the third period;
The gain stage further includes a third capacitor connected to the output of the operational amplifier circuit during the second period and connected to the first input of the operational amplifier circuit during the third period. ,
The digital circuit includes a first circuit for correcting a conversion error caused by the mismatch error, and a second circuit for correcting a conversion error caused by the finite gain error,
The first circuit includes a plurality of first registers for storing a bit string corresponding to the number of bits to be corrected, a second register for storing a first digital coefficient value for correcting the mismatch error, and the first circuit. A first adder for adding a digital value of one register to generate an added value; and a first multiplier for multiplying the first digital coefficient value by the added value to generate a first multiplied value And
The second circuit includes a plurality of third registers for storing a bit string corresponding to the number of bits to be corrected, a fourth register for storing a second digital coefficient value for correcting the finite gain error, A second adder that adds the digital values of the third register to generate an added value; and a second adder that multiplies the second digital coefficient value and the added value to generate a second multiplied value. And a multiplier
The digital circuit includes a third adder that adds the first multiplication value and the second multiplication value,
The A / D conversion comparator circuit provides the digital signal in the first to third periods;
The D / A conversion circuit provides the voltage signal to the first capacitor of the gain stage during the second period, and supplies the voltage to the third capacitor of the gain stage during the third period. An N-bit A / D converter characterized by providing a signal . An N-bit A / D converter capable of correcting a conversion error caused by a circuit element,
A gain stage including an input that receives an analog signal, an output, and an operational amplifier circuit having an input and an output; an A / D conversion comparison circuit that provides a digital signal according to a signal from the output of the gain stage; A cyclic A / D conversion circuit including a logic circuit that generates a control signal in response to a digital signal, and a D / A conversion circuit that provides a voltage signal to the gain stage according to the control signal;
The digital signal is corrected for the conversion error using a digital coefficient stored for the conversion error caused by the gain stage and a bit string generated from the digital signal from the cyclic A / D conversion circuit. And a digital circuit for generating a corrected digital value by
The conversion error includes at least one of a mismatch error of a capacitance value of a capacitor of the gain stage and a finite gain error of the operational amplifier circuit,
The gain stage includes a first capacitor and a second capacitor, wherein the first capacitor receives the analog signal during a first period and in a second period after the first period. It is connected between the D / A conversion circuit and the input of the operational amplifier circuit, and is connected to the output of the operational amplifier circuit in a third period after the second period. The capacitor receives the analog signal during the first period, and is connected between the input and the output of the operational amplifier circuit during the second and third periods ,
The output of the operational amplifier circuit is connected to one end of the first capacitor in the third period;
The gain stage further includes a third capacitor connected to the output of the operational amplifier circuit during the second period and connected to the first input of the operational amplifier circuit during the third period. ,
The digital circuit includes a first circuit for correcting a conversion error caused by the mismatch error,
The first circuit includes a plurality of first registers for storing a bit string corresponding to the number of bits to be corrected, a second register for storing digital coefficient values for correcting the mismatch error, and the first register. An adder that adds the digital values of each other to generate an added value, and a multiplier that multiplies the digital coefficient value by the added value,
The A / D conversion comparator circuit provides the digital signal in the first to third periods;
The D / A conversion circuit provides the voltage signal to the first capacitor of the gain stage during the second period, and supplies the voltage to the third capacitor of the gain stage during the third period. An N-bit A / D converter characterized by providing a signal . An N-bit A / D converter capable of correcting a conversion error caused by a circuit element,
A gain stage including an input that receives an analog signal, an output, and an operational amplifier circuit having an input and an output; an A / D conversion comparison circuit that provides a digital signal according to a signal from the output of the gain stage; A cyclic A / D conversion circuit including a logic circuit that generates a control signal in response to a digital signal, and a D / A conversion circuit that provides a voltage signal to the gain stage according to the control signal;
The digital signal is corrected for the conversion error using a digital coefficient stored for the conversion error caused by the gain stage and a bit string generated from the digital signal from the cyclic A / D conversion circuit. And a digital circuit for generating a corrected digital value by
The conversion error includes at least one of a mismatch error of a capacitance value of a capacitor of the gain stage and a finite gain error of the operational amplifier circuit,
The gain stage includes a first capacitor and a second capacitor, wherein the first capacitor receives the analog signal during a first period and in a second period after the first period. It is connected between the D / A conversion circuit and the input of the operational amplifier circuit, and is connected to the output of the operational amplifier circuit in a third period after the second period. The capacitor receives the analog signal during the first period, and is connected between the input and the output of the operational amplifier circuit during the second and third periods ,
The output of the operational amplifier circuit is connected to one end of the first capacitor in the third period;
The gain stage further includes a third capacitor connected to the output of the operational amplifier circuit during the second period and connected to the first input of the operational amplifier circuit during the third period. ,
The digital circuit includes a second circuit for correcting a conversion error caused by the finite gain error,
The second circuit includes a plurality of first registers that store a bit string corresponding to the number of correction target bits, a second register that stores a digital coefficient value for correcting the finite gain error, and the first circuit An adder that adds digital values of registers to generate an added value; and a multiplier that multiplies the digital coefficient value and the added value,
The A / D conversion comparator circuit provides the digital signal in the first to third periods;
The D / A conversion circuit provides the voltage signal to the first capacitor of the gain stage during the second period, and supplies the voltage to the third capacitor of the gain stage during the third period. An N-bit A / D converter characterized by providing a signal . The comparison circuit for A / D conversion generates a digital value of redundant binary representation for each conversion,
The digital operation in the digital circuit is performed using a redundant binary representation, and the corrected digital value generated by the digital circuit is represented in a redundant binary representation,
The N-bit A / D converter, a redundant binary representation of the corrected digital value including a circuit for converting the non-redundant binary representation, that in any one of claims 1 to 3, wherein The N-bit A / D converter described.

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