JP5011538B2 - Cyclic analog-digital converter and image sensor device - Google Patents

Description

  The present invention relates to a cyclic analog-to-digital (A / D) converter, an image sensor device, and a method for generating a digital value from an analog value by cyclic A / D conversion.

Non-Patent Document 1 describes a cyclic A / D converter integrated in an image sensor column. Non-Patent Document 2 describes the world's first cyclic A / D converter with 12-bit resolution. This cyclic A / D converter is applied to a CMOS image sensor having a very wide dynamic range. Further, Patent Document 1 describes an A / D conversion array for an image sensor. In the cyclic A / D converter of Non-Patent Document 1, three amplifiers per channel are required together with amplifiers for canceling noise generated by the pixels of the image sensor. Necessary and many amplifiers increase power consumption. On the other hand, the A / D converter disclosed in Patent Document 1 can reduce the number of amplifiers while performing noise cancellation and cyclic A / D conversion.
S. Decker, RD Mcgrath, K. Brehmer, CG Sodini, “A 256 x 256 CMOS imaging array with wide dynamic range pixels and column parallel digital output,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2081-2091, Dec. 1998. M. Mase, S. Kawahito, M. Sasaki, Y. Wakamori, A 19.5b Dynamic Range CMOS Image Sensor with 12b Column-Parallel Cyclic A / D Converters, Dig. Tech. Papers, Int.Solid-Sate Circuits Conf., No. 19.3 (2005). JP 2005-136540 A

By generating ternary digital values by A / D conversion, it is possible to relax the accuracy requirement for the comparison circuit. However, an A / D converter that generates ternary digital values requires two comparators. Moreover, voltage sources (+ V _ref / 4, −V _ref / 4) are necessary for reference voltages used in the internal D / A conversion circuit. In addition to the circuit for this purpose, a wiring area for providing this signal is also required. The circuit configuration of the comparison circuit is also complicated because it generates ternary digital values. Furthermore, since the D / A conversion circuit switches three signals including zero, a code-dependent offset voltage may occur due to this switching, resulting in a decrease in conversion accuracy. Since this A / D converter generates a redundant code, the output of the A / D converter includes a circuit for storing a signal with a bit width approximately twice the number of bits of the non-redundant expression, A circuit for horizontally scanning these signals is required. In an image sensor device in which this A / D converter is integrated with an image sensor, it is necessary to arrange these circuits close to the cell array.

  The present invention has been made in view of such circumstances, and provides a cyclic A / D converter that can relax the accuracy requirement of a comparison circuit without using a ternary digital value. It is an object of the present invention to provide an image sensor device using a cyclic A / D converter, and to provide a method of generating a digital value from an analog value by cyclic A / D conversion.

  One aspect of the present invention is a cyclic A / D converter that performs N (N> M + 1) cyclic operations to generate an M + 1-bit digital value. The cyclic A / D converter includes (a) a gain stage that provides amplification of a predetermined gain G that is less than 2, and (b) an input signal to the cyclic analog-to-digital converter or from the gain stage. A comparison circuit that generates a binary digital value according to the conversion signal, and (c) a D / A conversion circuit that provides a D / A signal according to the control signal from the comparison circuit to the gain stage. The gain stage performs a cyclic operation according to the D / A signal to generate a converted signal.

  In a cyclic A / D converter using a gain stage of twice the gain, when the conversion result exceeds the maximum value or minimum value allowed in the A / D conversion due to the influence of the offset error of the comparison circuit, A large conversion error occurs. On the other hand, according to the cyclic A / D converter of the present invention, since the gain of the gain stage is a predetermined value less than 2, the conversion result exceeds the maximum value or minimum value allowed in the A / D conversion. The accuracy required for the comparison circuit can be relaxed.

  Further, this cyclic A / D converter (d) corrects N digital values from the comparison circuit using a correction coefficient associated with the gain G, and generates a M + 1 bit digital value. Is provided. The conversion error due to the use of a gain stage with a gain of less than 2 generates an additional digital value (N-M-1) that is generated by a relatively small increase in the number of cyclic conversions and a correction associated with the gain G. The A / D conversion digital value (N bits) can be eliminated by correcting the coefficient. As a result, the cyclic A / D converter according to the present invention converts the digital value of the desired number of bits (M + 1). provide.

  In the cyclic A / D converter of the present invention, the correction circuit may include a circuit that generates a product-sum operation value of N digital values and correction coefficients. According to this cyclic A / D converter, a corrected digital value can be generated from a digital value including a conversion error caused by using a gain stage having a gain of less than 2 by a product-sum operation circuit.

  In the cyclic A / D converter of the present invention, the gain stage includes first and second capacitors having a capacitance value that provides a capacitance ratio associated with the gain, and gain due to the capacitance ratio of the first and second capacitors. And an operational amplifier circuit for amplifying the signal. The capacitance ratio provides a gain stage gain of less than 2 with suitable accuracy.

  In the cyclic A / D converter of the present invention, the first capacitor receives an analog signal from the input of the cyclic analog-digital converter during the first period, and the second capacitor after the first period. The second capacitor is connected between the D / A conversion circuit and the input of the operational amplifier circuit during the period, and is connected to the output of the operational amplifier circuit during the third period after the second period. The analog signal can be received during one period and can be connected between the input and output of the operational amplifier circuit during the second and third periods. According to this cyclic A / D converter, the operation of the cyclic A / D converter is provided with a gain defined by the capacitance ratio.

  In the cyclic A / D converter of the present invention, the capacitor value of the first capacitor is smaller than the capacitor value of the second capacitor. According to this cyclic A / D converter, by using a capacitor, a gain of less than 2 is provided to the gain stage with suitable accuracy.

  In the cyclic A / D converter of the present invention, the correction coefficient of the correction circuit may be further associated with a finite gain error of the operational amplifier circuit. According to this cyclic A / D converter, the correction circuit can also reduce errors related to the finite gain error of the operational amplifier circuit. In the cyclic A / D converter of the present invention, the correction coefficient of the correction circuit may be further associated with a capacitance ratio mismatch. According to this cyclic A / D converter, the correction circuit can also reduce errors related to capacitance ratio mismatch.

  In the cyclic A / D converter of the present invention, the correction circuit includes a circuit that generates an M + 1-bit first product-sum operation value and a circuit that generates an N-bit second product-sum operation, and M + 1 The digital value of the bit can be generated from the first and second multiply-accumulate values. According to this cyclic A / D converter, when the error correction of the mismatch of the capacitance ratio is performed, a correction value for digital correction of the error is generated by two product-sum operation values.

  In the cyclic A / D converter of the present invention, the comparison circuit can compare the received signal with a single reference signal. According to this cyclic A / D converter, since the gain of the gain stage is less than 2, even if a comparison circuit that compares the input signal with a single reference signal is used, the conversion result is acceptable in the A / D conversion. Never exceed the maximum or minimum value.

  In the cyclic A / D converter of the present invention, the gain stage includes a fully differential circuit and provides a non-inverted signal and an inverted output signal, and the comparison circuit receives the non-inverted output signal and the inverted output signal. A differential circuit may be included. According to this cyclic A / D converter, since the gain of the gain stage is less than 2, even if a differential circuit that receives a non-inverted output signal and an inverted output signal is used as a comparison circuit, the conversion result is A / D converted. Does not exceed the maximum or minimum value allowed.

  Another aspect according to the present invention is an image sensor device. The image sensor device includes a cell array of image sensor cells and a circuit array of any one of the cyclic analog-digital converters described above, and the cyclic analog-digital converter receives signals from at least one column of the image sensor cells. Process.

  In the image sensor device of the present invention, the image sensor cell provides a first signal corresponding to the reset level and a second signal corresponding to the signal level, and the gain stage has a non-inverting input and an inverting input and all The gain stage includes one of the first and second signals from the image sensor cell at the non-inverting input and the other of the first and second signals from the image sensor cell. Is received at the inverted input. According to this image sensor device, the reset level of the image sensor cell can be canceled.

  Another aspect of the present invention is a method for generating a digital value from an analog value by cyclic A / D conversion. In this method, (a) a cyclic A / D conversion is performed using a gain stage having a gain G of less than 2 of a cyclic A / D converter, and N bits including a nonlinear error due to a gain of less than 2 are included. Generating a digital value; and (b) M + 1 bit (N> M + 1) digital with improved non-linear error by applying correction using a coefficient associated with the gain G to the N bit digital value. Generating a value.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, there is provided a cyclic analog-digital converter that enables a circuit configuration without using ternary digital values. In addition, according to the present invention, an image sensor device using the cyclic analog-digital converter is provided. Furthermore, according to the present invention, there is provided a method for generating a digital value from an analog value by cyclic A / D conversion.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the cyclic A / D converter and the image sensor device of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

FIG. 1 is a diagram schematically showing a cyclic A / D converter. FIG. 2 is a diagram showing the input / output relationship of the cyclic A / D converter. The cyclic A / D converter 11 performs N (N> M + 1) cyclic operations to generate a digital value of M + 1 bits. The cyclic A / D converter 11 includes a gain stage 13 that provides amplification of a predetermined gain G that is less than 2, a comparison circuit 15, and a D / A conversion circuit 17. Comparator circuit 15 generates a digital value _{S DIG} binary depending on the conversion signal _{S CONV} from the input signal _{V IN,} or gain stage 13 to the cyclic A / D converter 11. The D / A conversion circuit 17 provides the D / A signal S _{D / A} corresponding to the control signal S _CONT from the comparison circuit 15 to the gain stage 13. The gain stage 13 generates a conversion signal S _CONV by performing a cyclic operation according to the D / A signal _{SD / A.}

In a cyclic A / D converter using a gain stage having a gain of 2 times, the conversion result is allowed in the A / D conversion due to the influence of the offset error of the comparison circuit (that is, the range between the maximum value and the minimum value). ), A large conversion error occurs. On the other hand, according to the cyclic A / D converter 11, the gain of the gain stage 13 is a predetermined value less than 2 as shown in FIGS. 2 (A) and 2 (B). Even when the characteristic indicated by (1) is shown, the maximum or minimum value allowed in the A / D conversion is not exceeded, and the range _VFR is entered. Therefore, the required accuracy for the comparison circuit 15 can be relaxed. For example, the burden for reducing the offset error in the comparison circuit 15 is reduced. In addition, the frequency of occurrence of large errors due to deviation from the range V _FR is reduced. A preferable gain range is 1.95 or less in consideration of variation, and is preferably 1.6 or more in consideration of ease of realization of digital correction.

  The cyclic A / D converter 11 includes a correction circuit 19 that receives N digital values from the comparison circuit 15. The correction circuit 19 corrects the N digital values from the comparison circuit 15 using the correction coefficient associated with the gain G to generate an M + 1 bit digital value. The conversion error due to the use of the gain stage 13 with a gain of less than 2 produces an additional digital value (N−M) and uses an A / D converted digital value (N bits) with a correction factor associated with the gain G. ) Can be removed by correcting. The number of extra cyclic transformations for the additional digital values is relatively small, as will be understood from the following description. As a result of this correction, the cyclic A / D converter 11 provides a digital value having a desired number of bits (M + 1).

The comparison circuit 15 includes a comparator 21 and a control circuit 23 that generates a control signal S _CONT (φ _N , φ _P ) of the D / A conversion circuit from the output signal _SDIG of the comparator 21. Control circuit 23, AND circuit 23a receiving the output signal _{S DIG} and an external signal φc2 the comparator 21, and an inverter 23b for generating an inverted signal of the output signal of the comparator 21, the output signal _{S DIG} comparator 21 receiving an inverted signal _{_S DIG} and the external signal phi _c2 and a logical product circuit 23c. The AND circuits 23a and 23b are controlled by an external signal _φc2 .

  The gain stage 13 includes first and second capacitors 25 and 27 (third and fourth capacitors 35 and 37) and an operational amplifier circuit 29 as main circuit elements. The gain stage 13 includes an inverting input 13a (non-inverting input 13c) that is selectively connected to the capacitors 25 and 27 (35, 37), and a non-inverting output 13b (inverting output 13d) that provides a calculated analog signal. including. The gain stage 13 includes a number of switches responsive to timing signals from the clock generation circuit 31, which will be described later. These switches are realized by, for example, MOS analog switches.

The D / A conversion circuit 17 includes a plurality of switches 33a, 33b, 33c, and 33d that operate in response to the control signal S _CONT from the comparator 21. The switch 33 a is connected between the voltage source 39 a that provides the voltage V _RN and the first D / A input 13 e of the gain stage 13. Switch 33b is connected between the first D / A input 13e of the voltage source 39b and the gain stage 13 which provides a voltage _{V RP.} The switch 33c is connected between the voltage source 39b and the second D / A input 13f of the gain stage 13. The switch 33d is connected between the voltage source 39a and the second D / A input 13f of the gain stage 13. Switch 33a, 33c is adapted to operate in response to the clock phi _N, switch 33b, 33d operates in response to the clock phi _P.

The capacitance ratio (C ₁ / C ₂ ) of the first and second capacitors 25 and 27 is related to the gain G, and the gain stage 13 performs signal amplification at the gain G based on the capacitance ratio by the operational amplifier circuit 29. To do. Using a capacitance ratio of two capacitors provides a gain stage gain G of less than 2 with good accuracy.

FIG. 3 is a timing chart for the cyclic A / D converter. The clock generation circuit 31 generates a representative clock signal shown in FIG. Schematically, in the first period _{T 1,} the first capacitor 25 (third capacitor 35) receives the analog signal _V IP from the input 13a of the gain stage 13 (input 13c) _{(V IN)} . In the second period T ₂ after the _first period T ₁ , the first capacitor 25 (third capacitor 35) is connected to the D / A conversion circuit 17 and the inverting input 29 a (the operational amplifier circuit 29). Non-inverting input 29c). Furthermore, the first capacitor 25 (third capacitor 35) is connected to the non-inverting output 29b of the operational amplifier circuit 29 (the inverted output 29d) the third period _{T 3} after the second period _{T 2} . The first period _{T 1,} the second capacitor 27 (fourth capacitor 37) receives the analog signal _V IP _{(V IN).} In the second and third periods T ₂ and T ₃ , the second capacitor 27 (fourth capacitor 37) is connected to the non-inverting input 29a (inverting input 29c) and the inverting output 29b (non-inverting) of the operational amplifier circuit 29. Output 29b). A cyclic A / D conversion operation is provided using a gain stage 13 with a gain G defined by a capacitance ratio (C ₁ / C ₂ ) of less than ₁ .

In the cyclic A / D converter 11, the capacitor value of the capacitor 25 (capacitor 35) is smaller than the capacitor value of the capacitor 27 (capacitor 37). In the example circuit shown in FIG. 1, the capacitor value C ₁ (= 7C) of the capacitor 25 (capacitor 35) is smaller than the capacitor value C ₂ (= 8C) of the capacitor 27 (capacitor 37). The capacitor ratio C ₁ / C ₂ = 7/8 = 0.875.

In the cyclic A / D converter 11, the comparison circuit 15 can compare the input signals V _IP and S _CONV from the input of the cyclic analog-digital converter or the output of the gain stage 13 with a single reference signal. it can. Since the gain G of the gain stage 13 is less than 2, even if a comparison circuit that compares the input signals V _IP and S _CONV with a single reference signal is used, the conversion result is the maximum value allowed in the A / D conversion or The minimum value is never exceeded. Alternatively, the comparison circuit 15 may include a differential circuit for receiving the non-inverted output signals V _OP and the inverted output signal V _ON from the gain stage 13 which includes a fully differential circuit. Even if this differential circuit is used as a comparison circuit, the conversion result does not exceed the maximum value or minimum value allowed in the A / D conversion.

  FIG. 4 is a circuit diagram of an example comparison circuit. The comparison circuit 15 includes a comparator 61 and a latch circuit 63. The comparator 61 includes a differential unit 61b including transistors MN1 and MN2 that receive input signals, a current source 61a that includes a transistor MN5 that receives a bias signal Vbn, a first load unit 61c, and a second load unit 61d. And an equalizing unit 61e. The sources of the transistors MN1 and MN2 are connected to the common node, and the common node is connected to the current source 61a. The drains of the transistors MN1 and MN2 of the differential unit 61b are respectively connected to the drains of the transistors MP1 and MP2 of the first load unit 61c, and the transistors MP1 and MP2 are cross-coupled. The transistors MP1 and MP2 of the first load unit 61c are connected to the second load unit 61d including the transistors MN3 and MN4, and the transistors MN3 and MN4 are cross-coupled. The transistors MN1 and MN2 of the differential unit 61b are connected to a pair of output nodes that provide signals Vop and Von, respectively, and the pair of outputs are equalized by an equalization unit 61e that responds to the control signal φc. The The transistor MP3 of the equalizing unit 61e is connected between a pair of output nodes. The comparator 61 includes transistors MN6 and MN7 that operate in response to the control signal φc. The transistor MN6 sets the second load units 61c and 61d to the power down mode, and the transistor MN7 sets the differential unit 61b to the power down mode. To. The output of the comparator 61 is connected to the input of the latch circuit 63. The latch circuit 63 includes a cross-coupled multi-input logic gate. When using the CMOS technology, for example, two NAND (NAND) gates can be used.

Referring to FIG. 5, a circuit connection by a differential circuit configuration for a cyclic A / D conversion operation is shown. From the following description, it is understood that the cyclic A / D conversion operation can be performed by a single-ended circuit configuration and also by a fully differential configuration. The circuit elements of FIG. 5 are labeled with the corresponding circuit element reference numbers shown in FIG. The circuit connections in the parts (a), (b) and (c) of FIG. 5 correspond to the first, second and third periods T ₁ , T ₂ and T ₃ shown in FIG. 3, respectively. To do.

Referring to part (a) of FIG. 5, the circuit connections in period T ₁ corresponding to the sampling is shown. In response to the clocks φ _S , φ ₀ , φ ₂ , the switches 41a (41b), 43a (43b), 45a (45b), 47a (47b) are closed. In response to the clocks φ ₃ and φ ₁ , the switches 49a (49b), 51a (51b) and 53 are opened.

In the first period T1, _one end 25a (35a) of the capacitor 25 (capacitor 35) switches the analog signal V _IP (V _IN ) from the input 13a (input 13c) of the gain stage 13 to the switch 41a (41b). Receive through. One end 27a (37a) of the capacitor 27 (capacitor 37) receives the analog signal V _IP (V _IN ) via the switch 43a (43b). The other end 25b (35b) of the capacitor 25 (capacitor 35) is connected to a non-inverting input 29a (inverting input 29c) of the operational amplifier circuit 29 via a switch 47a (47b). In the circuit connection of part (a) in FIG. 5, the non-inverting input 29c of the operational amplifier circuit 29 is connected to the ground (virtual ground). The inverting input 29a (non-inverting input 29c) of the operational amplifier circuit 29 is connected to the inverting output 29b (inverted output 29b) via the switch 45a (45b), and the operational amplifier circuit 29 is reset. The potential of the other end 25b (25b) of the capacitor 25 (capacitor 35) also becomes the ground potential under ideal conditions where the gain of the operational amplifier circuit 29 is infinite.

The comparison circuit 15 receives the analog signal V _IP (V _IN ) via the switch 43a (43b) and generates a digital value _SDIG corresponding to the received analog signal. In response to the control signals φ _P and φ _N , the switches 33a to 33d of the D / A conversion circuit 17 are opened. The comparator 15 is operated to perform 1-bit A / D conversion on the input signal V _IP (V _IN ) to generate a signal _SDIG . This is the value of the most significant digit (MSB) of A / D conversion.

Referring to part (b) of FIG. 5, the circuit connections in the period T ₂ of the order of the first arithmetic is shown. In response to the clocks φ ₃ and φ ₂ , the switches 49a (49b) and 47a (47b) are closed. In response to the clocks φ _S , φ ₀ , φ ₁ , the switches 41a (41b), 43a (43b), 45a (45b), 51a (51b, 53) are opened.

Ｄ／Ａ変換回路１７は、キャパシタ２５（キャパシタ３５）の一端２５ａ（３５ａ）にＤ／Ａ信号Ｓ_Ｄ／Ａを加える。ゲインステージ１３は、アンプの有限利得誤差、キャパシタミスマッチやオフセット電圧を無視できるとき、式（２）に従って動作する。

ここで、Ｖ_Ｒ＝Ｖ_ＲＰ−Ｖ_ＲＮである。ゲインステージ１３の利得は２未満であるので、キャパシタンス比Ｃ_１／Ｃ_２は１未満のある値である。演算増幅回路２９の非反転出力２９ｃには、新たな値Ｖ_Ｏが生成される。 The second period _{T 2,} the other end 27b of the capacitor 27 (capacitor 37) (37b) is connected to the inverting input 29a of the operational amplifier circuit 29, one end 27a (37a) is non-inverted output 29b of the operational amplifier circuit 29 Are connected to each other via a switch 49a (49b). The other end 25b (35b) of the capacitor 25 (capacitor 35) is connected to the inverting input 29a of the operational amplifier circuit 29 via a switch 47a (47b). The D / A conversion circuit 17 opens and closes the switches 33a to 33d in response to the control signals [phi] _P and [phi] _N, and operates according to the equation (1).

The D / A conversion circuit 17 applies a D / A signal S _{D / A} to one end 25a (35a) of the capacitor 25 (capacitor 35). The gain stage 13 operates according to the equation (2) when the finite gain error of the amplifier, capacitor mismatch, and offset voltage can be ignored.

Here, V _R = V _RP −V _RN . Since the gain of the gain stage 13 is less than 2, the capacitance ratio C ₁ / C ₂ is a value less than 1. A new value V _O is generated at the non-inverted output 29 c of the operational amplifier circuit 29.

  The gain G is, for example, 2-0.125 = 1.875. The relationship between input and output at a gain of less than 2 is shown in FIG. As a result, as with the ternary A / D conversion, the accuracy requirement of the comparator can be relaxed. When the gain is 2, if an error occurs in the comparator, it exceeds the range (−VREF to + VREF), which is the maximum value allowed in the cyclic A / D conversion, and a large error occurs. On the other hand, in the A / D converter according to the present embodiment, even if an error occurs as shown by the broken line, an error does not occur if the output does not exceed the range (−VREF to + VREF). For example, at a gain of 1.875, if the reference voltage VREF is 1 volt, the allowable error of the comparator is 64 mV.

Referring to part (c) of FIG. 5, the circuit connections are shown in the period T ₂ of the order of the second arithmetic. In response to the clocks φ ₃ and φ ₁ , the switches 49a (49b) and 51a (51b and 53) are closed. In response to the clocks φ _S , φ ₀ , φ ₂ , the switches 41a (41b), 43a (43b), 45a (45b), 47a (47b) are opened.

The third period _{T 3,} the other end 27b of the capacitor 27 (capacitor 37) (37b) is connected to the inverting input 29a of the operational amplifier circuit 29, one end 27a (37a) is non-inverted output 29b of the operational amplifier circuit 29 Connected to. One end 25a (35a) of the capacitor 25 (capacitor 35) is connected to the non-inverted output 29a of the operational amplifier circuit 29 via the switch 51a (51b), and the other end 25b (35b) is connected to the ground potential (virtual ground). The The comparator 15 is connected to the non-inverted output 29 b of the operational amplifier circuit 29. The comparator 15 is operated to perform 1-bit A / D conversion on the operation value of the operational amplifier circuit 29 to generate the signal _SDIG . This is the value of the most significant next digit (MSB-1) of the A / D conversion. The capacitors 25 and 27 store charges corresponding to the value of the next highest digit of the A / D conversion.

Referring to part (d) of FIG. 5, as a subsequent operation, a step of repeating the first and second calculations a desired number of times is shown. That is, in the circuit connection shown in FIG. 5B, the first calculation is performed on the charges stored in the capacitors 25 and 27. The operational amplifier circuit 29 operates according to the equation (2). Next, the comparator 15 is operated to perform 1-bit A / D conversion on the operation value of the operational amplifier circuit 29 to generate a signal _SDIG . The capacitors 25 and 27 store charges corresponding to this value. Through such a cycle, a series of A / D conversion values are sequentially generated. Using a gain stage with a gain of 2 is suitable for generating a digital value (binary number) that does not include a nonlinear error, but using a gain stage 13 having a gain of less than 2 results in an A / D converted digital value. Contains a large non-linear error. However, the cyclic A / D converter 11 performs A / D conversion using a gain stage 13 having a gain G less than 2, and an N-bit digital value including a predetermined nonlinear error caused by a gain less than 2 Is generated. Thereafter, in the step shown in part (e) of FIG. 5, a correction using a coefficient associated with the gain G is applied to the N-bit digital value so that the above-described nonlinear error is improved to M bits (M> M) is generated.

  The digital value sequence (digital code) generated as described above includes a large error due to the gain of the gain stage 13 being a certain value (set value) less than 2, but the correction circuit 19 is used. Digital values without errors can be generated by correction in the digital domain. That is, after the repetition, a digital value of M + 1 bits (N> M + 1) corresponding to the analog signal is generated by calculating a correction coefficient associated with the gain G of the gain stage 13 and a series of A / D conversion values. .

と書き直す。シンボル「ａ」は１未満の正の数である。アナログ入力信号に対応する真のディジタル値を「Ｘ_０」と記す。ディジタル値Ｘ_０はＶ_ＩＮ／Ｖ_Ｒをディジタル化した値である。式（３）を更に書き換えて式（４）を得る。

第１回目のＡ／Ｄ変換による値Ｘ_１は、

と表される。第２回目以降の巡回動作についても、第１回Ａ／Ｄ変換と同様に行って、

を得る。第ｉ回目の演算増幅器の出力Ｘ_ｉと記し、１ビットのＡ／Ｄ変換値をＤ_ｉと記す。 Next, this correction will be described. Since the gain of the gain stage 13 is less than 2, the equation (2) is modified,

And rewrite. The symbol “a” is a positive number less than one. The true digital value corresponding to the analog input signal is denoted as “X ₀ ”. Digital value _{X 0} is a value obtained by digitizing the _V IN / _{V R.} Equation (3) is further rewritten to obtain equation (4).

The value _{X 1} of the first round of A / D conversion,

It is expressed. For the second and subsequent rounds, the same as the first A / D conversion,

Get. Marked output X _i of the i-th operational amplifier, referred to 1-bit A / D conversion value D _i.

を得る。これを変形して式（８）を得る。

Ｘ_Ｎは、必要な分解能を得るためのＮ回の巡回後の残差であり、この値を無視できるので、

と見なす。式（８）は

となる。Ｄ_ｉは巡回動作で得られた値であり、「ａ」は、意図的に減らされた利得差を表す。したがって、この演算により、Ａ／Ｄ変換器への入力信号Ｘ_０に対応する正確なディジタル値が求められる。 Using equation (6)

Get. This is transformed to obtain equation (8).

X _N is the residual after N cycles to obtain the required resolution, and this value can be ignored, so

Is considered. Equation (8) is

It becomes. _Di is a value obtained by the cyclic operation, and “a” represents a gain difference that is intentionally reduced. Therefore, by this operation, exact digital value corresponding to the input signal X ₀ to the A / D converter is required.

であるので、両辺の対数を取ると、

となる。例えば、ａ＝０．１２５、Ｍ＝１４であるとき、Ｎ＝１６．５４ビット、すなわち１７ビットに相当する巡回が必要である。 When the maximum value of the non-linearity error of the A / D converter of M + 1 bit resolution and 0.25 LSB, the maximum of the absolute value of _{X N} is 1, be 1LSB = ^{1/2 M-1}

So, taking the logarithm of both sides,

It becomes. For example, when a = 0.125 and M = 14, N = 16.54 bits, that is, a cycle corresponding to 17 bits is required.

  FIG. 6 shows the integral nonlinearity error. It was confirmed by simulation that an accurate digital value was obtained by the above calculation. FIG. 6A shows the integral nonlinearity error with respect to the converted value by 17 round operations, and FIG. 6B shows the integral nonlinearity error with respect to the transformed value by 18 round operations. Both results show that sufficient linearity can be obtained as a 14-bit A / D converter.

Further, equation (10), the digital value of the desired accuracy corresponding to the input signal X ₀ to the A / D converter, a D _i generated by the cyclic operation, the correction coefficient obtained from the gain difference a It is obtained by the product-sum operation. Therefore, the correction circuit 19 can include an arithmetic circuit 65 that provides a product-sum operation value of N digital values and correction coefficients. The arithmetic circuit 65 can generate a corrected digital value from a digital value including a conversion error caused by using the gain stage 13 having a gain of less than 2.

ここで、シンボル「ｍ」は、キャパシタンスミスマッチ誤差を示し、シンボル「ｇ」は演算増幅回路に有限利得誤差を示している。既に説明された手順と同様にして、式（１４）が得られる。ｍ＝（Ｃ_２−Ｃ_１）／Ｃ_１、ｇ＝（Ｃ_１＋Ｃ_２＋Ｃ_ｉ）／（Ｃ_２×Ｇ_ＦＧ）である。「Ｃ_ｉ」は仮想接地点におけるキャパシタンスを示す。「Ｇ_ＦＧ」は、演算増幅回路のオープン・ループ・ゲインである。

式（１４）は、キャパシタミスマッチ及び有限利得誤差が十分小さければ、

と書き直される。この式によれば、補正回路１７は、Ｍ＋１ビットの第１の積和演算値を提供する第１の演算回路と、Ｎビットの第２の積和演算値を提供する第２の演算回路とを含むことができる。キャパシタンス比のミスマッチの誤差補正が為されるとき、誤差のディジタル補正のための補正値は２つの演算回路によって生成される。つまり、利得に関する誤差だけでなく、キャパシタンスミスマッチ誤差および有限利得誤差が補正されたディジタル値が得られる。式（１５）において「Ｍ」は、誤差の補正に必要な精度を得るための演算の桁数に関連しており、補正のためにＤ_０〜Ｄ_Ｍを使うことを意味する。式（１５）は、イメージセンサデバイス（例えば、ＣＭＯＳイメージセンサデバイス）のようなＡ／Ｄ変換器アレイに対して誤差補正を行うとき、回路構成を簡単化するために有用である。 Next, the cyclic A / D converter of this embodiment will be described. When there is a capacitance mismatch in the capacitor of the gain stage and a finite gain error in the operational amplifier circuit,
In that case, equation (5) is modified and expressed as equation (13).

Here, the symbol “m” indicates a capacitance mismatch error, and the symbol “g” indicates a finite gain error in the operational amplifier circuit. Similar to the procedure already described, equation (14) is obtained. m = (C ₂ −C ₁ ) / C ₁ , g = (C ₁ + C ₂ + C _i ) / (C ₂ × G _FG ). “C _i ” indicates the capacitance at the virtual ground point. “G _FG ” is an open loop gain of the operational amplifier circuit.

Equation (14) is: if the capacitor mismatch and the finite gain error are small enough,

Rewritten. According to this equation, the correction circuit 17 includes a first arithmetic circuit that provides an M + 1-bit first product-sum operation value, and a second arithmetic circuit that provides an N-bit second product-sum operation value. Can be included. When the error correction of the capacitance ratio mismatch is performed, a correction value for digital correction of the error is generated by two arithmetic circuits. That is, not only the gain-related error but also the digital value in which the capacitance mismatch error and the finite gain error are corrected is obtained. In Expression (15), “M” relates to the number of digits of calculation for obtaining the accuracy required for error correction, and means that D _{0 to} D _M are used for correction. Equation (15) is useful for simplifying the circuit configuration when performing error correction on an A / D converter array such as an image sensor device (eg, a CMOS image sensor device).

を用いて書き換えると、式（１５）は、

と表される。アンプの有限利得誤差が既知であれば、式（１６）は定数であるので、誤差補正は、補正係数と各ビットＤ_ｉとの積和演算と、キャパシタミスマッチの係数「ｍ」に関連する係数との乗算により得られる。 In equation (15),

(15) can be rewritten using

It is expressed. Since the equation (16) is a constant if the finite gain error of the amplifier is known, the error correction is performed by multiplying the correction coefficient by each bit D _i and a coefficient related to the coefficient “m” of the capacitor mismatch. Is obtained by multiplication with.

を計算する部分の一例を説明する。図７は、３桁ずつの演算を行う組み合わせを示す図面である。すでに説明したように、変換値Ｄ_ｉは−１または＋１をとるので、８通りの組み合わせが存在する。例えば

式（１９）に関しては、予め

を計算して記憶回路（例えば、レジスタ）に格納しておけば、Ｄ_０、Ｄ_１、Ｄ_２に応じて式（２０）の値のいずれかを選択する演算と、その計算結果の極性反転の演算とにより

が求められる。 In order to reduce the amount of the product-sum operation, it is effective to perform several digits (for example, a plurality of digits, for example, three digits) collectively.

An example of the part for calculating is described. FIG. 7 is a diagram showing a combination for performing an operation by three digits. As already described, since the conversion value D _i takes −1 or +1, there are eight combinations. For example

Regarding equation (19),

Is calculated and stored in a memory circuit (for example, a register), an operation for selecting one of the values of the expression (20) according to D ₀ , D ₁ , D ₂ , and polarity inversion of the calculation result With the operation of

Is required.

により規定される。式（１７）の第２項の式（２３）

についても第１項と同様に計算される。 FIG. 8 is a diagram illustrating an example of a correction circuit that provides the above-described configuration. In FIG. 8, u _a (0), u _b (0), u _c (0), u _d (0), etc. are

It is prescribed by. Equation (23) in the second term of Equation (17)

Is calculated in the same manner as the first term.

The correction circuit 70 includes a first partial product-sum circuit 71 (71a, 71b, 71c, 71d, 71e, 71f), a second partial product-sum circuit 73 (73a, 73b, 73c), and a first addition circuit. 75 (75a, 75b, 75c, 75d, 75e), second adder circuit 77 (77a, 77b), third adder circuit 79, first memory circuit 81a, and fourth adder circuit 83 , A first multiplication circuit 85, a second storage circuit 81b, a second multiplication circuit 89, and a third storage circuit 81c. Each of the first partial product-sum circuits 71 (71a, 71b, 71c, 71d, 71e, 71f) provides a partial product-sum value for each group defined by the division of the digital values D _i arranged in order. Each of the second partial product sum circuit 73 (73a, 73b, 73c) provides a partial product sum value for each group defined by division of the digital value D _i arranged in order. The first adder circuit 75 (75a, 75b, 75c, 75d, 75e) generates a first partial sum value _{S PS1} by adding the partial product sum value from the first partial product sum circuit 71. The adder circuit 77 (77a, 77b) adds the partial product sum values from the second partial product sum circuit 73 to generate a second partial sum value _SPS2 . The multiplication circuit 79 provides a multiplication value S _M1 of the coefficient Km for the capacitor mismatch m and the second partial addition value S _PS2 . The storage circuit 81a stores the coefficient Km and includes, for example, a line memory. The circuit 83 provides an addition value S _A1 of the first partial product sum value S _PS1 from the first circuit 69a and the multiplication value S _M1 from the second circuit 69b. The circuit 85 provides a multiplication value S _M2 of the correction coefficient K _{(1-a) (1-g)} for the gain and finite gain error g and the addition value S _A1 . The memory circuit 81b stores the coefficient K _{(1-a) (1-g)} and includes, for example, a line memory. The circuit 89 provides an addition value of the multiplication value S _M2 and the offset correction value S _OFFSET . The storage circuit 81c stores the coefficient K _OFFSET and includes, for example, a line memory.

Each of the first partial product-sum circuits 71a to 71f and the second partial product-sum circuits 73a to 73c includes a decoder 87a that receives q digital signals, storage circuits 87b, 87c, 87d, and 87e, and a decoder 87a. Multiplexer 87f that selects read signals from the memory circuits 87b to 87e according to the decoded signal, and a circuit that adds a sign according to the decoded signal to the selected value from the multiplexer 87f (in the case of a negative sign, generates a complement) 87g. The number of the memory circuits 87b to 87e is, for example, 2q ^-1 .

  As understood from the above description, by setting g = 0, an error relating to gain and a capacitance mismatch error are corrected. The correction coefficient of the correction circuit 70 is further associated with a capacitance ratio mismatch. Further, by setting m = 0, an error relating to gain and a finite gain error are corrected. The correction coefficient of the correction circuit 70 is further related to the finite gain error of the operational amplifier circuit. Further, by setting g = 0 and m = 0, an error related to gain is corrected.

  FIG. 9 is a diagram illustrating an example of an A / D converter for an image sensor. FIG. 10 is a drawing showing an example of a timing chart for the A / D converter for the image sensor shown in FIG. As the A / D conversion circuit unit 91 of the image sensor device 1, the circuit array 95 of any one of the above cyclic analog / digital converters 11a is shown. The cell array 93 of the image sensor cell 93a includes a plurality of image sensor cells 93a arranged in rows and columns. The cyclic analog-digital converter 11a processes a signal from at least one column of image sensor pixels. As the image sensor pixel, for example, a CMOS image sensor cell can be used. The digital value from the comparison circuit 15 of the cyclic analog / digital converter 11 a is corrected by, for example, the correction circuit 70. The image sensor device 91 can further include a vertical scanning circuit 97, a horizontal scanning circuit, and the like.

Image sensor cells 93a provides a second signal S _SG corresponding to the first signal S _RS and the signal level corresponding to the reset level. The gain stage 13 includes an operational amplifier circuit having a fully differential configuration. The gain stage 13 receives one of the first and second signals S _RS and S _SG from the image sensor cell 93a at the non-inverting input and inputs the other S _RS and S _SG of the first and second signals as an inverting input. To receive. According to the A / D converter for the image sensor, the reset level of the image sensor cell 93a can be canceled.

Referring to FIGS. 9 and 10, A / D converter 11a is a first signal _{S RS} via the switch 41c, 43c to the first portion of the first period _{T 1} (reset level sampling period _{T 1R)} And sample. As a result, charges corresponding to the reset level are stored in the first and second capacitors 25 and 27. A / D converter 11a, the second signal _{S SG} via switch 41b, and 43b sampling the first second portion of the period _{T 1} (signal level sampling period _{T 1S).} As a result, charges corresponding to the reset level are stored in the third and fourth capacitors 35 and 37. The sampled signal is also provided to the comparison circuit 17.

In the first calculation in the second period T2, the charge (signal level charge) stored in the third and fourth capacitors 35 and 37 and the charge stored in the first and second capacitors 25 and 27 ( A difference from the reset level charge) is taken, and charge rearrangement occurs in response to the signal _{SD / A} from the D / A conversion circuit 17. In the second calculation in the third period T3, the A / D conversion of the calculation value from the operational amplifier circuit 13 corresponding to this difference value is performed, and the charges for the subsequent calculation are first to fourth. Store in capacitors 25, 27, 35 and 37. Then, the first and second calculations are repeated.

FIG. 11 is a diagram illustrating an example of an image sensor device. In the CMOS image sensor device 1, a vertical shift register 3 is connected to a row of the cell array 2, and an A / D converter array 4 is connected to a column of the cell array 2. The A / D converter array 4 includes a plurality of arranged A / D converters 11a. In the cell array 2 of the CMOS image sensor 1, for example, CMOS image sensor pixels 2a are arranged in the row direction and the column direction. Although the CMOS image sensor pixel 2a is shown in FIG. 11 as an example of the image sensor cell 93a, the CMOS image sensor pixel is not limited to this specific circuit configuration. A data register 5 is connected to the A / D converter array 4. An A / D conversion value corresponding to the signal from the pixel 2 a is stored in the data register 5. In response to the signal from the horizontal shift register 6, the data register 5 corrects a conversion error caused by the circuit elements of the cyclic A / D converter 11a and a non-linear error created by the A / D converter. An A / D conversion value is provided to the digital circuit 70. In the pixel 2a, the photodiode _DF receives light for one pixel (Optical Signal) related to the image. The gate of the selection transistor M _S is connected to the row select line Si extending in the row direction. The gate of the reset transistor M _R is connected to a reset line Ri. The gate of the transfer transistor M _T is connected to the transfer selection line extending in the row direction. One end of the photodiode D _F is connected to the floating diffusion layer FD via the transfer transistor M _T. Floating diffusion layer FD is connected to a reset potential line Reset via the reset transistor M _R, is connected to the gate of the transistor M _A. One current terminal (for example, drain) of the transistor M _A is connected to the column line 8 via the selection transistor M _S. Transistor M _A is provided in the column line through the selection transistor M _S a potential corresponding to the charge amount of the floating diffusion layer FD.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

  As already described, the embodiment of the present invention does not perform A / D conversion on the ternary digital value using the redundant code, and therefore the number of comparators is small. For this reason, an area and power consumption are reduced. Since a plurality of reference voltages applied to the comparator are not necessary, the area is reduced due to the wiring of the reference voltage. In addition, since the D / A conversion circuit does not perform a ternary switching operation (a switching of a ternary reference voltage including zero) in which a code-dependent offset voltage is likely to occur, it is possible to avoid a problem that causes a decrease in accuracy. Further, the A / D converter using the redundant code also integrates a circuit for storing a signal in a bit width of about twice the digital value of the non-redundant expression and a circuit for horizontally scanning these signals in the column. Although a large area is necessary for this purpose, the circuit structure of the present embodiment can be reduced to an area increase of about 1.2 times.

  As a result, an A / D converter for a CMOS image sensor that is easy to achieve high accuracy and has a small circuit area and low power consumption is realized. Further, by using the digital correction technique, an A / D converter having a high resolution equivalent to 14 bits, which has not been realized yet by anyone, can be realized as a column parallel type. Such a high-performance column parallel A / D converter is considered to be useful in an image sensor for high vision.

FIG. 1 is a diagram schematically showing a cyclic A / D converter. FIG. 2 is a diagram showing the input / output relationship of the cyclic A / D converter. FIG. 3 is a timing chart for the cyclic A / D converter. FIG. 4 is a circuit diagram of an example comparison circuit. FIG. 5 is a diagram showing main steps for a cyclic A / D conversion operation with reference to circuit connection based on a differential circuit configuration. FIG. 6 is a diagram showing an integral nonlinearity error. FIG. 7 is a diagram showing a combination for performing an operation by three digits. FIG. 8 is a diagram illustrating an example of a correction circuit that provides the above-described configuration. FIG. 9 is a diagram illustrating an example of an A / D converter for an image sensor. FIG. 10 is a drawing showing an example of a timing chart for the A / D converter for the image sensor shown in FIG. FIG. 11 is a diagram illustrating an example of an image sensor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Cyclic A / D converter, 13 ... Gain stage less than gain 2, 15 ... Comparison circuit, 17 ... D / A conversion circuit, 19 ... Correction circuit, 21 ... Comparator, 23 ... Control circuit, 25, 27 , 35, 37 ... capacitors, 29 ... operational amplifier circuit, 29a ... non-inverting input, 29b ... inverting output, 29c ... inverting input, 29d ... non-inverting output, 39a, 39b ... voltage source

Claims (14)

A cyclic analog-digital converter that performs N (N> M + 1) cyclic operations to generate a digital value of M + 1 bits,
A gain stage that receives an input signal to the cyclic analog-to-digital converter and provides amplification of a predetermined gain G that is less than 2;
A comparator for generating a binary digital value in response to the input signal or the conversion signal from the gain stage;
A D / A conversion circuit for providing a D / A signal corresponding to a control signal from the comparison circuit to the gain stage;
A correction circuit that corrects N digital values from the comparison circuit using a correction coefficient associated with the gain G to generate the M + 1 bit digital value;
The gain stage performs a cyclic operation according to the D / A signal to generate the converted signal ,
The correction circuit includes a circuit that generates a product-sum operation value of the N digital values and the correction coefficient . The gain stage is for performing amplification at the gain according to the capacitance ratio of the first and second capacitors with a capacitor value providing a capacitance ratio associated with the gain, and the first and second capacitors. The cyclic analog-digital converter according to claim 1 , comprising an operational amplifier circuit. The first capacitor receives an analog signal from the input of the cyclic analog-digital converter during a first period, and the D / A conversion circuit in a second period after the first period. And the input of the operational amplifier circuit, and is connected to the output of the operational amplifier circuit in a third period after the second period,
The second capacitor, together with receiving the analog signal during the first period, is connected between the input and the output of said second and third said operational amplifier circuit during the period, claims 2. The cyclic analog-digital converter described in 2 . The cyclic analog-digital converter according to claim 2 or 3 , wherein a capacitor value of the first capacitor is smaller than a capacitor value of the second capacitor. The correction coefficient of the correction circuit further said that at least associated with one of mismatching errors of the finite gain error and the capacitance ratio of the operational amplifier circuit, in any one of claims 2 to 4 The described cyclic analog-to-digital converter. The correction circuit includes a circuit that generates a first product-sum operation value of M + 1 bits and a circuit that generates a second product-sum operation value of N bits,
6. The cyclic analog-to-digital converter according to claim 5 , wherein the M + 1 bit digital value is generated from the first and second product-sum operation values. The cyclic analog-digital converter according to claim 1 , wherein the comparison circuit compares the received signal with a single reference signal. The gain stage includes a fully differential circuit and provides a non-inverted output signal and an inverted output signal,
The cyclic analog-digital converter according to any one of claims 1 to 6 , wherein the comparison circuit includes a differential circuit that receives the non-inverted output signal and the inverted output signal. An image sensor device,
A cell array of image sensor cells;
A cyclic analog-to-digital converter that performs N (N> M + 1) cyclic operations to generate an M + 1 bit digital value to process a signal from at least one column of the image sensor cell. ,
The cyclic analog-digital converter is
A gain stage providing amplification of a predetermined gain G of less than 2;
A comparison circuit that generates a binary digital value in response to an input signal to the cyclic analog-digital converter or a conversion signal from the gain stage;
A D / A conversion circuit for providing a D / A signal corresponding to the digital value from the comparison circuit to the gain stage;
The image sensor device further includes a correction circuit that corrects N digital values from the comparison circuit using a correction coefficient associated with the gain G to generate the M + 1 bit digital value;
The gain stage performs a cyclic operation according to the D / A signal to generate the converted signal ,
The image sensor device , wherein the correction circuit includes a circuit that generates a product-sum operation value of the N digital values and the correction coefficient . The image sensor cell provides a first signal corresponding to a reset level and a second signal corresponding to a signal level;
The gain stage includes a non-inverting input and an inverting input, and includes an operational amplifier circuit having a fully differential configuration,
The gain stage receives one of the first and second signals from the image sensor cell at the non-inverting input and receives the other of the first and second signals from the image sensor cell as the inverting input. The image sensor device according to claim 9 , wherein the image sensor device is received. A method of generating a digital value from an analog value by cyclic A / D conversion,
Performing a cyclic A / D conversion using a gain stage having a gain G of less than 2 of the cyclic A / D converter to generate an N-bit digital value including a non-linear error due to a gain of less than 2; ,
Wherein by performing correction using the coefficients associated with the gain G to the digital value of said N bits, saw including a step of generating a digital value of the M + 1 bit non-linear error is improved (N> M + 1),
A method of generating a product-sum operation value of the N-bit digital value and the coefficient in the step of generating the M + 1 bit digital value . A cyclic analog-digital converter that performs N (N> M + 1) cyclic operations to generate a digital value of M + 1 bits,
  A gain stage that receives an input signal to the cyclic analog-to-digital converter and provides amplification of a predetermined gain G that is less than 2;
  A comparator for generating a binary digital value in response to the input signal or the conversion signal from the gain stage;
  A D / A conversion circuit for providing a D / A signal corresponding to a control signal from the comparison circuit to the gain stage;
  A correction circuit that corrects N digital values from the comparison circuit using a correction coefficient associated with the gain G to generate the M + 1 bit digital value;
With
  The gain stage is for performing amplification at the gain according to the capacitance ratio of the first and second capacitors with a capacitor value providing a capacitance ratio associated with the gain, and the first and second capacitors. A cyclic analog-digital converter that includes an operational amplifier circuit and performs the cyclic operation according to the D / A signal to generate the converted signal. The cyclic analog-to-digital conversion according to claim 12, wherein the correction coefficient of the correction circuit is further related to at least one of a finite gain error of the operational amplifier circuit and a mismatch error of the capacitance ratio. vessel. A cyclic analog-digital converter that performs N (N> M + 1) cyclic operations to generate a digital value of M + 1 bits,
  A gain stage that receives an input signal to the cyclic analog-to-digital converter and provides amplification of a predetermined gain G that is less than 2;
  A comparator for generating a binary digital value in response to the input signal or the conversion signal from the gain stage;
  A D / A conversion circuit for providing a D / A signal corresponding to a control signal from the comparison circuit to the gain stage;
  A correction circuit that corrects N digital values from the comparison circuit using a correction coefficient associated with the gain G to generate the M + 1 bit digital value;
With
  The gain stage performs a cyclic operation according to the D / A signal to generate the converted signal, includes a fully differential circuit, and provides a non-inverted output signal and an inverted output signal,
  The comparison circuit includes a cyclic analog / digital converter including a differential circuit that receives the non-inverted output signal and the inverted output signal.

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