JP2014239426A - Digital correction circuit for a/d conversion circuit, a/d conversion circuit, and image sensor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct errors caused by an analog circuit in an integrating/cyclic A/D conversion device in a digital domain.SOLUTION: A digital correction circuit for, in an integrating/cyclic A/D conversion circuit for sequentially performing folding integration A/D conversion and cyclic A/D conversion with the use of an operational amplification circuit, correcting an A/D conversion value by subtracting from the A/D conversion value a digital value of a nonlinear error caused by a gain error of folding integration having a predetermined number of times of integration (M) and a predetermined number of times of folding (M) calculates a digital value of a first error (E) substantially proportional to the number of times of folding (M), which is a nonlinear error caused by the gain error of the folding integration, and subtracts the first error (E) from the A/D conversion value. In addition, a digital value of a second error (E) that is an integration error of the folding integration is furthermore calculated, and the first error (E) and the second error (E) are subtracted from the A/D conversion value.

Description

  The present invention relates to a digital correction circuit, an A / D conversion circuit, and an image sensor device for an A / D conversion circuit that converts an analog signal into a digital signal.

  Patent Document 1 describes an A / D converter. In this A / D converter, an integration type (or folding integration type) A / D conversion is performed on an input analog signal, and a cyclic type is applied to a residual analog signal of the folding integration type A / D conversion. A / D conversion is performed. In the folded integration type A / D conversion, calculation for A / D conversion is performed while repeating sampling of the input signal and integration of the sample value, and a digital value is obtained from the analog signal. In this A / D conversion method, the dynamic range is expanded by the folding operation while reducing noise by integration, so that both low noise and dynamic range can be achieved.

  In the folded integration type A / D converter described in Patent Document 1, for example, when the voltage range of the input signal is 0V to 1V, the output range is 2 such as −1V to 1V. Double. In this case, if the cyclic A / D conversion performed after the folded integration A / D conversion is configured by a fully differential cyclic A / D converter, the input voltage in the folded integration is used while using the same reference voltage. It is possible to accommodate an input voltage range that is twice the range.

  However, when a cyclic A / D converter is configured by a single-ended A / D converter, there is a problem that only a half input voltage range of the fully differential type can be handled. That is, in the A / D converter described in Patent Document 1, when an A / D converter having a single-end configuration is applied, the amplitude range of the input voltage is limited to half. On the other hand, in such A / D converters, there has been a demand to apply a single-ended configuration in order to reduce the area and power consumption.

  Therefore, the present inventors have so far developed a method of sequentially performing a folding integration type A / D conversion and a cyclic type A / D conversion as a column parallel type A / D converter mounted on a CMOS image sensor ( For example, see Patent Document 2). It is possible to have a wide dynamic range and high resolution (tone gradation) while reducing the noise of the sensor by sampling, integration and folding operations many times, and can be widely put into practical use. .

International Publication No. 2008/016049 Pamphlet International Publication No. 2012/111821 Pamphlet Japanese Patent No. 4469989

  In order to achieve higher speed and lower power consumption in the A / D converter (hereinafter referred to as an integral / cyclic A / D converter) that sequentially performs the above-described folded-integral A / D conversion and cyclic A / D conversion. It is effective to correct an error caused by an analog circuit in the A / D converter in the digital domain. However, although a digital correction circuit of a cyclic A / D modulation circuit is disclosed in Patent Document 3, a digital correction circuit of an integration / cyclic A / D converter has not been developed.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a digital correction circuit for an A / D conversion circuit capable of correcting an error caused by an analog circuit in an integration / cyclic type A / D conversion circuit in the digital domain. It is to provide a D conversion circuit and an image sensor device.

  As described above, it is effective to correct an error generated by an analog circuit in the A / D converter in the digital domain in order to make the integration / cyclic A / D converter faster and reduce power consumption. . In order to increase speed and reduce power consumption, it is effective to use a small-sized capacitor and a low-gain amplifier, but this degrades the accuracy of the A / D converter and increases nonlinear errors. Become. If the accuracy degradation can be corrected by processing in the digital domain and the nonlinear error can be made sufficiently small, a highly accurate A / D converter can be realized with a small size capacitor and a low gain amplifier. Power consumption can be reduced. The present invention is characterized by using the following means in order to realize these.

A digital correction circuit for an A / D conversion circuit according to the present invention is an integration / cyclic A / D conversion circuit that sequentially performs folded integration type A / D conversion and cyclic type A / D conversion using an operational amplifier circuit. Digital that corrects an A / D conversion value by subtracting a digital value of a nonlinear error caused by a gain error of folding integration having a predetermined integration number (M) and a predetermined folding number (M ₁ ) from the A / D conversion value A correction circuit,
A digital value of a first error (E _FR ) that is a non-linear error caused by a gain error of the folding integration and is substantially proportional to the number of foldings (M ₁ ) is calculated, and the digital value is calculated from the A / D conversion value. A correction means for correcting the A / D conversion value by subtracting the first error (E _FR ) is provided.

In the digital correction circuit, the correction means _supplies the first reference voltage (V _RL ) as the input voltage (V _in ) to the operational amplifier circuit to perform one integration, and then the operational amplifier circuit at that time A first A / D conversion value obtained by performing cyclic A / D conversion on the output voltage of the second output voltage and a second higher than the first reference voltage (V _RL ) as the input voltage (V _in ). The second reference voltage (V _RH ) is applied to the operational amplifier circuit and integrated once, and then the output voltage of the operational amplifier circuit at that time is subjected to cyclic A / D conversion for a predetermined number of cycles. The first A / D conversion value is subtracted from the second A / D conversion value, and the subtraction value is input to the cyclic A / D conversion side. by converting, calculating the digital value of the first error (E _FR) And features.

Further, in the digital correction circuit, the correction means is based on a calculation value of an integral nonlinear error (INL) related to the first error (E _FR ) with respect to a plurality of A / D conversion operations. Calculating a digital value of the first error (E _FR ) when the cost function obtained by adding the square value of the error (INL) to a plurality of A / D conversion operations is minimized. To do.

Further, in the digital correction circuit, the correction means further calculates a digital value of a second error (E _FI ) that is a non-linear error caused by the gain error of the folding integration and is an integration error of the folding integration. The first error (E _FR ) and the second error (E _FI ) are subtracted from the A / D conversion value.

Still further, in the digital correction circuit, the correction means includes code data indicating the number of integrations (i) indicating the number of integrations of the folding integration, and data indicating the presence / absence of folding of the folding integration ( The digital value of the second error (E _FI ) is calculated based on D _I (i)).

In the digital correction circuit, the correction means includes a circuit for calculating a digital value of the second error (E _FI ) in the column circuit, and the calculation circuit includes:
An up-counter that counts the number of integrations (i) indicating the number of integrations;
A register that operates using data indicating the presence or absence of the folding integration as a clock; and
The number of integrations (i) from the up-counter and the data from the register are added to calculate the digital value of the second error (E _FI ) through the register with the added value data And an adder that outputs the correction coefficient (m ₁ ).

In the digital correction circuit, the correction means is connected between a capacitor (C ₁ ) connected to the input terminal of the operational amplifier circuit and the input terminal and the output terminal in cyclic A / D conversion. A third error (E _g1 ) corresponding to an error due to a capacitor mismatch with the integral capacitance (C ₂ ) is further calculated, and the first error (E _FR ) and the first error are calculated from the A / D conversion value. 2 error (E _FI ) and the third error (E _g1 ) are subtracted.

Further, in the digital correction circuit, the correction means copes with an error due to a mismatch of capacitors between two capacitors (C _1a , C1 _b ) connected to the input terminal of the operational amplifier circuit in the cyclic A / D conversion. The fourth error (E _m1 ) is further calculated, and the third error (E _FI ) is added to the first error (E _FR ) and the second error (E _FI ) from the A / D conversion value. E _g1 ) and at least one of the fourth error (E _m1 ) is subtracted.

  Further, in the digital correction circuit, the integration / cyclic A / D conversion circuit is configured by using the same circuit as the folded integration A / D conversion circuit and the cyclic A / D conversion circuit. It is characterized by being.

  Further, in the digital correction circuit, the integration / cyclic A / D conversion circuit is configured by using different circuits for the folded integration A / D conversion circuit and the cyclic A / D conversion circuit. It is characterized by being.

  An A / D conversion circuit according to the present invention is an integration / cyclic A / D conversion circuit that sequentially performs a folded integration type A / D conversion and a cyclic A / D conversion using an operational amplifier circuit. It is provided with.

  In the A / D conversion circuit, the integration / cyclic A / D conversion circuit uses the same circuit for the folded integration A / D conversion circuit and the cyclic A / D conversion circuit. It is characterized by being configured.

  Further, in the A / D conversion circuit, the integration / cyclic A / D conversion circuit uses different circuits for the folded integration A / D conversion circuit and the cyclic A / D conversion circuit. It is characterized by being configured.

An image sensor device according to the present invention is an image sensor device that reads an image.
An A / D conversion circuit for A / D converting the pixel value signal obtained by reading the image;
The A / D conversion circuit is an integration / cyclic A / D conversion circuit that sequentially performs folded integration type A / D conversion and cyclic type A / D conversion using an operational amplifier circuit, and the digital correction circuit is It is characterized by having.

  In the image sensor device, the integration / cyclic A / D conversion circuit is configured by using the same circuit for the folded integration A / D conversion circuit and the cyclic A / D conversion circuit. It is characterized by being.

  Further, in the image sensor device, the integration / cyclic A / D conversion circuit includes the folded integration A / D conversion circuit and the cyclic A / D conversion circuit using different circuits. It is characterized by being.

  According to the digital correction circuit of the present invention, the digital correction can improve the accuracy of the A / D converter, that is, increase the resolution, and can realize, for example, a 14-bit highly accurate A / D conversion. In addition, the speed can be increased with low power consumption.

It is a block diagram which shows the circuit structure of the A / D converter which concerns on the 1st Embodiment of this invention. FIG. 2 is a circuit diagram of a reference voltage generation circuit in the cyclic A / D converter shown in FIG. 1. FIG. 2 is a circuit diagram of a reference voltage generation circuit in the cyclic A / D converter shown in FIG. 1. It is drawing which shows the image sensor cell used with the A / D converter of FIG. It is drawing which shows the operation | movement of integral type A / D conversion in the A / D converter shown by FIG. It is drawing which shows the input-output characteristic of the gain stage by simulation of the A / D converter of FIG. It is drawing which shows the comparative example of the input-output characteristic of a gain stage by simulation of the A / D converter of FIG. FIG. 2 is a diagram showing processing timing in one horizontal readout period when analog CDS is performed in the A / D converter of FIG. 1 and a processing timing in one horizontal readout period when digital CDS is implemented. It is drawing which shows operation | movement of cyclic | annular A / D conversion in the A / D converter shown by FIG. It is drawing which shows the operation | movement of integral type A / D conversion in the A / D converter shown by FIG. It is a figure which shows the relationship between the input level of the analog signal _VIN which is an input signal, and a digital count value corresponding to the simulation of FIG. It is drawing which shows the operation | movement of integral type A / D conversion in an A / D converter. It is drawing which shows the input-output characteristic of the gain stage by simulation in the operation | movement of integral type A / D conversion shown in FIG. 2 is a block diagram showing a configuration for generating a digital value from an output signal of a comparator in the A / D converter of FIG. 1. FIG. FIG. 15 is a circuit diagram of a part of the configuration shown in FIG. 14. FIG. 15 is a circuit diagram of a part of the configuration shown in FIG. 14. It is a block diagram which shows the structure of the CMOS image sensor 101 which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the digital correction circuit 112 of FIG. It is a figure which shows the input-output voltage characteristic which shows the operation | movement of the folding | integrating integration type A / D converter of FIG. FIG. 19 is a circuit diagram showing a circuit for measuring error parameters e _m1 and e _m2 for the digital correction circuit 112 of FIG. 18. 19 is a graph of a cost function showing a method using a cost function, which is one method for measuring the error parameter E _FR for the digital correction circuit 112 of FIG. FIG. 19 is a circuit diagram showing a circuit of a column circuit 150 in the integration / cyclic ADC array 4 for measuring an error _EFI for the digital correction circuit 112 of FIG. 18. FIG. 18 is a MATLAB simulation result of an A / D conversion circuit using the digital correction circuit 112 of FIG. 17, and shows an integral nonlinearity error (INL) and differential nonlinearity with respect to the digital code when the error parameter P1 is used without correction. It is a graph which shows an error (DNL). FIG. 18 is a MATLAB simulation result of the A / D conversion circuit using the digital correction circuit 112 of FIG. 17, and shows integral nonlinearity error (INL) and differential nonlinearity for the digital code when the error parameter P1 is used in the method M1. It is a graph which shows an error (DNL). FIG. 18 is a MATLAB simulation result of an A / D conversion circuit using the digital correction circuit 112 of FIG. 17, and shows integral nonlinearity error (INL) and differential nonlinearity with respect to a digital code when the error parameter P1 is used in the method M2. It is a graph which shows an error (DNL). FIG. 18 is a MATLAB simulation result of an A / D conversion circuit using the digital correction circuit 112 of FIG. 17, and shows an integral nonlinearity error (INL) and differential nonlinearity with respect to the digital code when the error parameter P2 is used without correction. It is a graph which shows an error (DNL). FIG. 18 is a MATLAB simulation result of an A / D conversion circuit using the digital correction circuit 112 in FIG. 17, and shows integral nonlinearity error (INL) and differential nonlinearity with respect to a digital code when the error parameter P2 is used in the method M1. It is a graph which shows an error (DNL). FIG. 18 is a MATLAB simulation result of an A / D conversion circuit using the digital correction circuit 112 of FIG. 17, and shows integral nonlinearity error (INL) and differential nonlinearity with respect to a digital code when the error parameter P2 is used in the method M2. It is a graph which shows an error (DNL). It is a block diagram which shows the whole structure of the A / D converter which concerns on the 3rd Embodiment of this invention. FIG. 30 is a circuit diagram illustrating a configuration of a folded integration type A / D conversion circuit 201 and its peripheral circuits in FIG. 29. FIG. 31 is a circuit diagram showing a configuration of a reference voltage generation circuit 37C of FIG. 30. FIG. 31 is a diagram showing an operation of the folding integration type A / D conversion circuit 201 of FIG. 30. FIG. FIG. 33 is a diagram showing input / output characteristics of a gain stage by simulation in the operation of the folding integration type A / D conversion circuit 201 shown in FIG. 32. FIG. 33 is a diagram illustrating a relationship between an input level of an analog signal _VIN , which is an input signal, and a digital count value, corresponding to the simulation of the folding integration type A / D conversion circuit 201 illustrated in FIG. 32. FIG. 30 is a circuit diagram showing a configuration of a cyclic A / D conversion circuit 202 in FIG. 29 and its peripheral circuits.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the A / D converter, the image sensor device, and the method for generating a digital signal from an analog signal according to the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

First embodiment.
FIG. 1 is a circuit diagram of an A / D converter according to this embodiment. The A / D conversion circuit 111 has the same circuit for a first A / D conversion operation that is a so-called folded integration type A / D conversion and a second A / D conversion operation that is a cyclic type A / D conversion. Implement using the configuration. The A / D conversion circuit 111 realizes the first and second A / D conversion operations by changing the time-series control pattern of the switches included in the A / D conversion circuit 111.

  The A / D conversion circuit 111 includes a gain stage 15, an A / D conversion circuit 17, a logic circuit 19, and a D / A conversion circuit 21. The A / D conversion circuit 111 includes a reference voltage generation circuit 37 and a clock generator 41.

The gain stage 15 includes an input 15a receiving the analog signal _{V IN} to be converted to a digital value, and an output 15b to provide a calculation value _{V OP.} The gain stage 15 includes a single-ended operational amplifier circuit 23 and first to third capacitors 25, 27, and 29.

The operational amplifier circuit 23 has a first input 23a, an output 23b, and a second input 23c. The phase of the signal of the output 23b is inverted from the phase of the signal applied to the first input 23a. ing. For example, the first and second inputs 23a and 23c are an inverting input terminal and a non-inverting input terminal, respectively, and the output 23b is a non-inverting output terminal. For example, a second input 23c of the operational amplifier circuit 23 is connected to a reference potential line _{L COM,} also receives a reference voltage _{V COM.}

  The gain stage 15 includes a plurality of switches for connecting the capacitors 25, 27, and 29 and the operational amplifier circuit 23. The arrangement of the switches 43, 47, 49, 51, 53, and 55 shown in FIG. 1 is an example. The switches 43, 47, 49, 51, 53 are controlled by the clock generator 41.

  The gain stage 15 can perform the first calculation operation and the first storage operation in the first A / D conversion operation, and the second calculation operation and the second storage operation in the second A / D conversion operation. A second storage operation can be performed.

In the first calculation operation, the calculation value V _OP is generated by the calculation amplifier circuit 23 and the first to third capacitors 25, 27, and 29.

In the first storing operation, the first capacitor 25 is connected to the first or second reference reference voltage V _RH or V _RL supplied from the first output 21 a of the D / A conversion circuit 21 or the gain stage input 15 a. The analog signal V _IN supplied from is stored. In the first storing operation, the second capacitor 27 stores the first or second reference reference voltages V _RH and V _RL supplied from the second output 21 b of the D / A conversion circuit 21. In the first storing operation, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a, thereby holding the calculated value _VOP .

In the first calculation operation, when the first or second reference reference voltages V _RH and V _RL are stored in the first capacitor 25 in the first storage operation, the first capacitor 25 is analog. When the analog signal _VIN is stored in the first capacitor 25 in the first storing operation, it is connected between the input 15a that receives the signal _VIN and the first input 23a of the operational amplifier circuit 23. One capacitor 25 is connected between the first output 21 a of the D / A conversion circuit 21 and the first input 23 a of the operational amplifier circuit 23. In the first arithmetic operation, the second capacitor 27 is connected between the second output 21 b of the D / A conversion circuit 21 and the first input 23 a of the operational amplifier circuit 23. Further, in the first calculation operation, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a, so that the calculated value V _OP is applied to the output 15b of the gain stage 23. Generated.

In the second storing operation, the calculated value V _OP is stored in the first and second capacitors 25 and 27. In the second calculation operation, the calculation value V _OP is generated by the calculation amplifier circuit 23 and the first to third capacitors 25, 27, and 29. That is, in the second arithmetic operation, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a, and the first and second capacitors 25, 27 are respectively connected to D / Connected between the first output 21 a or the second output 21 b of the A conversion circuit 21 and the first input 23 a, the calculated value V _OP is generated at the output 15 b of the gain stage 15.

The first to third capacitors 25, 27, and 29 are capacitors for storing and calculating various signal values. Here, the capacitance C ₂ of the third capacitor 29 is larger than the capacitances C _1a and C _{1b of} the first and second capacitors 25 and 27. As a result, the analog signal _VIN input in the first A / D conversion operation which is the folding integration type A / D conversion is attenuated according to the capacitance ratio (C _1a / C ₂ , C _1b / C ₂ ). Integrated. Therefore, the voltage range of the analog signal _VIN output in the folding integration type A / D conversion is also reduced according to the capacitance ratio of the capacitor, so that the A / D conversion circuit 111 can be configured by a single end configuration.

The third capacitor 29 ideally has a capacity twice as large as that of the first capacitor 25 or the second capacitor 27. That is, the relationship of C _1a = 1/2 × C ₂ and C _1b = 1/2 × C ₂ is established. According to the A / D conversion circuit 111 having such a capacitor, the analog signal _VIN input in the folded integration type A / D conversion is attenuated by ½ and sampled and integrated. Hence, the voltage range of the analog signal V _OP is outputted in the folded integral type A / D conversion also, since half according to the volume ratio of the capacitor, the second A / D converter is a cyclic A / D converter In operation, an input voltage suitable for a single-ended A / D converter is provided.

The A / D conversion circuit 17 generates a digital signal D according to the conversion reference voltages V _RCH and V _RCL based on the signal V _OP from the output 23 b of the gain stage 23.

The A / D conversion circuit 17 can include, for example, two comparators 17a and 17b. The comparators 17a and 17b respectively compare the input analog signal with the respective predetermined first and second converted reference voltages V _RCH and V _RCL, and as shown in FIG. 1, the comparison result signals B ₀ and B ₁ is provided. The conversion reference voltages V _RCH and V _RCL in the A / D conversion circuit 17 are provided by the reference voltage generation circuit 37. The digital signal D indicates an A / D conversion value. The digital signal D has, for example, 2 bits (B ₀ , B ₁ ), and each bit (B ₀ , B ₁ ) can take “1” or “0”. The digital signal D is represented as (D = B ₀ + B ₁ ). In the A / D conversion circuit 111, the integration value of one time or the digital value for each round is changed to the first to third values (D = 0, D = 1, D =) by the combination of the bits (B ₀ , B ₁ ). 2). That is, the comparators 17a and 17b operate as follows.

When V _OP > V _RCH B ₁ = 1, B ₀ = 1
When V _RCL <V _OP ≦ V _RCH B ₁ = 0, B ₀ = 1
When V _OP ≦ V _RCL B ₁ = 0, B ₀ = 0

Further, the A / D conversion circuit 17 may generate the digital signal D using, for example, one comparator 17a in the first A / D conversion operation. In this case, the digital signal D is only 1 bit (B ₁ ) and can represent a binary value. A signal used as a reference in the comparator 17a is a conversion reference voltage V _RCH . In this case, the comparator 17a operates as follows.

When V _OP > V _RCH B ₁ = 1
When V _OP ≦ V _RCH B ₁ = 0

The reference voltage generation circuit 37 is a circuit that generates first and second conversion reference voltages V _RCH and V _RCL based on the first and second reference reference voltages V _RH and V _RL . The first reference reference voltage V _RH and the second reference reference voltage V _RL are supplied from the reference voltage sources 33 and 35. FIG. 2 is an example of a circuit diagram of the reference voltage generation circuit 37. As shown in FIG. 2, the reference voltage generation circuit 37 generates a voltage V _RC1H according to resistors R _{1 to} R ₅ having predetermined resistance values based on the first and second reference reference voltages V _RH and V _RL. , V _RC2H , V _RC2L , and V _RC1L are generated. In the first A / D conversion operation, the voltages V _RC1H and V _RC1L are supplied as the first and second conversion reference voltages V _RCH and V _RCL by the operation of the switch SI. On the other hand, in the second A / D conversion operation, the voltages V _RC2H and V _RC2L are supplied as the first and second conversion reference voltages V _RCH and V _RCL by the operation of the switch SA.

According to the reference voltage generation circuit 37, the first conversion reference voltage V _RCH is higher than the median value between the first reference reference voltage V _RH and the second reference reference voltage value V _RL and It is lower than the standard reference voltage _VRH . The first conversion reference voltage _{V RCH} at the first A / D conversion operation is higher than the first conversion reference voltage _{V RCH} in the second A / D conversion operation. In addition, the second conversion reference voltage V _RCL is lower than the median value between the first standard reference voltage V _RH and the second standard reference voltage value V _RL and higher than the second standard reference voltage V _RL . The second conversion reference voltage V _RCL in the first A / D conversion operation is lower than the second conversion reference voltage V _RCL in the second A / D conversion operation. Since the first and second conversion reference voltages V _RCH and V _RCL are generated in this way, the first A / D conversion operation and the second A / D conversion operation are appropriately performed.

Further, for example, the resistance value of the resistor _R 1 to R _5, resistors _R 1 = 2R, the resistance _R 2 = R, the resistance _R 3 = 2R, the resistance _R 4 = R, resistor _R 5 = 2R _(R is a predetermined resistance Value), the voltages V _RC1H and V _RC1L represented by the following expressions are supplied as the first and second conversion reference voltages V _RCH and V _RCL in the first A / D conversion operation. It is preferred that

V _RC1H = (3V _RH + V _RL ) / 4
V _RC1L = (V _RH + 3V _RL ) / 4

_Further , it is preferable that voltages V _RC2H and V _RC2L represented by the following expressions are supplied as the first and second conversion reference voltages V _RCH and V _RCL in the second A / D conversion operation.

V _RC2H = (5V _RH + 3V _RL ) / 8
V _RC2L = (3V _RH + 5V _RL ) / 8

Since the first and second conversion reference voltages V _RCH and V _RCL are generated in this way, the second A / D conversion operation is more appropriately performed.

FIG. 3 shows an example of a circuit diagram of the reference voltage generation circuit 37 when the A / D conversion circuit 17 generates the digital signal D using one comparator 17a in the first A / D conversion operation. It is. According to the reference voltage generation circuit 37, in the first A / D conversion operation, the voltage V _RC1H is supplied as the first conversion reference voltage V _RCH by the operation of the switch SI. On the other hand, in the second A / D conversion operation, the voltages V _RC2H and V _RC2L are supplied as the first and second conversion reference voltages V _RCH and V _RCL by the operation of the switch SA.

According to the reference voltage generation circuit 37, the first conversion reference voltage V _RCH in the first A / D conversion operation is between the first standard reference voltage V _RH and the second standard reference voltage value V _RL. Is the median of Further, as the first and second conversion reference voltages V _RCH and V _RCL in the second A / D conversion operation, voltages V _RC2H and V _RC2L represented by the following expressions are supplied.

V _RC2H = (5V _RH + 3V _RL ) / 8
V _RC2L = (3V _RH + 5V _RL ) / 8

The logic circuit 19 generates a control signal V _CONT (for example, φ _DH , φ _DL , φ _DS ) corresponding to the digital signal D.

D / A conversion circuit 21, first and second output 21a, has 21b, at least one of the first standard reference voltage _{V RH} and the second standard reference voltage _{V RL,} control signal _{V CONT} Accordingly, the gain stage 15 is provided via the first and second outputs 21a and 21b. The first reference voltage V _RH and the second reference voltage V _RL are supplied from the reference voltage sources 33 and 35. In response to the control signal, the D / A conversion circuit 21 provides either the first or second reference reference voltage V _RH or V _RL to the first output 21a and the first to the second output 21b. And a switch circuit 31 for providing one of the second reference reference voltages V _RH and V _RL .

The switch circuit 31 operates the switches 31a and 31b to supply the first and second reference reference voltages V _RH and V _RL to the first and second outputs 21a and 21b, respectively, and operates the switches 31a and 31c. the first standard reference voltage _{V RH} the first and second output 21a by, supplied to both 21b, the switch 31b, the second standard reference voltage _{V RL} first and by operating the 31c 2 are supplied to both outputs 21a and 21b. The first and second outputs 21a and 21b of the D / A conversion circuit 21 are connected to one ends 25a and 27a of the first and second capacitors 25 and 27, respectively. Since the opening and closing of the switches 31a to 31c are controlled by control signals φ _DH , φ _DS , φ _DL from the logic circuit 19, the values of the digital signals B ₁ , B ₀ are the control signals φ _DH , φ _DS , Determine which of the _DLs becomes active.

If the voltages provided to the first and second outputs 21a and 21b are V _DA1 and V _DA2 , respectively, the D / A conversion circuit 21 responds to the control signal V _CONT from the logic circuit 19 and, for example, Control.

When condition D = 2 is satisfied: V _DA1 = V _DA2 = V _RH
When condition D = 1 is satisfied: V _DA1 = V _RH , V _DA2 = V _RL
When condition D = 0 is satisfied: V _DA1 = V _DA2 = V _RL

Further, in the first A / D conversion operation, when the A / D conversion circuit 17 is configured to generate the digital signal D using one comparator 17a, the D / A conversion circuit 21 is connected to the comparator 17a. The following control is performed in accordance with the control signal V _CONT based on the digital signal B ₁ .

When condition B ₁ = 1 is satisfied: V _DA1 = V _RH , V _DA2 = V _RL
When condition B ₁ = 0 is satisfied: V _DA1 = V _DA2 = V _RL

  Another aspect of the present invention is an image sensor device. FIG. 4 is a diagram illustrating pixels of the image sensor. The image sensor device includes a cell array including an array of image sensor cells 2a and a converter array connected to the cell array and including a plurality of A / D conversion circuits 111. Each of the A / D conversion circuits 111 is connected to the image sensor cell 2a via the column line 8 of the cell array.

The image sensor cell 2a has, for example, a CMOS image sensor cell structure. The photodiode PD receives light L for one pixel related to the image. The gate of the selection transistor M _S is connected to the row select line S extending in the row direction. The gate of the reset transistor M _R is connected to the reset line R. The gate of the transfer transistor M _T is connected to the transfer selection line extending in the row direction. One end of the photodiode PD is connected to the floating diffusion layer FD via the transfer transistor M _T. Floating diffusion layer FD is connected to a reset potential line Reset via the reset transistor _{M R,} is connected to the gate of the transistor _{M A.} One current terminal (for example, drain) of the transistor M _A is connected to the column line 8 via the selection transistor M _S. Transistor M _A is provided in the column line through the selection transistor M _S a potential corresponding to the charge amount of the floating diffusion layer FD.

The image sensor cell 2a having this structure can generate a first signal indicating a reset level and a second signal indicating a signal level superimposed on the reset level. That is, the image sensor cell 2a, first, providing a reset control signal R to the reset transistor M _R, resets the floating diffusion layer FD. Through the amplification transistor M _A, read out the reset level. Then, a charge transfer control signal TX is supplied to the transfer transistor M _T, is transferred from the photodiode PD the photo-induced signal charge to the floating diffusion layer. Thereafter, through the transistor M _A, reading the signal level. Thus, the pixel 2a can generate the first signal S1 indicating the reset level and the second signal S2 indicating the signal level superimposed on the reset level.

  Next, the first A / D conversion operation in the A / D conversion circuit 111 shown in FIG. 1 will be described with reference to FIG.

In FIG. 5A, the A / D conversion circuit 111 performs a first storing operation as a first initial storing step. In this step, the analog signal _VIN received via the input 15a of the gain stage 15 is stored in the first capacitor 25, and the output 23b of the gain stage 15 and the first input 23a are connected. The second capacitor 27 stores the second reference voltage _VRL supplied from the second output 21b, and the third capacitor 29 includes the output 23b of the operational amplifier circuit 23 and the first input 23a. Connected between.

Storage and connection in the first initial storage step and each step described below are realized by the switch circuit 31 and the switches 43, 47, 49, 51, 53. In the first initial storing step, the control signal (φ _DH = 0, φ _DS = 0, φ _DL = 1) and the clock signal (φ ₁ = 1, φ ₂ = 0, φ ₃ = 0, φ _R = 1, By φ _S = 1), the switches 31c, 47, 53, and 43 are turned on, and the switches 31a, 31b, 49, and 51 are turned off.

At this time, charges (Q _1a , Q _1b ) accumulated in the capacitors C _1a , C _1b are expressed by the following equations.

Q _1a = C _1a (V _IN −V _COM ) (1)
Q _1b = C _1b (V _RL −V _COM ) (2)

Subsequent to the first initial storage step, the A / D conversion circuit 111 performs the first calculation step shown in FIG. 5B or FIG. 5C according to the value of D (= B ₁ + B ₀ ). The first calculation operation is performed.

In this step, the first calculation operation is performed by connecting the first capacitor 25 between the first output 21a and the first input 23a. The second capacitor 27 is connected between the second output 21b and the first input 23a, and the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a. As a result, the calculated value V _OP is generated at the output 15 b of the gain stage 15. In the first calculation step, the switch 49 is turned on by the clock signals (φ ₁ = 0, φ ₂ = 1, φ ₃ = 0, φ _R = 0, φ _S = 0), and the switches 47, 51, 53, 43 is made non-conductive.

The first output 21a and the second output 21b of the D / A conversion circuit 21 are controlled by the switch circuit 31 according to the output value D (= B ₁ + B ₀ ) from the comparators 17a and 17b. A reference reference voltage V _RH or a second reference reference voltage V _RL is provided.

  The comparators 17a and 17b operate as follows.

When V _OP > V _RCH B ₁ = 1, B ₀ = 1
When V _RCL <V _OP ≦ V _RCH B ₁ = 0, B ₀ = 1
When V _OP ≦ V _RCL B ₁ = 0, B ₀ = 0 (3)

When D = 2, the operation of FIG. 5B is performed while being controlled so that the first reference reference voltage _VRH is provided from the first output 21a and the second output 21b of the D / A conversion circuit 21. Done. On the other hand, when D = 0, the second reference reference voltage _VRL is controlled so as to be provided from the first output 21a and the second output 21b of the D / A conversion circuit 21 as shown in FIG. Operation is performed. Further, when D = 1, the first reference reference voltage V _RH and the second reference reference voltage V _RL are provided from the first output 21 a and the second output 21 b of the D / A conversion circuit 21, respectively. The operation shown in FIG. 5C is performed while being controlled. The output value resulting from this operation is D (2).

For example, in the first initial storage step, since V _OP = V _COM , B ₁ = 0 and B ₀ = 1. Therefore, since D = 1, the operation shown in FIG. 5C is performed. The output V _{OP at} this time is as follows.

Subsequently, the A / D conversion circuit 111 performs the first storing operation shown in FIG. 5D as a first storing step. In the first storage step, while retaining the operation value V _OP to the capacitance C ₂ by connecting the third capacitor 29 between the output 23b and the first input 23a of the operational amplifier circuit 23, the gain stage The analog signal _VIN from the 15 inputs 15 a is stored in the first capacitor 25, and the second reference voltage V _RL supplied from the second output 21 b is stored in the second capacitor 27. In the first storing step, the control signal (φ _DH = 0, φ _DS = 0, φ _DL = 1) and the clock signal (φ ₁ = 1, φ ₂ = 0, φ ₃ = 0, φ _R = 0, φ _{With S} = 1), the switches 31c, 47, 43 are turned on, and the switches 31a, 31b, 49, 51, 53 are turned off.

  Next, according to the value of D (2), the A / D conversion circuit 111 performs a first calculation operation as a first calculation step shown in FIG. 5B or 5C. That is, the A / D conversion circuit 111 selects the first calculation step while selecting one of the first calculation operations shown in FIGS. 5B and 5C according to the value of the output value D. And an integration type A / D conversion step in which the first storing step is repeated a predetermined number of times.

  The calculated value at this time is expressed by the following equation (5).

Here, [Delta] V _R in the formula (5) is expressed by the following equation (6).

In the integration type A / D conversion step, the calculation value V _OP when the first calculation step and the first storage step are repeated M times to perform sampling and integration is expressed by the following equation (7). .

As shown in the second term on the right side of Equation (7), the analog signal _VIN that is the input signal is multiplied by a half gain, sampling is performed M times, and folding integration type A / D conversion is performed. And the amplitude range of the output (calculated value V _OP ) is the same as the input signal.

FIG. 6 is a diagram showing input / output characteristics at the time of operation as an integral A / D converter (folded integral A / D conversion) of the gain stage 15 obtained by simulation. FIG. 6A shows the input / output characteristics under the conditions of (V _RH = 2V, V _RL = 1V, reference voltage V _RI = V _RL , V _COM = 1.5 V, number of samplings M = 16 in the arithmetic operation). FIG. As shown in FIG. 6A, the output is 1 to 2V with respect to the input of 1.5V to 2.5V with an amplitude of 1V, and the amplitude is within the range of 1V.

The above description is an example in which the second reference voltage _VRL is adopted as the reference voltage _VRI in the arithmetic operation. That is, in FIGS. 5A and 5D, the second reference reference voltage _VRL is supplied to the second capacitor 27. On the other hand, the first reference voltage _VRH may be adopted as the reference voltage _VRI in the calculation operation. When the first standard reference voltage V _RH is employed, the absolute value of the output is different from that when the second standard reference voltage V _RL is employed. In this case, the equation (7) is transformed into the following equation (8).

FIG. 6B shows the conditions of (V _RH = 2.5 V, V _RL = 1.5 V, reference voltage V _RI = V _RH , V _COM = 2.0 V, sampling count M = 16 in the operation). It is a figure which shows the input-output characteristic in. As shown in FIG. 6 (b), the output is 1.5 to 2.5V with respect to the input of 1.0V to 1.0V and the amplitude is within the range of 1V. It has been.

Here, when the first and second conversion reference voltages V _RCH and V _RCL supplied to the comparators 17a and 17b are changed as compared with the input / output characteristics shown in FIG. Shown in In the example of the input / output characteristics shown in FIG. _6A , the first and second conversion reference voltages V _RCH and V _RCL have the values shown below.

V _RCH = (3V _RH + V _RL ) /4=1.75V
V _RCL = (V _RH + 3V _RL ) /4=1.25V

On the other hand, in the example of the input / output characteristics shown in FIG. 7, the first and second conversion reference voltages V _RCH and V _RCL are values shown below.

V _RCH = (5V _RH + 3V _RL ) /8=1.625V
V _RCL = (3V _RH + 5V _RL ) /8=1.375V

As shown in FIG. 7, when the first and second conversion reference voltages V _RCH and V _RCL are changed, the integral A / D conversion in the gain stage 15 is not suitably performed. Therefore, the first and second conversion reference voltages V _RCH and V _RCL are preferably set to values as when the input / output characteristics of FIG. _6A are obtained.

  Depending on whether the correlated double sampling (CDS) for the signal from the image sensor cell is performed in the analog domain (analog CDS) or in the digital domain (digital CDS), an integral A / D conversion which is a so-called folded integral A / D conversion is performed. The input signal in the D conversion step and the cyclic A / D conversion performed after the integration A / D conversion are different. FIG. 8A is a diagram illustrating processing timing in one horizontal readout period when analog CDS is performed. FIG. 8B is a diagram showing processing timing in one horizontal readout period when digital CDS is performed.

As shown in FIG. 8A, when analog CDS is performed, an analog signal V _IN that is input to the gain stage 15 is a first signal that is output from the image sensor cell and indicates a reset level in the period S _fr1 . Integral A / D conversion is performed (first reset level integral A / D conversion step). Subsequently, in the period _Sfs1 , the integration type A / D conversion is performed by using the second signal indicating the signal level superimposed on the reset level as the analog signal _VIN input to the gain stage 15 (first signal). Level integration type A / D conversion step). In the first signal level integration type A / D conversion step, as described later with reference to FIG. 9, the polarity of the charge transferred to the third capacitor 29 serving as an integrator is changed to the first reset level. The calculation is performed so as to be opposite to the level integration type A / D conversion step. Thereby, the value of the upper bit in the digital value obtained by A / D converting the signal level is obtained. In the digital value obtained here, noise is canceled. Then, in the period _Scs1 , cyclic A / D conversion is performed using a residual analog signal obtained as a result of the first signal level integration A / D conversion step as an input signal. Thereby, the value of the lower bit in the digital value obtained by A / D converting the signal level is obtained.

Further, as shown in FIG. 8B, when digital CDS is performed, an analog signal input from the image sensor cell to the gain stage 15 is output from the image sensor cell during the period _Sfr2 . Integral A / D conversion is performed as _VIN (integral A / D conversion step for the first signal). Thereby, the value of the upper bit in the digital value obtained by A / D converting the reset level is obtained. Subsequently, in the period S _cr2 , cyclic A / D conversion is performed using the residual analog signal obtained as a result of the integral A / D conversion step for the first signal as an input signal (cyclic for the first signal). Type A / D conversion step). Thereby, the value of the lower bit in the digital value obtained by A / D converting the reset level is obtained. Accordingly, a digital value obtained by A / D-converting the reset level is obtained in the period S _fr2 and the period S _cr2 .

Subsequently, in the period Sfs2, integral A / D conversion is performed with the second signal indicating the signal level superimposed on the reset level as the analog signal _VIN input to the gain stage 15 (for the second signal). Integration type A / D conversion step). Thereby, the value of the upper bit in the digital value obtained by A / D converting the second signal is obtained. Then, in the period _Scs2 , cyclic A / D conversion is performed using a residual analog signal obtained as a result of the integral A / D conversion step for the second signal as an input signal. Thereby, the value of the lower bit in the digital value obtained by A / D converting the second signal is obtained. Therefore, in the period _Sfs2 and the period _Scs2 , a digital value obtained by A / D converting the reset signal is obtained. Accordingly, a digital value obtained by A / D converting the second signal is obtained in the period _Sfs2 and the period _Scs2 . Then, by subtracting the digital value obtained in the period S _fr2 and the period S _cr2 from the digital value obtained in the period S _fs2 and the period S _cs2 , the signal level in which the output variation and noise between cells are canceled. Can be obtained.

Next, the operation of the cyclic A / D conversion as the cyclic A / D conversion step in the A / D conversion circuit 111 will be described with reference to FIG. This cyclic A / D conversion is performed, for example, in the periods S _cs1 , S _cr2 , S _cs2 in FIG.

First, the gain stage 15 performs a second storing operation as a second initial storing step as shown in FIG. In this step, the residual analog that is the calculation value V _OP in the first signal level integration type A / D conversion step (period S _fs1 ) or the integration type A / D conversion step (period S _fr2 or period S _fs2 ). The signal is stored in the first, second and third capacitors 25, 27 and 29. In this step, the control signal (φ _DH = 0, φ _DS = 1, φ _DL = 0) and the clock signal (φ ₁ = 1, φ ₂ = 0, φ ₃ = 1, φ _R = 0, φ _S = 0 ), The switches 31c, 47, 51 are turned on, and the switches 31a, 31b, 43, 49, 53 are turned off. In this step, the operation value V _OP in the first signal level integration type A / D conversion step or the integration type A / D conversion step is provided to the comparators 17a and 17b. The comparators 17a and 17b generate digital signals B ₁ and B ₀ based on the provided operation value V _OP .

Subsequently, the gain stage 15 follows the second initial storage step as a second calculation step shown in FIG. 9B or FIG. 9C according to the value of D (= B ₁ + B ₀ ). The second calculation operation is performed. In the second calculation operation, the gain stage 15 generates a calculation value V _OP by the calculation amplifier circuit 23 and the capacitors 25, 27, and 29. In the second arithmetic operation, the third capacitor 29 is connected between the output 15b of the operational amplifier circuit 15 and the input 15a, and the first capacitor 25 is connected to the first output 21a and the first input 23a. And the second capacitor 27 is connected between the second output 21b and the first input 23a. In the second calculation step, the switch 49 is turned on by the clock signals (φ ₁ = 0, φ ₂ = 1, φ ₃ = 0, φ _R = 0, φ _S = 0), and the switches 47, 51, 53, 43 is made non-conductive.

The first output 21a and the second output 21b of the D / A conversion circuit 21 are controlled by the switch circuit 31 in accordance with the output value D (= B ₁ + B ₀ ) from the comparators 17a and 17b. Refer to the first reference. A voltage V _RH or a second reference voltage V _RL is provided.

  The comparators 17a and 17b operate as follows.

When V _OP > V _RCH D = 2 (B ₁ = 1, B ₀ = 1)
When V _RCL <V _OP ≦ V _RCH D = 1 (B ₁ = 0, B ₀ = 1)
When V _OP ≦ V _RCL D = 0 (B ₁ = 0, B ₀ = 0)

When D = 2, the operation shown in FIG. 9B is performed while the first reference reference voltage _VRH is controlled to be provided from the first output 21a and the second output 21b of the D / A conversion circuit 21. Done. On the other hand, when D = 0, the second reference reference voltage _VRL is controlled so as to be provided from the first output 21a and the second output 21b of the D / A conversion circuit 21 as shown in FIG. 9B. Operation is performed. Further, when D = 1, the first reference reference voltage V _RH and the second reference reference voltage V _RL are provided from the first output 21 a and the second output 21 b of the D / A conversion circuit 21, respectively. The operation shown in FIG. 9C is performed while being controlled.

  Subsequently, the gain stage 15 performs the second storage operation as the second storage step shown in FIG. 9A following the second calculation step.

The second storage step is different from the second initial storage step in that the calculation value V _OP in the second calculation step is stored in the first, second, and third capacitors 25, 27, and 29.

  Then, the gain stage 15 repeats the second calculation step and the second storage step a predetermined number of times as the cyclic A / D conversion step.

Next, with reference to FIG. 10, for example, an integral A / D conversion operation performed in the period S _fs1 in FIG. FIG. 10 shows an example of the integral type A / D conversion operation for the second signal indicating the signal level superimposed on the reset level when the analog CDS is performed as described above. That is, the polarity of the charge transferred to the capacitor constituting the integrator is opposite to the integral A / D conversion (see FIG. 5) performed on the first signal indicating the reset level. An A / D conversion operation is performed.

First, the gain stage 15 performs the first signal level storage shown in FIG. 10 (a) or FIG. 10 (b) according to the output value D in the calculation operation one step before. A first storing operation as a step is performed. In this step, the gain stage 15 connects the third capacitor 29 between the output 23b of the operational amplifier circuit 23 and the first input 23a, so that in the first reset level integral A / D conversion step. while maintaining the operation value _{V OP} to the capacitor C2, and stores the first standard reference voltage _{V RH} or second standard reference voltage _{V RL} supplied from the first output 21a to the first capacitor 25, first The first reference reference voltage V _RH or the second reference reference voltage V _RL supplied from the second output 21 b is stored in the second capacitor 27.

When D = 2, the operation of FIG. 10A is performed while being controlled so that the second reference reference voltage _VRL is provided from the first output 21a and the second output 21b of the D / A conversion circuit 21. Done. On the other hand, when D = 0, the first reference reference voltage _VRH is controlled so as to be provided from the first output 21a and the second output 21b of the D / A conversion circuit 21 as shown in FIG. Operation is performed. Further, when D = 1, the first reference reference voltage V _RH and the second reference reference voltage V _RL are provided from the first output 21 a and the second output 21 b of the D / A conversion circuit 21, respectively. The operation of FIG. 10B is performed while being controlled.

Subsequently, the gain stage 15 performs a first calculation operation as a first signal level calculation step shown in FIG. In this step, the gain stage 15 connects the first capacitor 25 between the input _VIN of the gain stage 15 to which the second signal is supplied and the first input 23a, and the second output 21b and the second output 21b. A second capacitor 27 is connected between the first input 23a.

After the first or second reference voltage is supplied to the first and second capacitors 25 and 27, the analog signal _VIN and the reference voltage V _RI in the operational amplifier circuit 23 are changed to the first and second capacitors 25 and 27. 27, the charge related to the analog signal _VIN is transferred to the integrator with the opposite polarity to the integral type A / D conversion shown in FIG.

When the reference voltage V _RI in the operational amplifier circuit 23 is (V _RI = V _RL ), the calculated value V _OP (M + 1) at this time is expressed by the following equation (9).

Furthermore, the calculated value V _OP (2M) when the first signal level calculation step and the first signal level storage step are repeated M times is expressed by the following equation (10).

Further, when V _RI = V _RH , the equation (10) is transformed into the following equation (11).

In the first reset level integration type A / D conversion step (first to Mth sampling and integration), the analog signal _VIN provided to the input 15a of the gain stage 15 is a reset level signal _VRES . In the first signal level integration type A / D conversion step (M + 1 to 2M sampling and integration), the analog signal _VIN provided to the input 15a of the gain stage 15 is a signal level signal V _SIG . Therefore, the expression (10) is expressed as the expression (12).

  Furthermore, Formula (12) is represented as the following Formula (13).

  Furthermore, Expression (13) is expressed as Expression (14) below using Expression (6).

Expression by performing the cyclic A / D conversion of m bits to _V OP (2M) in the right-hand side of (14), the first term on the right side of formula _{(14) (V OP (2M} ) -V COM) / (V _RH −V _RL ) is converted into a digital value that takes a value from −0.5 to 0.5. This digital value is represented by X as shown in the following formula (15).

Here, the parenthesis [] means a digital value of the value in the parenthesis.
Further, the value Y is expressed as in Expression (16).

  Expression (14) is expressed as Expression (17) below using values X and Y.

In the equation (17), the digital value for M (V _RES −V _SIG ) to be obtained is expressed by the result of the cyclic A / D conversion and the result of the folding integration A / D conversion (digital count value). Means that. If the result of the folding integration type A / D conversion is n bits, the A / D conversion circuit 111 of the present embodiment can perform A / D conversion to obtain a digital value of (n + m−1) bits. The digital count value, which is the result of the folding integration type A / D conversion, appears as 1 in the output value D (B ₁ + B ₀ or B ₁ ) by the counter circuit provided at the subsequent stage of the A / D conversion circuit 17. It is obtained by acquiring the number of times. The acquisition of the count value will be described later.

FIG. 11 is a diagram showing the relationship between the input level of the analog signal _VIN , which is an input signal corresponding to the simulation of FIG. 6, and the digital count value. As shown in FIGS. 11 (a) and 11 (b), the digital count value takes a value of 15 gradations for 16 samplings and integrations in the integral type A / D conversion and an input range of 1.0V. obtain. Therefore, the range of this digital count value is represented by about 4 bits.

の項は、入力レベルの範囲が１．０Ｖである場合に、０〜１４の範囲の値を取りうるので、４ビットで表される。従って、例えば、巡回型Ａ／Ｄ変換を１２ビットの出力結果が得られるように実施した場合には、カウンタ値の上位ビットを１ビットシフトして線形の信号を生成することから、本実施形態のＡ／Ｄ変換回路１１１は、１５ビット（＝（１２＋４−１）ビット）にほぼ相当するダイナミックレンジを有することができる。以上説明したように、本実施形態のＡ／Ｄ変換回路１１１は、折り返し積分型のＡ／Ｄ変換である積分型Ａ／Ｄ変換によるノイズ低減の効果を十分に得ながら、広いダイナミックレンジを有するディジタル信号の出力をすることができる。 In equation (13)

This term can be a value in the range of 0 to 14 when the input level range is 1.0 V, and is represented by 4 bits. Therefore, for example, when the cyclic A / D conversion is performed so that a 12-bit output result is obtained, the higher order bits of the counter value are shifted by 1 bit to generate a linear signal. The A / D conversion circuit 111 can have a dynamic range substantially corresponding to 15 bits (= (12 + 4-1) bits). As described above, the A / D conversion circuit 111 according to the present embodiment has a wide dynamic range while sufficiently obtaining the noise reduction effect by the integration type A / D conversion which is the folded integration type A / D conversion. A digital signal can be output.

  Next, a first A / D conversion operation when the A / D conversion circuit 17 generates the digital signal D using one comparator 17a will be described with reference to FIG.

In FIG. 12A, the gain stage 15 performs a first storing operation as a first initial storing step. In this step, the analog signal _VIN received via the input 15a of the gain stage 15 is stored in the first capacitor 25, and the output 23b of the gain stage 15 and the first input 23a are connected. The second capacitor 27 stores the second reference voltage _VRL supplied from the second output 21b, and the third capacitor 29 includes the output 23b of the operational amplifier circuit 23 and the first input 23a. Connected between.

Storage and connection in the first initial storage step and each step described below are realized by the switch circuit 31 and the switches 43, 47, 49, 51, 53. In the first initial storing step, the control signal (φ _DH = 0, φ _DS = 0, φ _DL = 1) and the clock signal (φ ₁ = 1, φ ₂ = 0, φ ₃ = 0, φ _R = 1, By φ _S = 1), the switches 31c, 47, 53, and 43 are turned on, and the switches 31a, 31b, 49, and 51 are turned off.

Subsequent to the first initial storage step, the A / D conversion circuit 111 performs the first calculation step shown in FIG. 12B or FIG. 12C according to the value of D (= B ₁ ). 1 calculation operation is performed.

In this step, the first calculation operation is performed by connecting the first capacitor 25 between the first output 21a and the first input 23a. The second capacitor 27 is connected between the second output 21b and the first input 23a, and the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a. As a result, the calculated value V _OP is generated at the output 15 b of the gain stage 15. In the first calculation step, the switch 49 is turned on by the clock signals (φ ₁ = 0, φ ₂ = 1, φ ₃ = 0, φ _R = 0, φ _S = 0), and the switches 47, 51, 53, 43 is made non-conductive.

The first output 21a and the second output 21b of the D / A conversion circuit 21 are supplied with the first reference reference voltage V by the control of the switch circuit 31 according to the output value D (= B ₁ ) from the comparator 17a. _RH or a second reference voltage _VRL is provided.

  The comparator 17a operates as follows.

When V _OP > V _RCH B ₁ = 1
When V _OP ≦ V _RCH B ₁ = 0

When D = 0 (B ₁ = 0), the first reference reference voltage V _RH and the second reference reference voltage V _RL are respectively obtained from the first output 21a and the second output 21b of the D / A conversion circuit 21. The operation shown in FIG. 12B is performed while being controlled to be provided. On the other hand, when D = 1, the second reference reference voltage _VRL is controlled so as to be provided from the first output 21a and the second output 21b of the D / A conversion circuit 21 as shown in FIG. Operation is performed.

Subsequently, the gain stage 15 performs the first storing operation shown in FIG. 12D as a first storing step. In the first storage step, while retaining the operation value V _OP to the capacitance C ₂ by connecting the third capacitor 29 between the output 23b and the first input 23a of the operational amplifier circuit 23, the gain stage The analog signal _VIN from the 15 inputs 15 a is stored in the first capacitor 25, and the second reference voltage V _RL supplied from the second output 21 b is stored in the second capacitor 27. In the first storing step, the control signal (φ _DH = 0, φ _DS = 0, φ _DL = 1) and the clock signal (φ ₁ = 1, φ ₂ = 0, φ ₃ = 0, φ _R = 0, φ _{With S} = 1), the switches 31c, 47, 43 are turned on, and the switches 31a, 31b, 49, 51, 53 are turned off.

  Next, the gain stage 15 selects the first calculation step and the first calculation while selecting one of the first calculation operations shown in FIGS. 12B and 12C according to the value of the output value D. The integration type A / D conversion step is performed by repeating the storing step a predetermined number of times.

FIG. 13 shows the operation of the gain stage 15 as an integration type A / D converter (folded integration type A / D conversion) when the A / D conversion circuit 17 generates the digital signal D using one comparator 17a. ) Is a diagram showing input / output characteristics obtained by simulation at the time. The conditions in this simulation are (V _RH = 2.5 V, V _RL = 1.5 V, reference voltage V _RI = V _RL , V _COM = 2.0 V, sampling and integration count M = 16 in the arithmetic operation). As shown in FIG. 13, the output is 1.5 to 2.5 V with respect to the input of 1.5 to 2.5 V and the amplitude is 1 V, and the amplitude is within the range of 1 V. .

Next, referring to FIGS. 14 to 16, a digital value as a result of the A / D conversion is generated based on the output value D of the folding integration type A / D conversion which is the first A / D conversion operation. The configuration of the digital unit DC for this purpose will be described. FIG. 14A is a diagram showing the digital unit DC _A when the A / D conversion circuit 17 generates the digital signal D using the two comparators 17a and 17b and the two conversion reference voltages V _RCH and V _RCL . is there. The digital part DC _A includes a complement part CP _A , an adder AD _A , a register RG _1A, and a register RG _2A . FIG. 15 is a diagram showing a detailed configuration of the complement unit CP _A , the adder AD _A , and the register RG _1A shown in FIG. In the example shown in FIG. 15, a 5-bit digital value is obtained. The operation of these configurations will be described below with reference to FIGS. 14 (a) and 15.

First, a reset signal reset is given to a 5-bit register RG _1A (consisting of five flip-flops FF), and their outputs are set to zero. The output of the register RG _1A and the 2-bit outputs (B ₁ , B ₀ ) from the two comparators 17a and 17b of the integration type A / D conversion are added for each integration cycle in the integration type A / D conversion. It is added by the vessel AD a _(consisting of _five full adders FA), in addition to the clock, and stores the output result in register RG _1A. By repeating these additions and storages, the 2-bit output is digitally integrated. When performing A / D conversion of the first signal indicative of a reset level, a signal C _omp provided to complement portion CP _A is set to 0. Thus, the output of the complement portion CP _{A is} a _{(X 2 = 0, X 3} = 0, X 4 = 0). When the input is (B ₀ = 0, B ₁ = 0), the output is (X ₀ = 0, X ₁ = 0), so no value is added. When the input is (B ₀ = 1, B ₁ = 0), the output is (X ₀ = 1, X ₁ = 0), so the value is incremented by one. Further, when the input is (B ₀ = 1, B ₁ = 1), the output is (X ₀ = 0, X ₁ = 1), so the value is incremented by two.

On the other hand, when performing the A / D conversion of the second signal indicative of a signal level sets the signal C _omp provided to complement portion CP _A to 1. Thus, the output of the complement portion CP _{A is} a _{(X 2 = 1, X 3} = 1, X 4 = 1). When the input is (B ₀ = 0, B ₁ = 0), the output is (X ₀ = 0, X ₁ = 0, X ₂ = 0, X ₃ = 0, X ₄ = 0) Is not added. When the input is (B ₀ = 1, B ₁ = 0), the output is (X ₀ = 1, X ₁ = 1, X ₂ = 1, X ₃ = 1, X ₄ = 1). Is considered as a 2's complement, the values are added by -1. Further, when the input is (B ₀ = 1, B ₁ = 1), the output is (X ₀ = 0, X ₁ = 1, X ₂ = 1, X ₃ = 1, X ₄ = 1). Is considered as a two's complement, the value is added by -2.

With the above configuration, each time integration is repeated for each of the reset level and the signal level, the number of times the reference voltage is pulled back is counted, and the number corresponding to the difference between the two is finally stored in the register RG _1A . That is, such a configuration can be employed in the acquisition of a digital value by digital CDS as described with reference to FIG. Register RG _2A stores a digital value obtained as a result of cyclic A / D conversion.

14 (b) is a diagram illustrating a digital section DC _B in the A / D conversion circuit 17 generates a digital signal D by using one comparator 17a and one conversion reference voltage _{V RCH.} The digital part DC _B includes a complement part CP _B , an adder AD _B , a register RG _1B, and a register RG _2B . FIG. 16 is a diagram showing a detailed configuration of the complement unit CP _B shown in FIG. The configurations of the adder AD _B and the register RG _1B are the same as those shown in FIG. In the example shown in FIG. 16, a 5-bit digital value is obtained. Hereinafter, the operation of these configurations will be described with reference to FIGS.

First, a reset signal reset is given to a 5-bit register RG _1B (consisting of five flip-flops FF), and their outputs are set to zero. For each integration cycle in the integration type A / D conversion, the output of the register RG _1B and the 1-bit output (B ₁ ) from one comparator 17a of the integration type A / D conversion are added to the adder AD _B (5 Are added by a full adder FA), a clock is added, and the output result is stored in the register RG _1B . By repeating these additions and storages, the 1-bit output is digitally integrated. When the A / D conversion of the first signal indicating the reset level is performed, the signal C _comp provided to the complement unit CP _B is set to 0. As a result, the output of the complement unit CP _B is (X ₁ = 0, X ₂ = 0, X ₃ = 0, X ₄ = 0). When the input is (B ₁ = 0), the output is (X ₀ = 0), so no value is added. When the input is (B ₁ = 1), the output is (X ₀ = 1), so the value is incremented by one.

On the other hand, when the A / D conversion of the second signal indicating the signal level is performed, the signal C _comp provided to the complement unit CP _B is set to 1. As a result, the output of the complement unit CP _B becomes (X ₁ = 0, X ₂ = 1, X ₃ = 1, X ₄ = 1). When the input is (B ₁ = 0), the output is (X ₀ = 0, X ₁ = 0, X ₂ = 0, X ₃ = 0, X ₄ = 0), and the values are added. Absent. When the input is (B ₁ = 1), the output is (X ₀ = 1, X ₁ = 1, X ₂ = 1, X ₃ = 1, X ₄ = 1). When considered, values are added by -1.

With the configuration as described above, each time integration is repeated for each of the reset level and the signal level, the number of times the reference voltage is pulled back is counted, and the number corresponding to the difference between the two is finally stored in the register RG _1B . That is, such a configuration can be employed in the acquisition of a digital value by digital CDS as described with reference to FIG. Register RG _2B stores a digital value obtained as a result of cyclic A / D conversion.

According to the A / D conversion circuit 111 according to the first embodiment described above, the first A for performing the folding integration type A / D conversion by controlling the operation procedure in the same circuit configuration. A / D conversion operation and a second A / D conversion operation for performing cyclic A / D conversion are realized. Further, in the first A / D conversion operation, the capacitance of the third capacitor 29 used for integration of the output signal is the first and second used for storing the analog signal to be A / D converted and the reference reference voltage. Therefore, the analog signal _VIN input in the folding integration type A / D conversion is attenuated according to the capacitance ratio and sampled and integrated. For this reason, the voltage range of the analog signal output in the folding integration type A / D conversion is also reduced according to the capacitance ratio of the capacitor, so that the A / D converter can be configured by a single end configuration.

  The above first embodiment is summarized as follows.

The first embodiment of the present invention is a single-ended A / D converter. The A / D converter includes an input for receiving an analog signal to be converted into a digital value, an output, a gain stage including an operational amplifier circuit having a first input, a second input and an output, and an output of the gain stage. An A / D conversion circuit that generates a digital signal including one or more bits with reference to the conversion reference voltage, a logic circuit that generates a control signal according to the digital signal, D / having a second output and providing at least one of the first reference reference voltage and the second reference reference voltage to the gain stage via the first and second outputs according to the control signal A conversion circuit.
The gain stage includes first to third capacitors, and the capacitance of the third capacitor is larger than the capacitances of the first and second capacitors, the second input of the operational amplifier circuit receives the reference potential, The first reference voltage is higher than the second reference voltage value, and the D / A converter circuit provides either the first or second reference voltage to the first output in response to the control signal. And a switch circuit for providing either the first or second reference voltage to the second output.
The A / D converter performs a first A / D conversion operation and a second A / D conversion operation. In the first A / D conversion operation, the gain stage includes an operational amplifier circuit and first to first A / D conversion operations. A first calculation operation for generating a calculation value by the third capacitor and a first storage operation are performed. In the first storage operation, the first capacitor is supplied from the first output. Alternatively, the second reference voltage or analog signal is stored, the second capacitor stores the first or second reference voltage supplied from the second output, and the third capacitor is an operational amplifier circuit. Between the first output and the first input.
In the first calculation operation, when the first or second reference reference voltage is stored in the first capacitor in the first storage operation, the first capacitor receives an analog signal and the first input When the analog signal is stored in the first capacitor in the storing operation, the first capacitor is connected between the first output and the first input, and the second capacitor Is connected between the second output and the first input, and the third capacitor is connected between the output of the operational amplifier circuit and the first input, so that the calculated value becomes the output of the gain stage. Generated.
In the second A / D conversion operation, the gain stage stores the calculation value in the first and second capacitors, the second calculation operation for generating the calculation value by the operational amplifier circuit and the first to third capacitors. In the second calculation operation, a third capacitor is connected between the output of the operational amplifier circuit and the first input, and the first and second capacitors are respectively connected to D / It is connected between the 1st or 2nd output of A conversion circuit, and the 1st input, and an operation value is generated in the output of the gain stage concerned, It is characterized by the above-mentioned.

  According to this A / D converter, by controlling the operation procedure in the same circuit configuration, the first A / D conversion operation for performing the folding integration type A / D conversion and the cyclic A A second A / D conversion operation for performing / D conversion is realized. In the first A / D conversion operation, the capacitance of the third capacitor used for integration of the output signal is the first and second used for storing the analog signal to be A / D converted and the reference reference voltage. Since it is larger than the capacitance of the capacitor, the analog signal input in the folding integration type A / D conversion is attenuated according to the capacitance ratio and sampled and integrated. Therefore, the voltage range of the analog signal output in the folding integration type A / D conversion is also reduced in accordance with the capacitance ratio of the capacitor, so that the A / D converter can be configured with a single end configuration.

  In the A / D converter, the third capacitor has a capacity twice as large as that of the first or second capacitor.

  Furthermore, according to this A / D converter, the analog signal input in the folding integration type A / D conversion is attenuated to ½ and sampled and integrated. Therefore, the voltage range of the analog signal output in the folding integration type A / D conversion is also halved according to the capacitance ratio of the capacitor. Therefore, in the cyclic A / D conversion, the single-ended A / D conversion is performed. An input voltage suitable for the converter is provided.

  Furthermore, in this A / D converter, the conversion reference voltage is a median value between the first standard reference voltage and the second standard reference voltage value, and the A / D conversion circuit is a 1-bit digital signal. The signal is generated, and the logic circuit generates a control signal having first and second values.

  In addition, according to this A / D converter, a digital signal is generated based on one appropriately set conversion reference voltage, so that the A / D converter circuit can be easily configured and the generated digital signal A circuit having a simple configuration can also be adopted.

Further, in this A / D converter, the first conversion reference voltage V _RC2H and the second conversion reference voltage V _RC2L in the second A / D conversion operation are expressed by the following equations, respectively.
V _RC2H = (5V _RH + 3V _RL ) / 8
V _RC2L = (3V _RH + 5V _RL ) / 8
It is characterized by that. According to this A / D converter, the second A / D conversion operation is appropriately performed.

  Still further, in this A / D converter, the A / D converter circuit has first and second conversion reference voltages, and the first conversion reference voltage includes the first reference voltage and the second reference voltage. The first conversion reference voltage in the first A / D conversion operation is higher than the median value between the reference voltage values and lower than the first reference reference voltage, and the first conversion reference voltage in the second A / D conversion operation is The second conversion reference voltage is higher than the conversion reference voltage, the second conversion reference voltage is lower than the median value and higher than the second reference reference voltage, and the second conversion reference voltage in the first A / D conversion operation is the second A / D Lower than the second conversion reference voltage in the D conversion operation, the A / D conversion circuit generates a ternary digital signal, and the logic circuit generates a control signal having the first to third values. Features.

  Further, according to this A / D converter, since the conversion reference voltage is set to an appropriate voltage, the first A / D conversion operation and the second A / D conversion operation are appropriately performed.

Further, in this A / D converter, when the first standard reference voltage is V _RH and the second standard reference voltage is V _RL , the first conversion reference voltage in the first A / D conversion operation. V _RC1H and the second conversion reference voltage V _RC1L are respectively expressed by the following equations:
V _RC1H = (3V _RH + V _RL ) / 4
V _RC1L = (V _RH + 3V _RL ) / 4
The first conversion reference voltage V _RC2H and the second conversion reference voltage V _RC2L in the second A / D conversion operation are expressed by the following equations, respectively.
V _RC2H = (5V _RH + 3V _RL ) / 8
V _RC2L = (3V _RH + 5V _RL ) / 8
It is characterized by that. According to this A / D converter, the second A / D conversion operation is appropriately performed.

  In the A / D converter, in the first storing operation, the first capacitor is connected between the first output or the input of the gain stage and the reference potential, and the second capacitor is connected to the first capacitor. The second output or the gain stage is connected between the input and the reference potential.

  Still further, according to the A / D converter, the reference signal supplied by the first output or the analog signal supplied from the input of the gain stage is stored in the first capacitor and supplied by the second output. The reference signal or the analog signal supplied from the input of the gain stage is stored in the second capacitor.

  Another aspect of the second embodiment of the present invention is an image sensor device. The image sensor device includes a cell array including an array of image sensor cells and a converter array connected to the cell array and including a plurality of A / D converters. Each of the A / D converters is a column of the cell array. The A / D converter is connected to the image sensor cell via a line, and each A / D converter is the A / D converter described above. According to this image sensor device, since the A / D converter is configured as a single end type, the area of the image sensor device can be reduced.

Second embodiment.
FIG. 17 is a block diagram showing a configuration of a CMOS image sensor 101 according to the second embodiment of the present invention. FIG. 18 is a block diagram showing the configuration of the digital correction circuit 112 of FIG. The CMOS image sensor 101 according to the second embodiment uses the integration / cyclic A / D converter according to the first embodiment that sequentially performs the folding integration type A / D conversion and the cyclic type A / D conversion. In order to obtain linearity equivalent to, for example, 14 bits, digital correction is performed for the following errors between the folded integration type A / D conversion circuit and the cyclic type A / D conversion circuit. A digital correction circuit 112 is provided.
(1) Random and systematic mismatch errors of capacitors.
(2) An error associated with the finite gain of the operational amplifier circuit.
(3) Settling error of the operational amplifier circuit (in the case of a small error that can be handled as a linear).

  In the CMOS image sensor 101 of FIG. 17, the cell array 102 has CMOS image sensor pixels 102a arranged in the row direction and the column direction. FIG. 17 shows an example of the CMOS image sensor pixel 102a. The pixel 102a generates the first signal S1 in the reset state and the second signal S2 in the light induced signal output. An input terminal of the A / D conversion circuit 111 in the integration / cyclic ADC array 104 is connected to the pixel 102a.

  In the CMOS image sensor 101, a vertical shift register 103 is connected to a row of the cell array 102, and an A / D converter array 104 is connected to a column of the cell array 102 to read an image. The A / D converter array 104 includes a plurality of A / D conversion circuits 111 arranged in an array. A data register 105 is connected to the A / D converter array 104, and an A / D conversion value corresponding to a signal from the pixel 102 a is stored in the data register 105. In response to the signal from the horizontal shift register 106, the data register 105 provides a digital signal to the redundant representation / non-redundant representation conversion circuit 107 via the digital correction circuit 112 that performs the digital correction. Here, the A / D conversion circuit 111 and the digital correction circuit 112 constitute an N-bit A / D conversion device, and the redundant expression / non-redundant expression conversion circuit 107 has N bits corresponding to the signal from the pixel 102a. Generates a digital code.

In the pixel 102a, the photodiode PD receives light for one pixel related to the image. The gate of the selection transistor M _S is connected to the row select line S extending in the row direction. The gate of the reset transistor M _R is connected to the reset line R. The gate of the transfer transistor M _T is connected to the transfer selection line extending in the row direction. One end of the photodiode PD is connected to the floating diffusion layer FD via the transfer transistor M _T. Floating diffusion layer FD is connected to a reset potential line Reset via the reset transistor M _R, is connected to the gate of the transistor M _A. One current terminal (for example, drain) of the transistor M _A is connected to the column line 108 via the selection transistor M _S. Transistor M _A is a potential according to the charge amount of the floating diffusion layer FD, provides to the column line 108 through the selection transistor M _S.

In the pixel 102a having this structure, the noise canceling operation is performed as follows. First, to provide a reset control signal R to the reset transistor M _R, it resets the floating diffusion layer FD. Through the amplification transistor M _A, read out the reset level. Then, a charge transfer control signal TX is supplied to the transfer transistor M _T, is transferred from the photodiode PD the photo-induced signal charge to the floating diffusion layer. Thereafter, through the transistor M _A, reading the signal level. The difference between the reset level and the signal level is obtained by using, for example, an integration / cyclic cascade A / D converter as shown in FIG. This cancels noise such as fixed pattern noise caused by variations in transistor characteristics of the pixel 102a and reset noise generated when the floating diffusion layer is reset.

In FIG. 18, the digital correction circuit 112 temporarily stores various parameters m ₁ , M ₁ , D (i), D ₁ (i) (details will be described later) output from the A / D conversion circuit 111. Based on the register 70 and various parameters m ₁ , M ₁ , D (i), D ₁ (i) from the register 70, errors E _FI , E _FR , E _g1 , E _m1 in equation (18) to be described later are obtained. Based on the calculation units 71 to 74 to be calculated, the errors E _FI , E _FR , E _g1 , E _m1 calculated by the calculation units 71 to 74 and the output voltage digital signal Vo (M) from the A / D conversion circuit 111. And a corrected output value calculation unit 75 for calculating the corrected output value. Here, each calculation part 71-75 is comprised, for example using a digital signal processor (DSP), and performs calculation mentioned later in detail.

  Next, the digital correction method of the digital correction circuit 112 will be described in detail below.

Here, the circuit of FIG. 12 is used in the operation of each phase of the folded integration type A / D converter in the A / D conversion circuit 11 in the integration / cyclic type ADC array 4 of FIG. Hereinafter, the operation of the folded integration type A / D conversion will be described with reference to FIG. Capacitance C to which the reference potential V _COM is applied to the non-inverting input terminal of the operational amplifier circuit 23 of the A / D conversion circuit 111 of the integrating / cyclic ADC array 104 and the input voltage _VIN is applied to the inverting input terminal. _1a, the capacitor _{C 1} consisting of _{C 1b,} the reference voltage _{V RL} is connected to the capacitor _{C 2} to be applied.

First, the output terminal and the inverting input terminal of the operational amplifier circuit 23 are connected, and the operational amplifier circuit 23 is reset (FIG. 12 (a)). Next, after connecting the capacitor C ₂ between the output terminal and the inverting input terminal of the operational amplifier circuit 23, the reference voltage V _RL is applied to the inverting input terminal of the operational amplifier circuit 23 via the capacitor C ₁ , and the operational amplification is performed. Multiple sampling integration is performed with a gain of 1/2 using the circuit 23 (FIG. 12B). Here, the first two integrations are performed without folding. From the third time onward, folding integration is performed by outputting to the operational amplifier circuit 23 of the next stage via the 1-bit A / D converter 23A with the threshold V _T = (V _RH + V _RL ) / 2 (FIG. 12). (C) and (d)). If the reference potential V _COM (V _c ) = V _RL , the lower limit of the A / D conversion range of the folding integration can be set to V _RL . Hereinafter, a case where V _COM (V _c ) = V _RL is selected will be described. The operation of the folding integration type A / D conversion has been described in detail above with reference to FIG.

  FIG. 19 is a graph showing input / output voltage characteristics showing the operation of the folded integration type A / D converter of FIG. An ideal calculation that does not include an error (no folding integration until the second time) is performed as follows. 19, (a) shows the first (# 1) integration operation, (b) shows the second (# 2) integration operation, and (c) shows the third (# 3) folding integration operation. (D) shows the fourth (# 4) folding operation.

The output voltage V _o (1) of the first integration operation (# 1) is expressed by the following equation.
V _o (1) = 0.5 (V _in (1) −V _RL ) + V _RL
The output voltage V _o (M) of the Mth (#M) integration operation is expressed by the following equation. A detailed method for deriving the formula is described at the end of the specification.
V _o (M)
= 0.5 (V _in (M) −V _RI (M)) + V _o (M−1)
= 0.5 {MV _in- (M-M ₁ ) V _RL -M ₁ V _RH } + V _RL
here,
D _I (i)
= 0 (when V _o (i) ≦ V _T )
= 1 (when V _o (i)> V _T )
V _RI (i)
= _V RL _(D I _(when i-1) = 0)
= V _RH (when D _I (i-1) = 1)
It is. here,
ΔV _R = (V _RH −V _RL ) / 2
X = 0.5 (V _in −V _RL ) / ΔV _R
Y = (V _oF (M) −V _RL ) / ΔV _R
Then, the following equation is obtained.
MX = Y + M ₁

Therefore, for input voltage V _in = V _{RL to} V _RH and output voltage V _oF (M) = V _{RL to} V _RH , X = 0 to 1, Y = 0 to 2, M ₁ = 0 to M−2. On the other hand, Y + M ₁ = 0 to M and MX = 0 to M coincide with each other.

  Next, errors in the folding integration type A / D conversion will be described below. The error in the folded integration type A / D conversion includes a finite gain error relating to the operational amplifier circuit 23 and its peripheral circuits, and a mismatch error of a capacitor relating to the capacitor connected to the operational amplifier circuit 23.

(1) The finite gain error is expressed by the following equation.
_{e fg, FI = (C FI1} + C FI2 + C FIi) / (C FI2 A FI)
_{e fg2, FI = (C FI2} + C FIi) / (C FI2 A FI)
_{e fg1, FI = C FI1 /} (C FI2 A FI) = e fg, FI -e fg2, FI
Here, A _FI is an open-loop DC gain of the operational amplifier circuit 23, C _FI2 is a feedback side capacitor, and C _FI1 is an input side capacitor. _{Incidentally, C FI1} may vary depending embodiment, in the second _{embodiment, C FI1 = C 1a + C} 1b, in the third _embodiment, it is _C FI1 ₌ C _F1a. C _FIi is an input capacitance of the operational amplifier circuit 23.

(2) The capacitor mismatch error is expressed by the following equation in the second embodiment.
_{C FI1 = C FI2 + ΔC FI2} ( Second Embodiment)
here,
_{em , FI} = ΔC _FI2 / C _{FI2
C FI1 / C FI2 = (1} + e m, FI)
far.
In 3rd Embodiment, it represents with following Formula.
C _FI1 = 0.5 (C _FI2 + ΔC _FI2 ) (third embodiment)
here,
_{em , FI} = ΔC _FI2 / C _{FI2
C FI1 / C FI2 = 0.5 (} 1 + e m, FI)
far.

  Next, errors in cyclic A / D conversion will be described below. The error in the cyclic A / D conversion includes a finite gain error relating to the operational amplifier circuit 23 and its peripheral circuits, and a capacitor mismatch error relating to the capacitor connected to the operational amplifier circuit 23.

(1) The finite gain error is expressed by the following equation.
e _fg = (C _1a + C _1b + C ₂ + C _i ) / (C ₂ A)
e _fg2 = (C ₂ + C _i ) / (C ₂ A)
e _fg1 = (C _1a + C _1b ) / (C ₂ A) = e _fg −e _fg2
Here, A is the open loop DC gain of the operational amplifier circuit 23, C ₂ is the feedback side capacitor. Further, C ₁ is an input side capacitance, and is divided into C _1a and C _1b , where C ₁ = C _1a + C _1b . Further, C _i is an input capacitance of the operational amplifier circuit 23.

(2) The capacitor mismatch error is expressed by the following equation.
C ₁ = C ₂ + ΔC ₂
C _1a = 0.5 (C ₁ + ΔC ₁ )
C _1b = 0.5 (C ₁ −ΔC ₁ )
here,
e _m2 = ΔC ₂ / C ₂
e _m1 = ΔC ₁ / C ₁
far. e _m1 is an error due to mismatch in capacitor _{C 1a} and the capacitor _{C 1b, e m2} is the error caused by the mismatch of capacitance _{C 1} and the capacitance _{C 2.} At this time, the following equation is obtained.
C _1a / C ₂ = (1/2) (1 + e _m2 ) (1 + e _m1 ) ≈ (1/2) (1 + e _m2 + e _m1 )
C _1b / C ₂ = (1/2) (1 + _{em 2} ) (1-e _m1 ) ≈ (1/2) (1 + _{em 2} −em ₁ )
C ₁ / C ₂ = 1 + e _m2

  Next, the basic operation of the cyclic A / D conversion will be described below. A detailed formula derivation method is described at the end of the specification.

The output voltage Vo (i) of the i-th cyclic A / D conversion is expressed by the following equation.
V _o (i)
_{≒ (2 + e m2 + e} fg2 -e fg) V o (i-1) - (1 + e m2 -e fg) V RH
(When D (i) = 2)
V _o (i)
_{≒ (2 + e m2 + e} fg2 -e fg) V o (i-1)
− (1 + _{em 2} −ef _g ) (V _RH + V _RL ) / 2 + ( _em 1/2) (V _RH −V _RL )
(When D (i) = 1)
V _o (i)
_{≒ (2 + e m2 + e} fg2 -e fg) V o (i-1) - (1 + e m2 -e fg) V RL
(When D (i) = 0)

here,
_{g 1 = e m2 + e fg2} -e fg
g ₂ = _e m2 _{-e fg}
ΔV _R = (V _RH −V _RL ) / 2
D ₁ (i)
= 1 (when D (i) = 1)
= 0 (when D (i) = 0, 2)
The following formula is obtained.

V _o (i)
≈ (2 + g ₁ ) V _o (i−1) − (1 + g ₂ ) ΔV _R D (i)
+ E _m1 ΔV _R D ₁ (i) − (1 + g ₂ ) V _RL

  Next, the operation of the folding integration type A / D conversion including the error will be described below.

The folded integration type A / D conversion including the error operates as follows.
X = (V _in −V _RL ) / (2ΔV _R )
Y = (V _o (M) −V _RL ) / ΔV _R
E _F = ((M−1) / 2) e _{fg1, FI}
It is expressed by the following formula.
M (1-E _F ) _{X≈M 1} −m ₁ e _{fg1, FI} + (1 + e _{fg, FI} −em _{, FI} ) Y

here,
D _I (i)
= 0 (when V _o (i) ≦ V _T )
= 1 (when V _o (i)> V _T )
It is.

  Next, the operation of cyclic A / D conversion including the error will be described below.

The cyclic A / D conversion including the error operates as follows.
Y≈ {(1 + g ₂ ) / (1 + 0.5 g ₁ )} Y ₀ + E _g1 + E _m1

Accordingly, error correction of the integration / cyclic A / D conversion circuit that sequentially performs the folding integration A / D conversion and the cyclic A / D conversion is performed by the digital correction circuit 112 using the following equation.
M (1-E _F ) X≈M ₁ + Y ₀ + E _FI + E _FR + E _g1 + E _m1 (18)
here,
E _FI ≒ -m ₁ e _{fg1, FI}
E _FR ≈− (e _{fg, FI} −em _{, FI} + g ₂ −0.5 g ₁ ) M ₁

Here, in the above equation (18), M is the number of integrations, and M ₁ is the number of folding times. Here, the number of integrations M is obtained by, for example, counting the number of occurrences of, for example, 1 in the output signal of the comparator 17b of FIG. 1, and accumulating it by a circuit similar to the cascade connection circuit of the adder and register of FIG. It can be measured. Further, X is a parameter corresponding to the input voltage V _in, Y ₀ is a parameter corresponding to the output voltage. Further, the error parameters e _{fg1, FI,} e _{fg, FI} , g ₁ , g ₂ , and em ₁ are measured in advance as will be described later, and stored in the calculation units 71 to 74 of the digital correction circuit 112 in FIG. Value. Incidentally, E _F is the gain correction term of folded integral type A / D converter circuit, it can be omitted because it does not affect the linearity. The offset term can be omitted because it can be canceled by the subsequent digital CDS circuit.

The calculation units 71 to 74 of the digital correction circuit 112 shown in FIG. 18 use the error E in the above equation (18) based on various parameters m ₁ , M ₁ , D (i), and D ₁ (i) from the register 70. _FI , E _FR , E _g1 , and E _m1 (all of which are digital values) are calculated using the above equations and output to the corrected output value calculation unit 75. The corrected output value calculation unit 75 is based on the errors E _FI , E _FR , E _g1 , E _m1 calculated by the calculation units 71 to 74 and the output voltage digital signal Vo (M) from the A / D conversion circuit 111. To calculate and output the corrected output value.

  Next, a specific digital correction method in the digital correction circuit 112 will be described below.

(1) Method M1: a method for correcting only the error _{E FR} of the right side of the equation (18), has the following characteristics.
(A) Since no circuit is added to each column circuit, the circuit configuration of the digital correction circuit 112 is simplified.
(B) There is no increase in the number of horizontal signal lines and circuits for reading correction signals from the A / D conversion circuit 111.
(C) A relatively long time is required in the method for obtaining a coefficient for minimizing the integral nonlinearity error (INL) and the differential nonlinearity error (DNL) of the A / D conversion circuit 111 for each column, and the correction takes time. It takes. That is, a method for easily obtaining the error E _FR is given as an issue (see FIG. 21).

(2) Method M2: A method of correcting all of the errors E _FR , E _FI , E _G1 , E _M1 among the right side of Expression (18), and has the following characteristics.
(A) Ideal correction can be made so that the integral nonlinearity error (INL) and the differential nonlinearity error (DNL) are 0.25 LSB or less by a 14-bit A / D converter.
(B) An additional circuit in the column circuit 150 of FIG. 22 described later is required, and the digital correction circuit 112 becomes complicated.
(C) The number of horizontal signal lines and circuits for reading correction signals from the A / D conversion circuit 111 increases. For example, it increases from 14b bits to 32 bits.
(D) The measurement method such as the correction coefficient m ₁ is complicated and takes time to measure.

In the method M2, the errors E _FR , E _FI , E _G1 , E _M1 are corrected in the right side of the equation (18). However, the present invention is not limited to this, and the errors E _FI , E _G1 , It may be configured to correct only E _M1 .

Next, a method for measuring the error _efg using a folded integration circuit using the operational amplifier circuit 23 actually used in the A / D conversion circuit 111 will be described below.
(1) First, an input voltage V _in = V _RL is given and M times of folding integration is performed.
(2) Next, the input voltage V _in = V _RH is given, and the M folding integration operation is performed.
(3) By calculating the difference between the output voltage of the folding integration operation of (1) and the output voltage of the folding integration operation of (2), the error _EFI can be calculated by the following equation.
E _FI = −2 {(M−2) (M−1) / 2} e _fg1 = − (M−2) (M−1) e _fg1

The error _efgl can be measured using the following equation.
e _fg = (C _1a + C _1b + C ₂ + C _i ) / (C ₂ A) ≈ (2+ (C _i / C ₂ )) / A
e _fg1 = (C _1a + C _1b ) / (C ₂ A) ≈1 / A
e _fg2 = (C ₂ + C _i ) / (C ₂ A) ≈ (1+ (C _i / C ₂ )) / A

Here, as C _i / C ₂ , a value obtained by the circuit design of the A / D conversion circuit 111 may be used, or may be ignored as C _i / C ₂ << 1.

FIG. 20 is a circuit diagram showing a circuit for measuring error parameters e _m1 and e _m2 for the digital correction circuit 12 of FIG.

First, only the cyclic A / D converter circuit is operated, and the inverting input terminal and the output terminal of the operational amplifier circuit 23 are connected to reset (FIG. 20A).
(1) Then, the reference voltage applied to the capacitor _{C 1b} is changed from _{V RH} to _{V RL,} the reference voltage applied to the capacitor _{C 1a} and _{V RH} from _{V RH} (FIG. 20 (b1)). The output voltage at this time is Vo ⁽¹⁾ .
(2) Further, the reference voltage applied to the capacitor C _1b is changed from V _RH to V _RH, and the reference voltage applied to the capacitor C _1a is changed from V _RH to V _RL (FIG. 20 (b2)). The output voltage at this time is Vo ⁽²⁾ .
(3) Then, the reference voltage applied to the capacitor _{C 1b} and _{V RH} from _{V RH,} and _{V RH} reference voltage applied to the capacitor _{C 1a} from _{V RH} (FIG. 20 (b3)). The output voltage at this time is Vo ⁽³⁾ .

The output voltages Vo ⁽¹⁾ , Vo ⁽²⁾ , and Vo ⁽³⁾ are expressed by the following equations.
V _o ⁽¹⁾ = (1 / (1 + e _fg )) {V _RL + (1 + _{em 2} −em ₁ ) ΔV _R + e _fg V _c }
V _o ⁽²⁾ = (1 / (1 + e _fg )) {V _RL + (1 + e _m2 + e _m1 ) ΔV _R + e _fg V _c }
V _o ⁽³⁾ = (1 / (1 + e _fg )) (V _RL + e _fg V _c )
Therefore, the following equation is obtained using the above equation.
V _o ⁽²⁾ −V _o ⁽¹⁾ = {(2 e _m1 ) / (1 + e _fg )} ΔV _R ≈2 e _m1 ΔV _R
V _o ⁽²⁾ -V _o ⁽¹⁾ -2V _o ⁽³⁾
= 2 {(1 + e _m1 ) / (1 + e _fg )} ΔV _{R
≒ 2 (1 + e m1 -e} fg) ΔV R

Next, a method for measuring the correction value of the error _EFR will be described below. Here, a cyclic A / D conversion circuit using an operational amplifier circuit 23 is used.
(1) First, the inverting input terminal and the output terminal of the operational amplifier circuit 23 are connected and reset (FIG. 20A).
(2) Next, the input voltage V _in = V _RL is given to perform integration once, and cyclic A / D conversion is performed, for example, 10 times based on the output voltage (D (1 ) = 0.) (FIG. 20B). The A / D conversion value at this time is referred to as a first A / D conversion value.
(3) Further, the input voltage V _in = V _RH is given and integration is performed once, and cyclic A / D conversion is performed, for example, 10 times based on the output voltage (FIG. 20 (c)). ). However, in the first cycle, the output voltage of the A / D conversion circuit is set to _VRH (D (1) = 2 is set). The A / D conversion value at this time is referred to as a second A / D conversion value.
(4) The first A / D conversion value is subtracted from the second A / D conversion value, and the subtraction result value is converted at the input terminal of the cyclic A / D conversion circuit,
_{(E fg, FI -e m,} FI + g 2 -0.5g 1) ΔV R
The value of is directly obtained.

Here, when only the error E _FR is corrected, it is not a good idea to measure each component of the following equation and determine a correction value in view of the measurement time and the like.
E _FR ≈− (e _{fg, FI} −em _{, FI} + g ₂ −0.5 g ₁ ) M ₁ (19)
Moreover, there is a concern about the difference between the optimum correction value and the measured correction value.

Therefore, although it takes time to measure, as a method of simply and reliably measuring the optimum correction value, based on the calculated value of the integral nonlinear error (INL) related to the error E _FR for a plurality of A / D conversion operations, An optimal error E _FR * may be calculated using a cost function of the following equation.

FIG. 21 is a graph of a cost function showing a method using a cost function which is one method for measuring the parameter E _FR for the digital correction circuit 12 of FIG. Thereby, at least the calculation cost can be greatly reduced as compared with the measurement and calculation of each component of the formula (19).

Further, a method for measuring an error _EFI that is an integration error in the folding integration will be described below.

FIG. 22 is a circuit diagram showing a circuit of the column circuit 150 in the A / D conversion circuit 111 of the integration / cyclic ADC array 4 for measuring the error _EFI for the digital correction circuit 12 of FIG. The error _EFI is calculated in the column circuit 150 using the following equation.

を計算することができる。 In the above equation (20), the error parameter e _fg1 is measured by the above-described method, but the correction coefficient m ₁ needs to be calculated for each pixel signal by the column circuit 150 in FIG. The measurement circuit is provided in common to all the columns, and in addition to an m-bit up counter 60 that counts the number of integrations i indicating the number of integrations, an AND gate 151, an adder 152, And a register 153. In FIG. 22, output signals (indicating whether or not folding is performed) from the comparators 17 a and 17 b are input to one input terminal of the AND gate 151, and a clock is input to the other input terminal. An output signal from the AND gate 151 is input as a clock of the register 153. Code data indicating the number of integrations i from the up counter 60 is input to the adder 152, and the data signal from the adder 152 is temporarily stored in the register 153 and then fed back to the adder 152 to obtain the number of cycles i. Is added. In the column circuit 150 configured as described above, the A / D conversion value D _I (i) (takes 0 or 1) of the pixel value is multiplied by the number of times i, and every cyclic A / D conversion. By adding, the rightmost correction coefficient of equation (20)

Can be calculated.

  Furthermore, the correction effect by simulation using MATLAB is described below.

23 to 28 are graphs showing the results of the MATLAB simulation of the A / D conversion circuit using the digital correction circuit 12 of FIG. Table 1 shows specification values in the simulation.

Table 2 shows various error parameters P1 in the method M1 in which correction is performed using only the error _EFR .

Next, Table 3 shows various error parameters P2 in the method M2 for correcting all the errors E _FR , E _FI , E _G1 , and E _M1 .

Here, FIGS. 23 to 28 are as follows.
FIG. 23 is a MATLAB simulation result of the A / D conversion circuit using the digital correction circuit 12 of FIG. 17, and shows an integral nonlinearity error (INL) and a differential for the digital code when the error parameter P1 is used without correction. It is a graph which shows a non-linearity error (DNL).
FIG. 24 is a MATLAB simulation result of the A / D conversion circuit using the digital correction circuit 12 of FIG. 17, and the integral nonlinearity error (INL) and the differential for the digital code when the error parameter P1 is used in the method M1. It is a graph which shows a non-linearity error (DNL).
FIG. 25 is a MATLAB simulation result of the A / D conversion circuit using the digital correction circuit 12 of FIG. 17, and the integral nonlinearity error (INL) and the differential with respect to the digital code when the error parameter P1 is used in the method M2. It is a graph which shows a non-linearity error (DNL).
FIG. 26 is a MATLAB simulation result of the A / D conversion circuit using the digital correction circuit 12 of FIG. 17, and shows an integral nonlinearity error (INL) and a differential for the digital code when the error parameter P2 is used without correction. It is a graph which shows a non-linearity error (DNL).
FIG. 27 is a MATLAB simulation result of the A / D conversion circuit using the digital correction circuit 12 of FIG. 17, and shows the integral nonlinearity error (INL) and the differential for the digital code when the error parameter P2 is used in the method M1. It is a graph which shows a non-linearity error (DNL).
FIG. 28 is a MATLAB simulation result of the A / D conversion circuit using the digital correction circuit 12 of FIG. 17, and shows the integral nonlinearity error (INL) and differentiation for the digital code when the error parameter P2 is used in the method M2. It is a graph which shows a non-linearity error (DNL).

  As is clear from the simulation results of FIGS. 23 to 28 described above, the integral nonlinearity error (INL) and the differential nonlinearity error (DNL) are minimized when all errors are corrected as in the method M2. However, it can be understood that the integral nonlinearity error (INL) and the differential nonlinearity error (DNL) can also be reduced by the method M1 as compared to the case of no correction.

As described above, according to the present embodiment, the following specific effects are obtained.
(1) By correcting a mismatch of a plurality of capacitors such as an input section of an operational amplifier circuit, a highly accurate A / D converter circuit can be configured even with a small capacitor, so that the area of the column circuit can be reduced and the power consumption can be reduced. I can plan.
(2) Since the finite gain error and settling error of the operational amplifier circuit can be corrected, the A / D converter circuit can be increased in speed and power consumption.
(3) Non-linearity due to mismatch of circuit parameters of the first and second stages in the two-stage cyclic A / D converter circuit can be improved by digital correction.

Derivation of each expression of the second embodiment.
Derivation of each expression used in the second embodiment will be described below.

The operation of each phase of the folded integration type A / D conversion circuit of FIG. 2 operates as follows in an ideal calculation including no error.
1st time (# 1): V _o (1) = 0.5 (V _in (1) −V _RL ) + V _RL
Second time (# 2): V _o (2) = 0.5 (V _in (2) −V _RL ) + V _o (1)
3rd time (# 3): V _o (3) = 0.5 (V _in (3) −V _RI (3)) + V _o (2)
Mth (#M): V _o (M) = 0.5 (V _in (M) −V _RI (M)) + V _o (M−1)

The output voltage V _o (M) of the folding integration type A / D conversion circuit at the number of integrations M is expressed by the following equation.

V _o (M) = 0.5 {MV _in − (M−M ₁ ) V _RL −M ₁ V _RH } + V _RL

Here, the input DC voltage _{V in (i), (i} = 1, ..., M) = a _{V in} (fixed value), by folding number _{M 1} once in the folded integral type A / D converter function of the following formula value _{D I} take the 1.

D _I (i)
= 0 (when V _o (i) ≦ V _T )
= 1 (when V _o (i)> V _T )
V _RI (i)
= _V RL _(D I _(when i-1) = 0)
= V _RH (when D _I (i-1) = 1)

Therefore, the output voltage V _o (M) is expressed by the following equation.
V _o (M) = 0.5 {MV _in − (M−M ₁ ) V _RL −M ₁ V _RH } + V _RL
V _o (M) −V _RL = 0.5M (V _in −V _RL ) −0.5M ₁ (V _RH −V _RL )

here,
ΔV _R = (V _RH −V _RL ) / 2
X = 0.5 (V _in −V _RL ) / ΔV _R
Y = (V _oF (M) −V _RL ) / ΔV _R
Then, the following equation is obtained.

Y = MX-M ₁
MX = Y + M ₁

Here, with respect to V _in = V _{RL to} V _RH , V _oF (M) = V _{RL to} V _RH , a range of X = 0 to 1 and Y = 0 to 2 is taken. Further, for M ₁ = 0 to M−2, Y + M ₁ = 0 to M, MX = 0 to M, and the parameters Y + M ₁ and MX match each other.

  Next, error correction in the operation of each phase of the folding integration will be described below.

The following operation is performed in the first integration operation.
(1) Phase 1a (at the time of resetting in FIG. 12 (a), the capacitance _{C 1a,} before the application of the voltage _{V RL} with capacitive _{C 1} consisting of _{C 1b)}
The charge Qnet at the inverting input terminal of the operational amplifier circuit 23 is expressed by the following equation.
Q _net = C ₁ (V _c −V _in (1)) + C ₂ (V _s0 −V _RL ) + C _i V _s0
The output voltage _VoF of the operational amplifier circuit 23 at this time is expressed by the following equation.
V _oF = A (V _c −V _s0 ) + V _c
here,
V _s0 = V _c
It becomes.

(2) Phase 1b (at the time of the integration operation of Fig. 12 (b), upon application of a voltage _{V RL} with capacitive _{C 1} consisting of capacitor _{C 1a, C 1b)}
The charge Qnet at the inverting input terminal of the operational amplifier circuit 23 is expressed by the following equation.
Q _net = C ₁ (V _s −V _RL ) + C ₂ (V _s −V _oF (1)) + C _i V _s
The output voltage _VoF of the operational amplifier circuit 23 at this time is expressed by the following equation.
V _oF (1) = A (V _c −V _s ) + V _c
Therefore, the following equation is obtained.
C ₂ (1 + e _fg ) V _oF (1)
= C ₁ (V _in (1) −V _RL ) + C ₂ V _RL + C ₂ e _fg V _c
(1 + e _fg ) V _oF (1)
_{= 0.5 (1 + e m)} (V in (1) -V RL) + V RL + e fg V c
here,
e _fg = (C ₁ + C ₂ + C _i ) / (C ₂ A)
e _m = ΔC ₂ / C ₂
C ₁ = 0.5 (C ₂ + ΔC ₂ )
It is.

Next, the following operation is performed in the second integration operation.
(3) Phase 2a (during reset of FIG. 12 (a), the capacitance _{C 1a,} before the application of the voltage _{V RL} with capacitive _{C 1} consisting of _{C 1b)}
The charge Qnet at the inverting input terminal of the operational amplifier circuit 23 is expressed by the following equation.
Q _net = C ₁ (V _c −V _in (2)) + C ₂ (V _s0 −V _oF (1)) + C _i V _s0
The output voltage _VoF of the operational amplifier circuit 23 at this time is expressed by the following equation.
V _oF (1) = A (V _c −V _s0 ) + V _c

(4) Phase 2b (at the time of the integration operation of Fig. 12 (b), upon application of a voltage _{V RL} with capacitive _{C 1} consisting of capacitor _{C 1a, C 1b)}
The charge Qnet at the inverting input terminal of the operational amplifier circuit 23 is expressed by the following equation.
Q _net = C ₁ (V _s −V _RL ) + C ₂ (V _s −V _oF (2)) + C _i V _s
The output voltage _VoF of the operational amplifier circuit 23 at this time is expressed by the following equation.
V _oF (2) = A (V _c −V _s ) + V _c
Therefore, the following equation is obtained.
C ₂ (1 + e _fg ) V _oF (2)
= C ₁ (V _in (1) −V _RL ) + (1 + e _fg2 ) C ₂ V _oF (1) + C ₂ e _fg1 V _c
(1 + e _fg ) V _oF (2)
_{= 0.5 (1 + e m)} (V in (2) -V RL) + (1 + e fg2) V oF (1) + e fg1 V c
here,
e _fg2 = (C ₂ + C _i ) / (C ₂ A)
e _fg1 = C ₁ / (C ₂ A) = e _fg −e _fg2
It is.

Next, the following operation is performed in the third integration operation.
(5) In the phases 3a and 3b (after the reset of FIG. 12A, the voltage V _RL was applied to the capacitor C ₁ composed of the capacitors C _1a and C _1b in the integration operation of FIG. 12B. When)
The third integration operation is expressed by the following equation.
D _I (3)
= 0 (when V _oF (2) ≦ (V _RH + V _RL ) / 2)
= 1 (when V _oF (2)> (V _RH + V _RL ) / 2)
(1 + e _fg ) V _oF (3)
_{= 0.5 (1 + e m)} (V in (3) -V R (3))
+ (1 + e _fg2 ) V _oF (2) + e _fg1 V _c
V _R (3)
= V _RH (when D _I (3) = 1)
= V _RL (when D _I (3) = 0)

Further, the M-th integration operation operates as follows.
(6) In the phases Ma and Mb (after the reset of FIG. 12A, the voltage V _RL was applied to the capacitor C ₁ composed of the capacitors C _1a and C _1b during the integration operation of FIG. 12B. When)
The Mth integration operation is expressed by the following equation.
(1 + e _fg ) V _oF (M)
_{= 0.5 (1 + e m)} (V in (M-1) -V R (M-1))
+ (1 + e _fg2 ) V _oF (M−1) + e _fg1 V _c

The output voltage _VoF of the operational amplifier circuit 23 at this time is expressed by the following equation.
V _oF (M)
_{= 0.5 {(1 + e m} ) / (1 + e fg)} (V in (M) -V R (M))
+ {(1 + e _fg2 ) / (1 + e _fg )} V _oF (M−1)
+ {E _fg1 / (1 + e _fg )} Vc
_{≒ 0.5 (1 + e m -e} fg) (V in (M) -V R (M))
+ (1−e _fg1 ) V _o (M−1) + e _fg1 V _c
Therefore, the following equation is obtained.
V _oF (M)
_{≒ 0.5 (1 + e m -e} fg) × {(1-e fg1) 0 (V in (M) -V R (M))
+ (1-e _fg1 ) ¹ (V _in (M−1) −V _R (M−1))
...
+ (1-e _fg1 ) ^M-2 (V _in (2) -V _RL )
+ (1-e _fg1 ) ^M-1 (V _in (1) −V _RL )}
+ Me _fg1 V _c + (1-e _fg ) (1-e _fg1 ) ^M−1 V _RL

V _oF (M)
_{= 0.5 (1 + e m -e} fg) {M (1 - ((M-1) / 2) e fg1) V in
−M ₁ V _RH − (M−M ₁ ) V _RL + _efg1 (m ₁ V _RH + (m _M −m ₁ ) V _RL )}
+ Me _fg1 V _c + (1-Me _fg1 −e _fg2 ) V _RL
Here, it is as follows.
m _M = M (M−1) / 2
V _c = V _RL

D _I (i)
= 0 (when V _oF (i) ≦ V _T )
= 1 (when V _oF (i)> V _T )

Therefore, the following equation is obtained.
V _oF (M) -V _{RL
= 0.5 (1 + e m -e} fg) {M (1 - ((M-1) / 2) e fg1) V in
_{-MV RL -M 1 (V RH -V} RL) + e fg1 m M V RL -m 1 (V RH -V RL)}
_{-E fg2} V _RL
V _oF (M) -V _{RL
= 0.5 (1 + e m -e} fg) {M (1 - ((M-1) / 2) e fg1) (V in -V RL)
−2 (M ₁ −m ₁ e _fg1 ) ΔV _R } −e _fg2 V _RL

The above formulas are summarized as follows:
X = (V _in −V _RL ) / (2ΔV _R )
Y = (V _o (M) −V _RL ) / ΔV _R
E _F = ((M−1) / 2) e _{fg1
M (1-E F) X} = M 1 -m 1 e fg1 + (1 + e fg -e m) (Y-e fg2 V RL)

Next, the nonlinear correction term m ₁ e _fg1 of the folded integration A / D conversion circuit will be described below. The following equation is obtained from the equation of the Mth integration operation.
2 (1-e _m + e _fg ) V _o (M) =
(1-e _fg1 ) ⁰ (V _in (M) −V _R (M))
+ (1-e _fg1 ) ¹ (V _in (M−1) −V _R (M−1))
...
+ (1-e _fg1 ) ^M-3 (V _in (3) -V _R (3))
+ (1-e _fg1 ) ^M-2 (V _in (2) -V _RL )
+ (1-e _fg1 ) ^M-1 (V _in (1) −V _RL ) + V _RL )

Here, focusing on the fact that an error of i × e _fg1 is added when the voltage V _R (i) takes the voltage V _RH , the sum of the errors is m ₁ × e _fg1 as shown in the following equation.

here,
D _I (i)
= 0 (when V _o (i) ≦ V _T )
= 1 (when V _o (i)> V _T )

At this time, the parameter m ₁ takes (M−2) (M−1) / 2 at the maximum. Therefore, when M = 8, m ₁ is 21, and a storage capacity of 5 bits is required to store the parameter m ₁ .

  Next, the operation and error correction of the cyclic A / D conversion circuit will be described below.

In the first cyclic A / D conversion circuit, the output voltage V _o (1) is expressed by the following equation.

V _o (1)
_{≒ (2 + e m2 + e} fg2 -e fg) V oF (M) - (1 + e m2 -e fg) V RH
(D (1) = 2)
V _o (1)
_{≒ (2 + e m2 + e} fg2 -e fg) V oF (M)
− (1 + _{em 2} −ef _g ) (V _RH + V _RL ) / 2 + ( _em 1/2) (V _RH −V _RL )
(D (1) = 1)
V _o (1)
_{≒ (2 + e m2 + e} fg2 -e fg) V oF (M) - (1 + e m2 -e fg) V RL
(D (1) = 0)

here,
_{g 1 = e m2 + e fg2} -e fg
g ₂ = _e m2 _{-e fg}
far.

In the i-th cyclic A / D conversion circuit, the output voltage V _o (1) is expressed by the following equation.

V _o (i)
≈ (2 + g ₁ ) V _o (i−1) − (1 + g ₂ ) ΔV _R D (i)
+ E _m1 ΔV _R D ₁ (i) − (1 + g ₂ ) V _RL

here,
D ₁ (i)
= 1 (when D (i) = 1)
= 0 (when D (i) = 0, 2)
It is.

Therefore, the following equation is obtained.
_{Y≈Y 0} + E _g2 + E _g1 + E _m1
Y ₀ = 2 ⁻¹ D (1) +2 ⁻² D (2) +... +2 ^{− (N−1)} D (N−1) +2 ^−ND (N)
here,
E _g2
= G ₂ {2 ⁻¹ D (1) +2 ⁻² D (2) +... +2 ^{− (N−1)} D (N−1) +2 ^−ND (N)}
= G ₂ Y ₀
E _g1
= −g ₁ {1 · 2 ⁻¹ D (1) + 2 · 2 ⁻² D (2) +.
+ (I-1) .multidot.2- ^(i-1) D (i-1) + i.2.sup.- ⁱ D (i)}
E _m1
= −e _m1 {2 ⁻¹ D ₁ (1) +2 ⁻² D ₁ (2) +.
+2 ^{− (i−1)} D ₁ (i−1) +2 ⁻ⁱ D ₁ (i)}
It is.

The above-described folded integration type A / D conversion circuit is summarized as follows. The following operation is performed during the Mth sampling operation.
M {1-((M−1) / 2) e _fg1 } (V _in −V _RL )
_{= 2M 1 ΔV R +2 (1} + e fg -e m) (V oF (M) -V RL)
− ( _{M 1} V _RH + (m _M −m ₁ ) V _RL ) _efg1

here,
e _fg = (C _1a + C _1b + C ₂ + C _i ) / (C ₂ A)
e _m2 = ΔC ₂ / C ₂
e _m1 = ΔC ₁ / C ₁
It is. Therefore, the following equation is obtained.
X = (V _in −V _RL ) / ΔV _R
Y = (V _oF (M) −V _RL ) / ΔV _R
E _F = ((M−1) / 2) e _fg1
R _L = V _RL / ΔV _R
That is, it is expressed by the following formula.
M (1-E _F ) X
_{= 2M 1 +2 (1 + e} fg -e m) Y-m M e fg1 R L -2m 1 e fg1

  Further, the cyclic A / D conversion circuit described above is summarized as follows.

At the time of sampling in phase 1a, the charge Q _net and the output voltage V _{oF at} the inverting input terminal of the operational amplifier circuit 23 are expressed by the following equations.
Q _{net
= (C 1b + C 1a)} (V c -V oF (M)) + C 2 (V s0 -V oF (M)) + C i V s0
V _oF (M) = A (V _c −V _s0 ) + V _c
Here, V _s0 = V _c .

Further, at the time of the transfer in the phase 1b, the charge Q _net and the first output voltage V _o (1) at the inverting input terminal of the operational amplifier circuit 23 are expressed by the following equations.
Q _net
= C _1a (V _s −V _Ra (1)) + C _1b (V _s −V _Rb (1))
+ C ₂ (V _s −V _o (1)) + C _i V _s
V _o (1) = A (V _c −V _s ) + V _c

Therefore, the following equation is obtained.
(1 + e _fg ) V _o (1)
= (2 + e _m2 + e _fg2 ) V _oF (M)
− {(1 + _em 2 + em ₁ ) / 2} V _Ra (1)
_{- {(1 + e m2 -e} m1) / 2} V Rb (1) + e fg1 V c

Therefore, it is expressed by the following formula.
V _o (1)
_{≒ (2 + e m2 + e} fg2 -e fg) V oF (M) - (1 + e m2 -e fg) V RH
(When D (1) = 2)
V _o (1)
_{≒ (2 + e m2 + e} fg2 -e fg) V oF (M)
− (1 + _{em 2} −ef _g ) (V _RH + V _RL ) / 2 + ( _em 1/2) (V _RH −V _RL )
(When D (1) = 1)
V _o (1)
_{≒ (2 + e m2 + e} fg2 -e fg) V oF (M) - (1 + e m2 -e fg) V RL
(When D (1) = 0)

here,
_{g 1 = e m2 + e fg2} -e fg
g ₂ = _e m2 _{-e fg}
D ₁ (i)
= 1 (when D (i) = 1)
= 0 (when D (i) = 0, 2)
far. Output voltages Vo (1) to Vo (i) of the cyclic A / D conversion circuit are expressed by the following equations.

V _o (1)
≈ (2 + g ₁ ) V _oF (M) − (1 + g ₂ ) ΔV _R D (1)
+ E _m1 ΔV _R D ₁ (1) − (1 + g ₂ ) V _RL
V _o (2)
≈ (2 + g ₁ ) V _o (1) − (1 + g ₂ ) ΔV _R D (2)
+ E _m1 ΔV _R D ₁ (2) − (1 + g ₂ ) V _RL
...
V _o (i)
≈ (2 + g ₁ ) V _o (i−1) − (1 + g ₂ ) ΔV _R D (i)
+ E _m1 ΔV _R D ₁ (i) − (1 + g ₂ ) V _RL

Therefore, the following equation is obtained. Here, _Nc is the number of cycles of cyclic A / D conversion.

  The above second embodiment is summarized as follows.

The digital correction circuit for an A / D conversion circuit according to the second embodiment of the present invention is an integration / cyclic type A that sequentially performs a folded integration type A / D conversion and a cyclic type A / D conversion using an operational amplifier circuit. In the / D conversion circuit, the A / D is obtained by subtracting the digital value of the nonlinear error caused by the gain error of the folding integration having the predetermined number of integrations (M) and the predetermined number of foldings (M ₁ ) from the A / D conversion value. A digital correction circuit for correcting a conversion value,
A digital value of a first error (E _FR ) that is a non-linear error caused by a gain error of the folding integration and is substantially proportional to the number of foldings (M ₁ ) is calculated, and the digital value is calculated from the A / D conversion value. A comprising a correcting means for correcting the A / D conversion value by subtracting the first error (E _FR ).

In the digital correction circuit, the correction means _supplies the first reference voltage (V _RL ) as the input voltage (V _in ) to the operational amplifier circuit to perform one integration, and then the operational amplifier circuit at that time A first A / D conversion value obtained by performing cyclic A / D conversion on the output voltage of the second output voltage and a second higher than the first reference voltage (V _RL ) as the input voltage (V _in ). The second reference voltage (V _RH ) is applied to the operational amplifier circuit and integrated once, and then the output voltage of the operational amplifier circuit at that time is subjected to cyclic A / D conversion for a predetermined number of cycles. The first A / D conversion value is subtracted from the second A / D conversion value, and the subtraction value is input to the cyclic A / D conversion side. by converting, calculating the digital value of the first error (E _FR) And features.

Further, in the digital correction circuit, the correction means is based on a calculation value of an integral nonlinear error (INL) related to the first error (E _FR ) with respect to a plurality of A / D conversion operations. Calculating a digital value of the first error (E _FR ) when the cost function obtained by adding the square value of the error (INL) to a plurality of A / D conversion operations is minimized. To do.

Further, in the digital correction circuit, the correction means further calculates a digital value of a second error (E _FI ) that is a non-linear error caused by the gain error of the folding integration and is an integration error of the folding integration. The first error (E _FR ) and the second error (E _FI ) are subtracted from the A / D conversion value.

Still further, in the digital correction circuit, the correction means includes code data indicating the number of integrations (i) indicating the number of integrations of the folding integration, and data indicating the presence / absence of folding of the folding integration ( The digital value of the second error (E _FI ) is calculated based on D _I (i)).

In the digital correction circuit, the correction means includes a circuit for calculating a digital value of the second error (E _FI ) in the column circuit, and the calculation circuit includes:
An up-counter that counts the number of integrations (i) indicating the number of integrations;
A register that operates using data indicating the presence or absence of the folding integration as a clock; and
The number of integrations (i) from the up-counter and the data from the register are added to calculate the digital value of the second error (E _FI ) through the register with the added value data And an adder that outputs the correction coefficient (m ₁ ).

In the digital correction circuit, the correction means is connected between a capacitor (C ₁ ) connected to the input terminal of the operational amplifier circuit and the input terminal and the output terminal in cyclic A / D conversion. A third error (E _g1 ) corresponding to an error due to a capacitor mismatch with the integral capacitance (C ₂ ) is further calculated, and the first error (E _FR ) and the first error are calculated from the A / D conversion value. 2 error (E _FI ) and the third error (E _g1 ) are subtracted.

Further, in the digital correction circuit, the correction means copes with an error due to a mismatch of capacitors between two capacitors (C _1a , C1 _b ) connected to the input terminal of the operational amplifier circuit in the cyclic A / D conversion. The fourth error (E _m1 ) is further calculated, and the third error (E _FI ) is added to the first error (E _FR ) and the second error (E _FI ) from the A / D conversion value. E _g1 ) and at least one of the fourth error (E _m1 ) is subtracted.

  An A / D conversion circuit according to the present invention is an integration / cyclic A / D conversion circuit that sequentially performs folded integration A / D conversion and cyclic A / D conversion using an operational amplifier circuit. A correction circuit is provided.

Furthermore, the image sensor device according to the present invention is an image sensor device that reads an image.
An A / D conversion circuit for A / D converting the pixel value signal obtained by reading the image;
The A / D conversion circuit is an integration / cyclic A / D conversion circuit that sequentially performs folded integration type A / D conversion and cyclic type A / D conversion using an operational amplifier circuit, and the digital correction circuit is It is characterized by having.

Third Embodiment FIG. 29 is a block diagram showing an overall configuration of an A / D converter according to a third embodiment of the present invention. In the first embodiment shown in FIG. 1, the circuit for folding integration type A / D conversion and the circuit for cyclic A / D conversion are configured using the same circuit, but the third embodiment shown in FIG. As shown in FIG. 29, the folded integration type A / D conversion circuit 201 and the cyclic type A / D conversion circuit 202 are configured using different circuits. Thereby, by operating different circuits separately and simultaneously, there is a specific effect that the operation time can be shortened as compared with the first embodiment.

Here, the analog signal _VIN , which is a pixel output, is input to the folding integration type A / D conversion circuit 201, and the folding integration type A / D conversion circuit 201 outputs a higher A / D conversion value. The / D conversion circuit 202 outputs a lower A / D conversion value.

FIG. 30 is a circuit diagram showing the configuration of the folded integration A / D conversion circuit 201 and its peripheral circuits in FIG. In FIG. 30, the folding integration type A / D conversion circuit 201 includes an operational amplifier circuit 23C, capacitors 25C and 29C, switches 49C, 47C, 53, 54 and 55, an input analog signal switch 43C, and D / A conversion switches 31a and 31b, a reference voltage generation circuit 37C of FIG. 31, a comparator 17c, a logic circuit 19C, and a clock generator 41C. Here, “C” is added to the end of the reference numbers for the same components as in FIG. The folded integration type A / D converter circuit 201 of FIG. 30 is mainly different from the A / D converter of FIG. 1 in the following points.
(1) Instead of the capacitors 25 and 27, only the capacitor 25C is provided to perform the folding integration type A / D conversion operation, and the capacitor 27 and the switch 31c are not required here.
(2) In place of the comparators 17a and 17b, a comparator 17c for outputting a higher A / D conversion value is provided.
(3) Instead of the logic circuit 19, a logic circuit 19C that generates control signals φ _DH and φ _DL only for the operation of the folding integration type A / D conversion is provided.
(4) Instead of the clock generator 41, a clock generator 41C that generates clock signals φ2, φ3, φsd, and φs only for the operation of the folding integration type A / D conversion is provided.

Digital section DC _C illustrated in the lower side of FIG. 30 to generate a digital signal D of the upper A / D conversion value using a comparator 17c and two conversion reference voltage _{V RCH,} the _{V RCL.} The digital part DC _C includes a complement part CP _C , an adder AD _C , and a register RG _1C . Operation of the digital section DC _C, except that it produces a digital signal D of the upper A / D conversion value based on the 1-bit output B _0, is similar to the operation of the above-described FIG. 14 (a) .

FIG. 31 is a circuit diagram showing a configuration of reference voltage generating circuit 37C of FIG. In FIG. 31, the reference voltage generation circuit 37C is a folded integration type A / D according to the resistors R _{1 to} R ₅ having predetermined resistance values based on the first and second reference reference voltages V _RH and V _RL. generating conversion reference voltage V _T for the conversion operation. According to this reference voltage generating circuit 37, for example, the resistance value of the resistor _R 1 to R _5, resistors _R 1 = 2R, the resistance _R 2 = R, the resistance _R 4 = R, resistor _R 5 = 2R _(R is given The conversion reference voltage V _T can be set to a median value between the first standard reference voltage V _RH and the second standard reference voltage value V _RL .

FIG. 32 is a diagram showing the operation of the folding integration type A / D conversion circuit 201 of FIG. The operation of the folding integration type A / D conversion circuit 201 of FIG. 32 is different from that of the A / D converter according to the first embodiment of FIG.
(1) In order to perform the folding integration type A / D conversion operation using only the capacitor 25C having the capacitance C _F1a instead of the capacitors 25 and 27 having the capacitances C _1a and C _1b , respectively, Operate.
C _FI = C _F1a

Therefore, the finite gain error at the time of digital correction is expressed by the following equation.
e _{fg, FI} = (C _F1a + C _FI2 + C _FIi ) / (C _FI2 A _FI )
_{e fg2, FI = (C FI2} + C FIi) / (C FI2 A FI)
e _{fg1, FI} = C _F1a / (C _FI2 A _FI ) = e _{fg, FI} −e _{fg2, FI}
Here, A _FI is an open-loop DC gain of the operational amplifier circuit 23, C _FI2 is a feedback side capacitance, and C _FI1 is an input side capacitance (ideal value C _FI1 = C _FI2 / 2). C _FIi is an input capacitance of the operational amplifier circuit 23.

The finite gain error at the time of digital correction of the cyclic A / D conversion circuit 202 is slightly different from that of the second embodiment. That is, in the first cycle of the operation of the cyclic A / D conversion circuit 202, the error term g2 is expressed by the following equation.
g ₁ = _{em 2} −e _fg
In the second and subsequent cycles, the error term g2 is expressed by the following equation, as in the second embodiment.
_{g 1 = e m2 + e fg2} -e fg

FIG. 33 is a diagram showing the input / output characteristics of the gain stage by simulation in the operation of the folding integration type A / D conversion circuit 201 shown in FIG. FIG. 33 shows the input / output characteristics under the conditions of (V _RH = 2.5 V, V _RL = 1.5 V, reference voltage V _RI = V _RH , V _COM = 2.0 V, sampling number M = 16 in the operation operation). Show. As shown in FIG. 33, the output is 1.5 to 2.5V with respect to the input of 1.0V to 1.0V and the amplitude is within the range of 1V. .

FIG. 34 is a diagram showing the relationship between the input level of the analog signal _VIN , which is an input signal, and the digital count value, corresponding to the simulation of the folded integration type A / D conversion circuit 201 shown in FIG. As shown in FIG. 34, the digital count value can take a value of 15 gradations for 16 samplings and integrations in the folded integration type A / D conversion circuit 201 and an input range of 1.0V. Therefore, the range of this digital count value is represented by about 4 bits.

  FIG. 35 is a circuit diagram showing the configuration of the cyclic A / D conversion circuit 202 and its peripheral circuits in FIG. In FIG. 35, the cyclic A / D converter circuit 202 is configured in the same manner except for the folding integration A / D conversion operation using the A / D converter of FIG.

  According to the A / D converter according to the third embodiment configured as described above, different circuits are used for the folded integration type A / D conversion circuit 201 and the cyclic A / D conversion circuit 202. It is characterized by being configured. Thereby, by operating different circuits separately and simultaneously, there is a specific effect that the operation time can be shortened as compared with the first embodiment. Further, in the A / D converter according to the third embodiment, the above equation in the folded integration type A / D converter circuit 201 is replaced, so that the digital correction circuit according to the second embodiment is used similarly. Can be digitally corrected.

Other embodiments.
The present invention has been described in detail based on the embodiments. However, the present invention is not limited to the above embodiment. The present invention can be variously modified without departing from the gist thereof.

  As described above in detail, according to the digital correction circuit of the present invention, the A / D converter can be improved in accuracy, that is, increased in resolution by the digital correction. A / D conversion can be realized, and the speed can be increased with low power consumption. Further, an A / D converter can be configured using the digital correction circuit, and an image sensor device such as a CMOS image sensor can be provided using the A / D converter.

B ₁ , B ₀ ... digital signal,
C _1a , C _1b , C ₂ ... capacity,
D: Digital signal,
SA ... switch,
SI ... switch,
V _COM ... reference potential,
V _CONT ... control signal,
V _IN ... analog signal,
V _OP ... computed value,
V _RCH ... first conversion reference voltage,
V _RCL ... second conversion reference voltage,
V _RH ... first reference voltage,
V _RL ... second reference voltage,
31a-31c ... switch,
2a: Image sensor cell,
11 ... D / A converter,
15 ... gain stage,
15a ... input,
15b ... output,
17, 17C ... A / D conversion circuit,
17a, 17b, 17c ... comparators
19, 19C ... logic circuit,
21 ... D / A conversion circuit,
21a ... first output,
21b ... second output,
23, 23C ... operational amplifier circuit,
23A 1-bit A / D converter,
23a ... first input,
23b ... output,
23c ... second input,
25, 25C ... first capacitor,
27 ... second capacitor,
29, 29C ... third capacitor,
31 ... Switch circuit,
31a, 31b, 31c, 43, 49, 51, 53, 54, 55 ... switch,
33, 35 ... reference voltage source,
37, 37C ... reference voltage generation circuit,
41, 41C ... clock generator,
60 ... Up counter,
70: Register,
71 ... _EFI calculation part,
72 ... E _FR calculation section,
73 ... E _g1 calculation part,
74 ... E _m1 calculation part,
75: Output value calculation section after correction,
101 ... CMOS image sensor,
102 ... cell array,
102a ... pixels,
103 ... vertical shift register,
104. Integral / cyclic ADC array,
104a ... A / D converter,
105: Data register,
106: horizontal shift register,
107: Redundant-nonredundant conversion processing circuit,
108 ... column line,
111 ... A / D conversion circuit,
112 ... Digital correction circuit,
150 ... Column circuit,
151 ... Andgate,
152 ... adder,
153 ... registers,
201 .. Folded integration type A / D conversion circuit,
202... A cyclic A / D conversion circuit.

Claims (16)

In an integration / cyclic A / D conversion circuit that sequentially performs folding integration A / D conversion and cyclic A / D conversion using an operational amplifier circuit, a predetermined number of integrations (M) and a predetermined number of foldings (M ₁ A digital correction circuit that corrects the A / D conversion value by subtracting the digital value of the non-linear error caused by the gain error of the folding integration having A) from the A / D conversion value,
A digital value of a first error (E _FR ) that is a non-linear error caused by a gain error of the folding integration and is substantially proportional to the number of foldings (M ₁ ) is calculated, and the digital value is calculated from the A / D conversion value. A digital correction circuit for an A / D conversion circuit, comprising correction means for correcting an A / D conversion value by subtracting a first error (E _FR ). The correction means _applies the first reference voltage (V _RL ) as the input voltage (V _in ) to the operational amplifier circuit, performs one integration, and then outputs the output voltage of the operational amplifier circuit at a predetermined value. A first A / D conversion value obtained by performing cyclic A / D conversion for the number of cycles, and a second reference voltage (V _RH ) higher than the first reference voltage (V _RL ) as the input voltage (V _in ). ) Is applied to the operational amplifier circuit and integration is performed once, and then the second A / D conversion value obtained by performing cyclic A / D conversion on the output voltage of the operational amplifier circuit for a predetermined number of cycles. , And subtracting the first A / D conversion value from the second A / D conversion value and converting the subtraction value to the input side of the cyclic A / D conversion, first error a / D according to claim 1, wherein the calculating a digital value (E _FR) Circuit for digital correction circuit. The correction means calculates a square value of the integral nonlinear error (INL) based on a calculated value of the integral nonlinear error (INL) with respect to the first error (E _FR ) for a plurality of A / D conversion operations. 2. The A / D according to claim 1, wherein a digital value of the first error (E _FR ) when a cost function added to a plurality of A / D conversion operations is minimized is calculated. Digital correction circuit for D conversion circuit. The correction means further calculates a digital value of a second error (E _FI ) that is a non-linear error caused by the gain error of the folding integration and is an integration error of the folding integration, and calculates from the A / D conversion value 4. The digital correction for an A / D converter circuit according to claim 1, wherein the first error (E _FR ) and the second error (E _FI ) are subtracted. circuit. The correction means is based on code data indicating the number of integrations (i) indicating the number of integrations of the folding integration and data (D _I (i)) indicating whether or not the folding integration is performed. _{5. The} digital correction circuit for an A / D conversion circuit according to claim 4, wherein a digital value of the second error (E _FI ) is calculated. The correction means includes a circuit for calculating a digital value of the second error (E _FI ) in the column circuit.
An up-counter that counts the number of integrations (i) indicating the number of integrations;
A register that operates using data indicating the presence or absence of the folding integration as a clock; and
The number of integrations (i) from the up-counter and the data from the register are added to calculate the digital value of the second error (E _FI ) through the register with the added value data The digital correction circuit for an A / D conversion circuit according to claim 5, further comprising an adder that outputs the correction coefficient (m ₁ ). The correction means includes a capacitor (C ₁ ) connected to the input terminal of the operational amplifier circuit in the cyclic A / D conversion and an integration capacitor (C ₂ ) connected between the input terminal and the output terminal. A third error (E _g1 ) corresponding to an error due to a capacitor mismatch between the first error (E _FR ), the second error (E _FI ), and the second error (E _FI ); The digital correction circuit for an A / D conversion circuit according to any one of claims 4 to 6, wherein the third error ( _Eg1 ) is subtracted. The correction means includes a fourth error (E _m1 ) corresponding to an error due to a capacitor mismatch between two capacitors (C _1a , C1 _b ) connected to the input terminal of the operational amplifier circuit in the cyclic A / D conversion. ) And the third error (E _g1 ) and the fourth error in addition to the first error (E _FR ) and the second error (E _FI ) from the A / D conversion value. The digital correction circuit for an A / D conversion circuit according to any one of claims 4 to 7, wherein at least one of the errors (E _m1 ) is subtracted.   The integration / cyclic A / D conversion circuit includes the folded integration A / D conversion circuit and the cyclic A / D conversion circuit using the same circuit. Item 9. The digital correction circuit for an A / D conversion circuit according to any one of Items 1 to 8.   The integration / cyclic A / D conversion circuit includes the folded integration A / D conversion circuit and the cyclic A / D conversion circuit using different circuits, respectively. Item 9. The digital correction circuit for an A / D conversion circuit according to any one of Items 1 to 8. In an integration / cyclic A / D conversion circuit that sequentially performs folded integration A / D conversion and cyclic A / D conversion using an operational amplifier circuit,
An A / D conversion circuit comprising the digital correction circuit according to claim 1.   The integration / cyclic A / D conversion circuit includes the folded integration A / D conversion circuit and the cyclic A / D conversion circuit using the same circuit. Item 12. The A / D conversion circuit according to Item 11.   The integration / cyclic A / D conversion circuit includes the folded integration A / D conversion circuit and the cyclic A / D conversion circuit using different circuits, respectively. Item 12. The A / D conversion circuit according to Item 11. In an image sensor device that reads images,
An A / D conversion circuit for A / D converting the pixel value signal obtained by reading the image;
The A / D conversion circuit is an integration / cyclic A / D conversion circuit that sequentially performs folded integration A / D conversion and cyclic A / D conversion using an operational amplifier circuit. An image sensor device comprising the digital correction circuit according to any one of the above.   The integration / cyclic A / D conversion circuit includes the folded integration A / D conversion circuit and the cyclic A / D conversion circuit using the same circuit. Item 15. The image sensor device according to Item 14.   The integration / cyclic A / D conversion circuit includes the folded integration A / D conversion circuit and the cyclic A / D conversion circuit using different circuits, respectively. Item 15. The image sensor device according to Item 14.

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