JP4423427B2 - Analog-digital converter and image sensing semiconductor device - Google Patents

Description

  The present invention relates to an analog-digital converter and an image sensing semiconductor device.

Patent Document 1 describes an 8-bit integrating A / D converter element, and the integrating A / D converter element uses a ramp signal generator, a comparator, and a register. The integrating A / D converter element is connected to the column line. Non-Patent Document 1 and Non-Patent Document 2 describe a technique similar to the integral A / D converter element of Patent Document 1. Non-Patent Document 3 describes a successive approximation A / D converter using a capacitor, and the successive approximation A / D converter is connected to a column line. Non-patent document 4 describes an A / D converter including two cyclic A / D converter elements. The A / D converter is connected to the column line, and the cyclic A / D converter element includes two amplifiers.
JP 62-154981 A specification A. Simoni, A. Sartori, M. Gottaidi, A. Zorat, “A digital vision sensor,” Sensors and Actuators, A46-47, pp. 439-443, 1995. T. Sugiki, S. Ohsawa, H. Miura, M. Sasaki, N. Nakamura, I. Inoue, M. Hoshino, Y. Tomizawa, T. Arakawa, "A 60mW 10b CMOS image sensor with column-to-column FPN reduction , "Dig. Tech. Papers, Int. Solid-State Circuits Conf.," Pp.108-109,2000. B. Mansoorian, HY Yee, S. Huang, E. Fossum, "A 250mW 60frames / s 1280x 720 pixel 9b CMOS digital image sensor," Dig. Tech. Papers, Int. Solid-State CircuitsConf., "Pp.312-313 1999. S. Decker, RD McGrath, K. Bremer, CG Sodini, "A 256 x 256 CMOS imaging array with wide dynamic range pixels and column-parallel digitaloutput,“ IEEEJ. Solid-State Circuits, vol. 33, no. 12, Dec. 1998.

  The integral type A / D converters described in Patent Document 1, Non-Patent Document 1 and Non-Patent Document 2 have a long conversion time, and in particular, if the resolution is increased, the conversion time becomes exponentially longer. However, it is not easy to achieve higher resolution. The actual accuracy of the successive approximation A / D converter as described in Non-Patent Document 3 is only about 8 bits. Since the cyclic A / D converter element of Non-Patent Document 4 uses two amplifiers, the circuit scale increases.

  When trying to increase the resolution of the cyclic A / D converter, the conversion time does not increase exponentially unlike the integral A / D converter. Further, the conversion accuracy of the cyclic A / D converter does not reach the limit value as compared with the successive approximation A / D converter. However, in the cyclic A / D converter element of Non-Patent Document 4, it is desired to reduce the circuit scale. It is also desired to reduce the power consumed by the two amplifiers.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide an analog-digital converter capable of reducing current consumption and circuit scale, and an image using this A / D converter. An object is to provide a sensing semiconductor device.

  An analog-to-digital converter according to an aspect of the present invention includes (a) an input connected to an analog input, and first and second outputs, and receives an analog signal during a sampling period and performs the sampling. A gain stage for converting the analog signal in a conversion period after the period; and (b) a digital signal having a pair of inputs for receiving signals from the first and second outputs of the gain stage and a ternary digital value. An A / D converter circuit having an output for providing a signal; (c) a logic circuit for generating a control signal in response to the digital signal from the A / D converter circuit; and (d) according to the control signal. A D / A conversion circuit for providing a predetermined voltage signal to the gain stage; and (e) a switching circuit connected between the gain stage and the A / D conversion circuit. The A / D converter circuit receives first and second inputs for receiving signals from the first and second outputs of the gain stage and first and second reference signals for receiving first and second reference signals, respectively. A comparator for generating a first comparison result in the first comparison period and generating a second comparison result in the second comparison period, and connected to an output of the comparator; A storage circuit having an input and first and second outputs for providing the digital signal and storing the first and second comparison results. The switching circuit is connected between the first and second outputs of the gain stage and the positive and negative inputs of the comparator, and the first output and the second output of the gain stage. An output connected to the positive input and the negative input of the comparator, respectively, to generate the first comparison result, and the second output and the first output of the gain stage are respectively connected to the comparator A positive input and a negative input are connected to generate the second comparison result.

  According to this analog-digital converter, the comparator generates the first comparison result in the first comparison period and the second comparison result in the second comparison period. In order to operate the comparator in this way, a switching circuit is connected between the gain stage and the A / D conversion circuit. The switching circuit connects the first output and the second output of the gain stage to the positive input and the negative input of the comparator, respectively, in the first comparison period. The switching circuit connects the second output and the first output of the gain stage to the positive input and the negative input of the comparator, respectively, in the second comparison period. Thus, a single comparator can be used in a time-division manner by inverting the polarity of the input signal to the comparator using the switching circuit. As a result, the power consumption of the analog-digital converter according to the present invention is reduced and the area occupied by the semiconductor device is also reduced as compared with the analog-digital converter using two comparators in the A / D conversion circuit.

  In the analog-digital converter according to the present invention, the comparator includes a differential circuit having a pair of inputs and a differential output, and one end and the other end connected to one of the pair of inputs of the differential circuit. A first coupling capacitor, a second coupling capacitor having one end and the other end connected to the other of the pair of inputs of the differential circuit, and the other end of the first coupling capacitor. And a first switch connected between the first reference input and a second switch connected between the other end of the second coupling capacitor and the second reference input. It is preferable to contain.

  According to the analog-digital converter, signals from the positive input and the negative input are received by the respective capacitors via the switching circuit, and two reference signals from the first and second reference inputs are received by the first and second reference signals. Therefore, a difference signal between the signal from the positive input and the negative input and the two reference signals can be generated using the charge on the capacitor. The comparison result is amplified using a differential circuit.

  If necessary, the comparator includes a third switch connected between the other end of the first coupling capacitor and the positive input, and the other end of the second coupling capacitor. And a fourth switch connected to the negative input. According to this analog-digital converter, since the signals from the positive input and the negative input are received by the respective capacitors via the third and fourth switches, the third input is independent of the clock for the switch in the switching circuit. And a clock for the fourth switch.

  The analog-to-digital converter of the present invention has (a) an input connected to an analog input and first and second outputs, and receives an analog signal during the sampling period and after the sampling period. A gain stage for converting the analog signal during a conversion period; and (b) a digital signal having a pair of inputs for receiving signals from the first and second outputs of the gain stage and a ternary digital value. An A / D conversion circuit having an output; (c) a logic circuit that generates a control signal in response to the digital signal from the A / D conversion circuit; and (d) the gain stage according to the control signal. And a D / A conversion circuit for providing a predetermined voltage signal. The A / D conversion circuit has a positive input and a negative input for receiving signals from the first and second outputs of the gain stage, and first and second reference inputs, and A comparator that generates a comparison result in the first comparison period and a second comparison result in the second comparison period, and switches the first and second reference signals to the first and second reference inputs. A switching circuit for providing; an input connected to the output of the comparator; and first and second outputs for providing the digital signal; and storing the first and second comparison results. And a storage circuit. The switching circuit has an input for receiving the first and second reference signals, an output for providing a switched signal, and a signal source of the first and second reference signals and the first and second Connected to the reference input. The switching circuit provides the first and second reference signals to the first and second reference inputs of the comparator to generate the first comparison result, and the first and second reference signals A reference signal is provided to the second and first reference inputs of the comparator for generating the second comparison result.

  According to this analog-digital converter, the comparator generates the first comparison result in the first comparison period and the second comparison result in the second comparison period. For such operation, the comparator includes a switching circuit connected between the signal sources of the first and second reference signals and the first and second reference inputs. The switching circuit switches between the first and second reference signals corresponding to the first and second comparison periods, and provides these reference signals to the first and second reference inputs of the comparator. In this way, a single comparator can be used in a time division manner by switching the reference signal to the comparator using the switching circuit. As a result, the power consumption of the analog-digital converter according to the present invention is reduced and the area occupied by the semiconductor device is also reduced as compared with the analog-digital converter using two comparators in the A / D conversion circuit. In addition, a switch for switching the input to the signal line from the gain stage becomes unnecessary.

  In the analog-digital converter according to the present invention, the comparator includes a differential circuit having a pair of inputs and a differential output, and one end and the other end connected to one of the pair of inputs of the differential circuit. A first coupling capacitor, a second coupling capacitor having one end and the other end connected to the other of the pair of inputs of the differential circuit, and the other end of the first coupling capacitor. And a third switch connected between the positive input and a fourth switch connected between the other end of the second coupling capacitor and the negative input.

  According to the analog-digital converter, signals from the positive input and the negative input are received by the respective capacitors via the third and fourth switches. A difference signal between the signal from the positive input and the negative input and the two reference signals can be generated using the charge on the capacitor. This comparison result can be amplified using a differential circuit.

  If necessary, the comparator includes a first switch connected between the other end of the first coupling capacitor and the first reference input, and the second coupling capacitor. A second switch connected between the other end and the second reference input may be further included. According to this analog-digital converter, the first and second reference signals are received by the respective capacitors via the switching circuit, and signals from the positive input and the negative input are received via the first and second switches. Therefore, the clocks for the first and second switches can be set independently of the clocks for the switches in the switching circuit.

  In the analog-digital converter according to the present invention, the comparator includes a latch circuit that receives each signal from the differential output of the differential circuit, and an output of the latch circuit is connected to the input of the storage circuit. Yes.

  According to this analog-digital converter, the latch circuit can receive a digital signal indicating the comparison result, and the storage circuit stores the comparison result provided in a time division manner.

  In the analog-digital converter according to the present invention, the gain stage is connected to an operational amplifier circuit having a non-inverted output, an inverted output, and an inverted input, and an input that receives a signal for A / D conversion during the sampling period A capacitor connected to the inverting input of the operational amplifier circuit during the conversion period, and another capacitor connected between the inverting input and the non-inverting output of the operational amplifier circuit during the conversion period; including. According to the analog-digital converter, an A / D conversion stage having a simple configuration is provided.

  An image sensing semiconductor device according to another aspect of the present invention includes (a) an array including a plurality of sensing elements arranged in a plurality of rows and a plurality of columns, and the array includes the sensing elements in the columns. A plurality of analog-to-digital converters each for processing a signal on the column line, each of the analog-to-digital converters including a connected column line, each of which is described above, It is connected to the.

  According to this image sensing semiconductor device, the occupied area and the power consumption are reduced.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, an analog-digital converter capable of reducing current consumption and circuit scale is provided. Moreover, according to this invention, the image sensing semiconductor device using this A / D converter is provided.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the analog-digital converter and the image sensing semiconductor device of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

(First embodiment)
FIG. 1 is a diagram showing an image sensor as an example to which a cyclic A / D converter is applied. 2 and 3 are drawings showing a cyclic A / D converter. FIG. 4A is a diagram showing a timing chart for an A / D conversion circuit using a single comparator in a time division manner. FIG. 4B is a diagram illustrating a timing chart for the gain stage of the cyclic A / D converter, the D / A conversion circuit, and the like.

  Referring to FIG. 1, in the CMOS image sensor 1, a vertical shift register 3 is connected to a row of the cell array 2, and an A / D converter array 4 is connected to a column of the cell array 2. The A / D converter array 4 includes a plurality of A / D converters arranged in an array. An A / D converter 11 can be used as each A / D converter. The A / D converter 11 is used in the CMOS image sensor 1. In the CMOS image sensor 1, the cell array 2 has CMOS image sensor pixels 2a arranged in the row direction and the column direction. FIG. 1 shows an example of the CMOS image sensor pixel 2a. The pixel 2a generates the first signal S1 in the reset state and the second signal S2 in the light induced signal output. An input 13 of the A / D converter 11 is connected to the pixel 2a. A data register 5 is connected to the A / D converter array 4, and an A / D conversion value corresponding to a signal from the pixel 2 a is stored in the data register 5. The data register 5 provides the digital signal to the redundant representation / non-redundant representation conversion circuit 7 in response to the signal from the horizontal shift register 6. The redundant expression-non-redundant expression conversion circuit 7 generates an N-bit digital code corresponding to the signal from the pixel 2a.

In the pixel 2a, the photodiode DF receives light for one pixel (Optical Signal) related to the image. The gate of the selection transistor M _S is connected to the row select line S extending in the row direction. The gate of the reset transistor M _R is connected to the reset line R. The gate of the transfer transistor M _T is connected to the transfer selection line extending in the row direction. One end of the photodiode D _F is connected to the floating diffusion layer FD via the transfer transistor M _T. Floating diffusion layer FD is connected to a reset potential line Reset via the reset transistor M _R, is connected to the gate of the transistor M _A. One current terminal (for example, drain) of the transistor M _A is connected to the column line 8 via the selection transistor M _S. Transistor M _A is provided in the column line through the selection transistor M _S a potential corresponding to the charge amount of the floating diffusion layer FD.

In the pixel having this structure, the noise canceling operation is performed as follows. First, to provide a reset control signal R to the reset transistor M _R, it resets the floating diffusion layer FD. Through the amplification transistor M _A, read out the reset level. The pixel 2a generates the first signal S1 when the floating diffusion layer FD is in the reset state. Then, a charge transfer control signal TX is supplied to the transfer transistor M _T, is transferred from the photodiode D _F photoinduced signal charges to the floating diffusion layer FD. Thereafter, through the transistor M _A, reading the signal level. The second signal S2 is generated when the floating diffusion layer FD of the pixel 2a is in a photo-induced charge accumulation state. The difference between the reset level and the signal level is obtained using a cyclic A / D converter as shown in FIG. As a result, noises such as fixed pattern noise due to variations in the transistor characteristics of the pixel 2a and reset noise generated when the floating diffusion layer is reset are canceled.

2 and 3, the cyclic A / D converter 11 includes a gain stage 15, an A / D conversion circuit 17, a logic circuit 19, a D / A conversion circuit 21, and a switching circuit 123. Is provided. An analog input 13 of the cyclic analog-digital converter 11 is provided for receiving an analog signal. Gain stage 15 has an input 15a connected to the analog input 13, has a first and a second output 15b, with receiving an analog signal during a sampling period T _S, during the conversion period T _C Convert received analog signals. The A / D conversion circuit 17 has a pair of inputs 17a and 17b and outputs 17c and 17d. The pair of inputs 17a and 17b receive signals V _oP and V _oM from the first and second outputs 15b of the gain stage 15, respectively. Output 17c, 17d, respectively, to provide a digital signal _{S DIG} corresponding to the signal from the output 15b of the gain stage 15, the digital signal _{S DIG} has, for example, a digital value of 3 values (D0, _D1) ( " _D1 ”represents an inverted signal of“ D1 ”). The logic circuit 19 generates a control signal S _CONT in response to the digital signal _SDIG from the A / D conversion circuit 17. The D / A conversion circuit 21 provides a voltage signal V _DAC called a voltage signal V _REFN or V _REFP to the gain stage 15 according to the control signal S _CONT . In an example of the analog-digital converter 17, the switching circuit 123 is connected between the gain stage 15 and the A / D conversion circuit 17.

The A / D conversion circuit 17 includes a comparator 131 and a storage circuit 133. The comparator 131 includes a positive input 131a and a negative input 131b for receiving signals V _oP and V _oM from the first and second outputs 15b and 15c of the gain stage 15, and first and second reference signals (V _REF1 , V _REF2 , eg, + V _ref / 4, −V _ref / 4), respectively, has first and second reference inputs 131c, 131d. As shown in FIG. 4A, the comparator 131 generates the first comparison result V _COMP1 in the first comparison period T _COMP1 and the second comparison result V _COMP2 in the second comparison period T _COMP2 . Generate. The storage circuit 133 has an input 33a connected to the output 131e of the comparator 131 and first and second outputs 33b and 33c for providing a digital signal V _DIG , and the first and second comparison results. V _COMP1 and V _COMP2 are stored. The switching circuit 123 is connected between the first and second outputs 15 b and 15 c of the gain stage 15 and the positive input 17 a and the negative input 17 b of the comparator 17. The switching circuit 123 connects the first output 15b and the second output 15c of the gain stage 15 to the positive input 131a and the negative input 131b of the comparator 131, respectively, in the first comparison period T _COMP1 and also the first output of the gain stage 15 The second output 15c and the first output 15b are connected to the positive input 131a and the negative input 131b of the comparator 131, respectively, in the second comparison period T _COMP2 .

According to the A / D converter 11, the comparator 131 generates the first comparison result V _COMP1 in the first comparison period T _COMP1 and the second comparison result V _COMP2 in the second comparison period T _COMP2 . Generate. In order to operate the comparator 131 in this way, the switching circuit 123 is connected between the gain stage 15 and the A / D conversion circuit 17. During the first comparison period T _COMP1 , the first and second outputs 15b of the gain stage 15 are connected to the positive input 131a and the negative input 131b of the comparator 131 via the switching circuit 123, respectively. Further, in the second comparison period T _COMP2 , the second output 15c of the gain stage 15 is connected to the positive input 131a of the comparator 131 via the switching circuit 123, and the first output 15b of the gain stage 15 is used. Is connected to the negative input 131 d of the comparator 131 via the switching circuit 123.

  Thus, the polarity of the input signal to the comparator 131 can be inverted using the switching circuit 123, and the single comparator 131 can be used in a time division manner. As a result, the power consumption of the analog / digital converter 11 according to the present embodiment is reduced and the area occupied by the semiconductor device is also reduced as compared with the analog / digital converter using two comparators in the A / D conversion circuit 17. The

The A / D conversion circuit 17 compares the input analog signal with predetermined reference signals V _REF1 and V _REF2 and provides comparison result signals D ₀ and D ₁ . The reference signal V _REF1 can be, for example, −V _ref / 4, and the reference signal V _REF2 can be, for example, + V _ref / 4.
Range of input analog signal V _i Digital signal (1) −V _ref / 4> V _i , −1 (D ₁ = 0, D ₀ = 0)
(2) V _ref / 4 ≧ V _i ≧ −V _ref / 4, 0 (D ₁ = 0, D ₀ = 1)
(3) V _i > + V _ref / 4, +1 (D ₁ = 1, D ₀ = 1)
It becomes. The A / D converter circuit can generate a ternary redundant digital signal by comparing the input analog signal with two predetermined reference signals. According to this conversion circuit, the input analog signal is compared with two predetermined reference signals, so that a ternary digital signal is obtained.

  The A / D conversion circuit 17 and the switching circuit 123 will be described again with reference to FIG. The switching circuit 123 is configured to include, for example, four switches 143a, 143b, 143c, and 143d. The switch 143a operates in response to the clock_φc (inverted signal of the clock φc), and is connected between the input 123a and the output 123d. The switch 143b operates in response to the clock φc and is connected between the input 123a and the output 123c. The switch 143c operates in response to the clock φc and is connected between the input 123b and the output 123d. The switch 143d operates in response to the clock_φc, and is connected between the input 123b and the output 123c.

By such switching, the positive input 131a of the comparator 131 is connected to the non-inverted output 23c of the operational amplifier circuit 23 via the one output 15b in the first comparison period T _COMP1, and the negative input 131b of the comparator 131 is In the first comparison period T _COMP1 , the inverted output 23d of the operational amplifier circuit 23 is connected to the other output 15b. During this connection, the comparator 131 generates the first comparison result V _COMP1 (for example, “D ₀ ” shown in FIG. 2). The negative input 131b of the comparator 131 is connected to the non-inverted output 23c of the operational amplifier circuit 23 through one output 15b in the second comparison period T _COMP2, and the positive input 131a of the comparator 131 is In the comparison period T _COMP2 , the inverted output 23d of the operational amplifier circuit 23 is connected to the other output 15b. During this connection, the comparator 131 generates the second comparison result V _COMP2 (for example, “D ₁ ” shown in FIG. 2).

  Therefore, as shown in FIGS. 5 (a) and 5 (b), the signals from the non-inverted output 23c and the inverted output 23d of the operational amplifier circuit 23 are switched to opposite polarities, so that the fully differential configuration is simple. Provided to one comparator. Therefore, it is not necessary to complicate the circuit configuration of the comparator and the operation of the comparator for the purpose of configuring the A / D conversion circuit using a single comparator.

Referring to FIG. 2 again, the two comparison results V _COMP1 and V _COMP2 are provided to the storage circuit 133. The storage circuit 133 includes a D-type flip-flop circuit 145a connected to the output 131e of the comparator 131 and operating in response to the clock φc, a D-type flip-flop circuit 145b connected thereto and operating in response to the clock_φc, a comparator A NOT circuit 145c connected to the output 131e of 131, and a D-type flip-flop circuit 145d that operates in response to the clock_φc in response to a signal from the NOT circuit 145c.

As described above, according to the analog-digital converter according to the present embodiment, the input signal is supplied to the comparator, and then the input signal is supplied to the comparator of the input signal with the polarity reversed, and the signal is supplied to the reference voltage V _ref / 4. Compare with -V _ref / 4. A NOT circuit is used so as to correspond to the above values (1) to (3). The value D ₀ indicating the first comparison result is stored in the two-stage D-type flip-flop circuits 145a and 45b, and the value D ₁ indicating the second comparison result is stored in the D-type flip-flop circuit 145d. . These flip-flop circuits provide digital values in synchronization with a desired clock.

In another example of the A / D converter, the switching circuit 123 can be used in the A / D conversion circuit 17. In addition to the comparator 131 and the storage circuit 133, the A / D conversion circuit 17 includes a switching circuit 123 connected between the signal sources of the first and second reference signals and the first and second reference inputs. . The comparator 131 includes a positive input 131a and a negative input 131b for receiving signals V _oP and V _oM from the first and second outputs 15b and 15c of the gain stage 15, and first and second reference signals (V _REF1 , V _REF2 , for example, + V _ref / 4, −V _ref / 4), has first and second reference inputs 131 c and 131 d for receiving via the switching circuit 123. The switching circuit 123 switches the first and second reference signals corresponding to the first and second comparison periods T _COMP1 and T _COMP2 and _applies them to the first and second reference inputs 131c and 131d of the comparator 131. Provides a reference signal. Thus, by switching the reference signal to the comparator 131 using the switching circuit 123, a single comparator can be used in a time-sharing manner, and a switch for switching the input to the signal line from the gain stage becomes unnecessary. . In addition, the power consumption of the analog-digital converter according to the present embodiment is reduced and the area occupied by the semiconductor device is also reduced as compared with the analog-digital converter using two comparators in the A / D conversion circuit.

According to this analog-digital converter, the comparator 131 can generate the first comparison result V _COMP1 in the first comparison period T _COMP1 and the second comparison result V _COMP2 in the second comparison period T _COMP2. . The two comparison results V _COMP1 and V _COMP2 are provided to the storage circuit 133.

  Referring again to FIGS. 2 and 3, the gain stage 15 has an input 15 a that receives signals S 1 and S 2 from the image sensor 1, an output 15 b, and an operational amplifier circuit 23. The operational amplifier circuit 23 has first and second inputs (inverted input, non-inverted input) 23a, 23b and first and second outputs (non-inverted output, inverted output) 23c, 23d. The gain stage 15 operates as follows. In the first period T1, the first signal S1 is sampled. In the second period T2, the second signal S2 is sampled so as to have a polarity opposite to that of the sampling of the first signal S1. In the third period T3, operation values are generated in the first and second outputs 23c and 23d of the operational amplifier circuit 23. In the fourth period T4, the operation values generated at the first and second outputs 23c and 23d of the operational amplifier circuit 23 are sampled for the next operation.

  The gain stage 15 includes a first capacitor 25, a second capacitor 27, a third capacitor 31, and a fourth capacitor 33. The first capacitor 25 receives the first signal S1 during the first period T1. A charge corresponding to the first signal S1 is accumulated in the other end 25b of the first capacitor 25. The second capacitor 27 receives the second signal S2 in the second period T2. A charge corresponding to the second signal S2 is accumulated in the other end 27b of the second capacitor 27. The third capacitor 31 receives the first signal S1 during the first period T1. A charge corresponding to the first signal S1 is accumulated at one end 31a of the third capacitor 31. The fourth capacitor 33 receives the second signal S2 in the second period T2. The charge corresponding to the second signal S2 is accumulated at one end 33a of the fourth capacitor 33.

The first capacitor 25 is connected between the terminal 21a of the D / A conversion circuit 21 and the first input (for example, inverting input) 23a of the operational amplifier circuit 23 in the third period T3. The second capacitor 27 is connected between the terminal 21b of the D / A conversion circuit 21 and the second input (for example, non-inverting input) 23b of the operational amplifier circuit 23 in the third period T3. The A / D conversion circuit 17 provides the digital signal _SDIG in the second and third periods T2 and T3. As a result, a digital signal corresponding to the signal S <b> 1 input to the A / D converter 11 is generated by the A / D conversion circuit 17.

The third capacitor 31 is connected between the first input (for example, inverting input) 23a and the first output (for example, non-inverting output) 23c of the operational amplifier circuit 23 in the third and fourth periods T3 and T4. Connected to. The fourth capacitor 33 is connected between the second input (for example, non-inverting input) 23b and the second output (for example, inverting output) 23d of the operational amplifier circuit 23 in the third and fourth periods T3 and T4. Connected to. The A / D conversion circuit 17 outputs the output of the gain stage 15 so that the gain stage 15 performs an operation for cyclic A / D conversion in the third period T3 after the first and second periods T1 and T2. 15c, the digital signal _S DIG three values corresponding to a signal from 15d _{(S DIG} is _(D 0, consisting of _{D 1))} to provide the third period T3. The D / A conversion circuit 21 provides the voltage signal _SVOL to the gain stage 15 in the third period T3. In response to this, the charges accumulated in the first and second capacitors 25 and 27 are transferred to the third and fourth capacitors 31 and 33, and the first and second outputs 23c of the operational amplifier circuit 23 are transferred. , 23d, the calculated value is generated. The input of the A / D conversion circuit 17 is connected to the output 15b of the gain stage 15, and the output 15b of the gain stage 15 is connected to one ends 31a and 33a of the capacitors 31 and 33, respectively. The other ends 31a and 33a of the capacitors 31 and 33 are connected to the first and second inputs 23a and 23b of the operational amplifier circuit 23, respectively.

According to this cyclic A / D converter 11, the first and second signals S1 and S2 are sampled by using the first and second capacitors 25 and 27, respectively, so that no noise cancellation circuit is used. Noise cancellation can be performed. Further, after sampling, amplification is performed using the gain stage 15, and an amplified signal corresponding to the difference signal between the first and second signals S1 and S2 is generated at the outputs 23c and 23d of the operational amplifier circuit 23. Is done. For this reason, the noise level can be greatly improved by the arithmetic operation of the A / D converter 11. Also,
The cyclic A / D converter 11 can include a switch circuit 24 for providing a common voltage V _COM to the outputs 23c and 23d of the operational amplifier circuit 23 during sampling. The switch circuit 29 of the gain stage 15, the common signal V to the one end 27a of the second capacitor 27 in the second period T2 with the first period T1 to the end 25a of the first capacitor 25 to provide a common signal _{V COM} Provide _COM . For this, the switch circuit 29 includes a switch 29a responsive to the clock phi _SHI1, and a switch 29b responsive to the clock φ _SHI2. The common voltage _VCOM is a constant voltage. The outputs 23c and 23d of the operational amplifier circuit 23 are connected to the common voltage source via the switches 24a and 24b of the switch circuit 24 in the first and second periods T1 and T2, respectively. Switch 24a, 24b is responsive to the clock phi _S that becomes active first and second periods T1, T2.

As can be understood from the circuit diagram of FIG. 3, the cyclic A / D converter 11 uses a relatively simple circuit, and this circuit effectively reduces random noise, and a very high-precision A / D converter. Provides / D conversion. The basic operation for this purpose is to sample two output signals (signal level and reset level) continuously output from a pixel using two capacitors, and perform noise cancellation on the sampled voltage signal. The basic operation of A / D conversion is performed (the input signal is amplified at an amplification factor (for example, 2 times) determined by the capacitance ratio of the capacitor, and the D / A conversion value is subtracted). Further, when sampling using capacitors, a common voltage V _COM is supplied to the terminals of the capacitors. Thanks to the application of the common voltage V _COM, one end of the sampling capacitor a fixed potential are provided rather than the virtual ground point. Therefore, since this capacitor end is not connected to a circuit such as an amplifier during sampling, it is not affected by this circuit during sampling. Therefore, for example, it is possible to reduce the influence of noise of a transistor (source follower-connected transistor) in the pixel, which is expressed by kT / C (k: Boltzmann constant, T: absolute temperature, C: capacitance for sampling). The influence of noise components can be reduced. This eliminates the need for a noise canceling circuit that has been necessary in the past, and reduces random noise generated by the circuit of the cyclic A / D converter. The configuration of the cyclic A / D converter includes one gain stage or two gain stages.

  The above basic operation is embodied as follows. Two signals (signal level and reset level) output from the pixel 2a are continuously output on the column line 8 which is a single line.

These two signals are sampled using two capacitors 25 and 27. A reset level is stored from the column line 8 to one capacitor 25, and a signal level is stored from the column line 8 to the other capacitor 27. The column line 8 is switched using the switches 37a and 37b. When the column line 8 is connected to one end of the capacitor via any of the switches 37a and 37b, the common voltage _VCOM is applied to the other end of the capacitor. For this reason, the other end of the capacitor is not connected to the virtual ground point, but the common voltage V _COM is applied. In the subsequent subtraction operation, random noise is cancelled. Immediately before the end of the sampling operation, the comparator 131 in the A / D converter circuit 17 is used in a time-sharing manner to perform the first A / D conversion on the differential voltage between two consecutive sampled values, and to send a control signal. Generate.

  After completion of this operation, a basic arithmetic operation for cyclic A / D conversion is performed on two consecutive sample values. The first A / D conversion result is used as a control signal for the D / A conversion circuit required in the basic arithmetic operation. In this operation, noise cancellation of the pixel signal is performed simultaneously with the basic calculation operation. Thereafter, a cyclic A / D conversion operation is performed using one operational amplifier circuit and four capacitors.

  The A / D converter 11 will be further described with reference to FIGS. 2, 3 and 4B again. In the cyclic A / D converter 11, the first and second outputs 23c and 23d of the operational amplifier circuit 23 are connected to the one ends 25a and 27a of the first and second capacitors 25 and 27 in the fourth period T4. Connected to each. The other ends 25b and 27b of the first and second capacitors 25 and 27 are connected to each other in the fourth period T4. According to the cyclic A / D converter 11, a signal for subsequent A / D conversion for the lower bits can be stored in the first and second capacitors 25 and 27.

The logic circuit 19 generates control signals φ _DZ , φ _DP , and φ _DN that control the first to third switches 51 a to 51 e, respectively. The values of the digital signals D1, D0 determine which of the control signals φ _DZ , φ _DP , φ _DN is active. A ternary A / D conversion is performed on these three areas to assign digital codes of “−1”, “0”, and “+1”. The first code is the most significant digit (MSB).

The D / A converter 21 provides a predetermined voltage corresponding to the control signals φ _DZ , φ _DP , and φ _DN to the capacitor end 25 b and the capacitor end 27 b in the gain stage 15. The D / A converter 21 has outputs 21a and 21b connected to the inputs 15c and 15d of the gain stage 15, respectively. The first voltage source 49a provides the voltage V _REFP . The second voltage source 49b provides the voltage V _REFN . The output of the first voltage source 49a is connected to the output 21a via the switch 51a, and the output of the second voltage source 49b is connected to the output 21a via the switch 51b. The output of the first voltage source 49a is connected to the output 21b via the switch 51c, and the output of the second voltage source 49b is connected to the output 21b via the switch 51d. The output 21a and the output 21b are connected to each other via the switch 51e.

That is, the output of the A / D conversion circuit 17 provides a redundant digital code, and in response to the redundant digital code, the control circuit 19 generates a control signal S _CONT for controlling the D / A conversion circuit 21. To do. For example, in order to obtain an A / D conversion value having a resolution of 12 bits in the cyclic A / D conversion operation, 11 cyclic operations are required.

  The clock signal for the switch shown in FIG. 2 and the clock signal shown in the timing chart of FIG. 4 are generated by a clock generator 35.

Reference values V _REFN / 4 and V _REFP / 4 are supplied to the comparator 131 in the A / D conversion circuit 17. As shown in FIG. 6, the A / D conversion circuit 17 assigns digital values (+1, 0, −1) to the output value V _O of the gain stage 15 for the three input voltage V _i regions. In FIG. 6, V _REFP = −V _REFN = V _ref . Since the digital signal of the gain stage takes the three values “−1”, “0”, and “+1”, it can be considered that 1.5-bit A / D conversion is performed per gain stage.

The logic circuit 19 generates control signals φ _DZ , φ _DP , and φ _DN for controlling the first to third switches 51 a to 51 e, respectively. The values of the digital signals D1, D0 determine which of the control signals φ _DZ , φ _DP , φ _DN is active. A ternary A / D conversion is performed on these three areas to assign digital codes of “−1”, “0”, and “+1”. The first code is the most significant digit (MSB).

The D / A converter 21 provides a predetermined voltage corresponding to the control signals φ _DZ , φ _DP , and φ _DN to the capacitor end 25 b and the capacitor end 27 b in the gain stage 15. The D / A converter 21 has outputs 21a and 21b connected to the inputs 15c and 15d of the gain stage 15, respectively. The first voltage source 49a provides the voltage V _REFP . The second voltage source 49b provides the voltage V _REFN . The output of the first voltage source 49a is connected to the output 21a via the switch 51a, and the output of the second voltage source 49b is connected to the output 21a via the switch 51b. The output of the first voltage source 49a is connected to the output 21b via the switch 51c, and the output of the second voltage source 49b is connected to the output 21b via the switch 51d. The output 21a and the output 21b are connected to each other via the switch 51e.

That is, the output of the A / D conversion circuit 17 provides a redundant digital code, and in response to the redundant digital code, the control circuit 19 generates a control signal S _CONT for controlling the D / A conversion circuit 21. To do. For example, in order to obtain an A / D conversion value having a resolution of 12 bits in the cyclic A / D conversion operation, 11 cyclic operations are required.

This operation, which describes the operation of the cyclic A / D converter, then provides a method for converting an analog signal from a pixel of the image sensor into a digital signal. Prior to the operations described below, to reset the gain stage 15 by closing the switch 45a, 45b in response to the clock phi _R.

FIG. 7A is a diagram showing connection of main circuit elements in the first sampling step. In the gain stage 15, a clock phi _SH1d, switch 37a responsive to phi _SH1, closes the 29a, clock phi _1, phi _3, the switch 39a responsive to phi _S, closing 39 b, 43a, 43 b, 24a, and 24b. The other switches 37b, 29b, 45a, 45b, 47a, 47b, 53 are opened. In the first period T1, the capacitor end 25b is connected to the column line 8 of the image sensor 1 through the switch 37a, and the common signal V _COM is applied to the capacitor end 25a through the switch 27a, so that the signal V _RES (of the pixel 3a The charge Q 1 corresponding to the reset level when the floating diffusion layer is in the reset state is sampled in the first capacitor 25. The charge Q2 corresponding to the signal _VRES is also stored through the switch 43a in the second capacitor 27 to which the common voltage _VCOM is applied through the switch 39a.

FIG. 7B is a diagram showing connection of main circuit elements in the second sampling step. In the gain stage 15, a clock φ _SH2d, φ _SH2, switch 37b responsive to phi _S, closes the 29 b, clock phi _1, switch 39a responsive to phi _3, closes 43a, 39 b, 43 b, 24a, and 24b. The other switches 37a, 29a, 45a, 45b, 47a, 47b, 53 are opened. In the second period T2, the capacitor end 27b is connected to the column line 8 and the common signal _VCOM is applied to the capacitor end 27a, so that the signal V _SIG (the floating diffusion layer of the pixel 2a is in a photo-induced charge accumulation state). Signal level) is sampled in the second capacitor 27. Further, the charge Q4 corresponding to the signal V _SIG is also stored through the switch 43b in the fourth capacitor 33 to which the common voltage V _COM is applied through the switch 39b. The switch 24a in response to the clock phi _S active on the first and second sampling step, since closing 24b, output 23c of the operational amplifier circuit 23, the 23d, are connected to a common voltage source. Thereby, it is possible to prevent the output of the operational amplifier circuit 23 from fluctuating.

Further, the signal V _SIG is compared with the first and second reference values (reference values V _REFN / 4 and V _REFP / 4 in the comparator 131) to generate a digital value. That is, the first A / D conversion operation is performed using a single comparator 131 in a time division manner.

With the operation shown in FIG. 7, the A / D converter performs sampling of two continuous pixel output signals (V _SIG , V _RES ) using the periods T1 and T2 of two clocks.

FIG. 8A is a diagram showing connection of main circuit elements in the A / D conversion step. In the gain stage, the switch 39a responsive to the clock _{φ 1, φ SH3, 39b,} 47a, and 47b are closed. The other switches 29a, 29b, 37a, 37b, 43a, 43b, 45a, 45b, 53 are opened. In the third period T3, the capacitor terminal 25a is connected to one of the inverting input 23a and the non-inverting input 23b (in this embodiment, the inverting input 23a) of the operational amplifier circuit 23, and the other of the inverting input 23a and the non-inverting input 23b ( In this embodiment, the capacitor end 27a is connected to the non-inverting input 23b). The D / A conversion circuit 21 applies a voltage signal to one ends 25b and 27b of the capacitors 25 and 27, respectively. The voltage signal from the D / A conversion circuit 21 is determined according to a digital value corresponding to the first A / D conversion value. In response to this application, the first and second charges Q1 and Q1 are rearranged to generate operation values at the outputs 23c and 23d of the operational amplifier circuit 23. The output voltage V _OUT of the operational amplifier circuit 23 is
V _OUT = 2 × (V _RES −V _SIG ) −D × V _ref
It is expressed. Capacitance ratios C1P / C2P, C1M / C2M = 1 (= C ₁ / C ₂ ), and symbol D is a value determined according to a digital value corresponding to the first A / D conversion value, (+1 , 0, -1). Note that V _ref = −V _REFN = V _REFP . In this operation, by performing the subtraction operation of the reset level and the signal level, not only noise cancellation is performed, but also the basic arithmetic operation of the A / D converter is performed directly. As a basic arithmetic operation, the sampled signal is amplified twice and the voltage signal from the D / A conversion circuit is applied to the gain stage. Only by performing this basic arithmetic operation, a noise cancellation circuit is unnecessary, and A / D conversion with low random noise becomes possible.

Further, the signal V _OUT is compared with first and second reference values (reference values V _REFN / 4 and V _REFP / 4 in the comparator 131) to generate a digital value. That is, an A / D conversion operation for the MSB is performed using a single comparator 131 in a time division manner.

FIG. 8B is a diagram showing connection of main circuit elements in the third sampling step. In the gain stage, the clock phi _2, phi _3, switch 53,43a responsive to phi _SH3, closing 43 b, 47a, and 47b. The other switches 29a, 29b, 37a, 37b, 39a, 39b, 45a, 45b are opened. In the fourth period T4, the capacitor terminal 25b is connected to the first output 23c of the operational amplifier circuit 23, and the capacitor terminal 27b is connected to the second output 23d of the operational amplifier circuit 23 to correspond to the operational value _VOUT . The charge to be sampled is sampled in the first and second capacitors 25 and 27. The third capacitor 31 is connected between the first input 23 a and the first output 23 c of the operational amplifier circuit 23, and the fourth capacitor 33 is connected to the second input 23 b of the operational amplifier circuit 23. Connected to the second output 23d.
The gain stage 15 repeats the operations in the third and fourth periods. By repeating the desired number of times, multi-bit A / D conversion with a desired resolution can be performed.

FIG. 9 is a diagram illustrating an example of a comparator for the analog-digital converter according to the present embodiment. The comparator 131 can include a capacitor coupling circuit 90, a differential circuit 91, and a latch circuit 92. Capacitor circuit 90 includes a positive input 90a and a negative input 90b that receive signals from inputs 131a and 131b of comparator 131, respectively, and reference inputs 90c and 90d that receive reference signals V _REF1 and V _REF2 , respectively, and outputs 90e and 90f. Outputs 91 c and 91 d of the differential circuit 91 are connected to the latch circuit 92, and the result of signal comparison by the differential circuit 91 is captured by the latch circuit 92.

  Capacitor coupling circuit 90 includes coupling capacitors 95, 97 and switches 99a, 99b, and can further include switches 99c, 99d if necessary. The capacitor coupling circuit 90 shown in the figure is an example, and the analog-digital converter in the present embodiment is not limited to a specific configuration.

When the capacitor coupling circuit 90 does not include the switches 99c and 99d, signal input to the coupling capacitors 95 and 97 is performed by switching the switches in the switching circuit 123. The first coupling capacitor 95 has one end 95 a and the other end 95 b connected to the input 91 a of the differential circuit 90. The second coupling capacitor 97 has one end 97 a and the other end 97 b connected to the input 91 b of the differential circuit 91. The first switch 99a is connected between the other end 95b of the first coupling capacitor 95 and the positive input 131a, and operates in response to the clock _φcR1 . The second switch 99b is connected between the other end 97b of the second coupling capacitor 97 and the negative input 131b, and operates in response to the clock _φcR1 . Fifth switch 99e is connected between one end 95a of the common terminal _{T COM} and the first coupling capacitor 95 to receive a common signal _{V COM2,} it operates in response to the clock phi _CR2. Switch 99f of the sixth is connected between one end 97a of the common terminal _{T COM} and second coupling capacitors 97, it operates in response to the clock phi _CR2.

When the capacitor coupling circuit 90 includes the switches 99c and 99d, the third switch 99c is connected between the other end 95b of the first coupling capacitor 95 and the reference input 90c, and is connected to the clock _φcR2d . Operates in response. The fourth switch 99d is connected between the other end 97b of the second coupling capacitor 97 and the reference input _90d , and operates in response to the clock _φcR2d . Signals are input to the coupling capacitors 95 and 97 by switching the third switch 99c and the fourth switch 99d.

In the present embodiment, the signals V _oP and V _oM from the gain stage 15 are switched using the switching circuit 123. Apart from this circuit example, in the circuit example in which the reference signals V _REF1 and V _REF2 are switched using the switching circuit 123, the capacitor coupling circuit 90 is connected between the other end 95b of the first coupling capacitor 95 and the positive input 131a. And a second switch connected between the other end 97b of the second coupling capacitor 97 and the negative input 131b. The signals from the positive input 131a and the negative input 131b are received by the capacitors 95 and 97 through these switches. A difference signal between the signal from the positive input 131a and the negative input 131b and the two reference signals can be generated using the charges on the capacitors 95 and 97. This comparison result can be amplified using a differential circuit.

If necessary, the capacitor coupling circuit 90 includes an additional switch connected between the other end 95a of the first coupling capacitor 95 and the reference input 90c, and the other end 97b of the second coupling capacitor 97. And a further switch connected between the reference input 90d. Since the reference signals V _REF1 and V _REF2 are received by the respective capacitors 95 and 97 via these switches and switching circuit 123, additional switches and further switches are independent of the clock for the switches in the switching circuit 123. You can set the clock for.

The operation of the comparator 131 will be described with reference to FIGS. 2 and 4B. The clock φ _cR2d indicates a clock _obtained by delaying the clock φ _cR2 . A node between the inputs 91a and 91b of the differential circuit 91 and the capacitors 95 and 97 has a switch _φ _cR2 (“_φ _cR2 ” indicates an inverted signal of φ _cR2 ) in response to a switch 99e and 99f. A common signal _VCOM2 is applied. In response to the clock _φcR1 , the signals V _oM and V _oP from the gain stage 15 are provided to the capacitors 95 and 97 of the comparator 131 via the switching circuit 123 and the switches 99a and 99b. As a result, charges corresponding to the signals V _oM and V _oP from the gain stage 15 are accumulated in the capacitors 95 and ₉₇ , respectively.

After this, the switch 99e in response to the clock _Fai _CR2, close to 99f, input 91a of the differential circuit 91, the common signal _{V COM2} remain in 91b. When the reference signals V _REF1 and V _REF2 are applied to the other ends 95b and 97b of the capacitors 95 and 97 via the switches 99c and _99d in response to the clock _φcR2d , the difference between the one ends 95a and 97a of the capacitors 95 and 97 is Signals (V _oP −V _REF1 , V _oM −V _REF2 ) are generated. In response to the difference signal, the differential circuit 91 operates and generates a comparison result at the outputs 91c and 91d. This comparison result is obtained by using the forward connection switching circuit 123.

  When the switching circuit 123 is operated in the same manner as described above, the comparator 131 can be used in a time division manner.

FIG. 10 is a diagram illustrating an example of a differential circuit and a latch circuit. The latch circuit 92 can include, for example, an RS flip-flop circuit. The differential circuit 91 includes a first differential stage 93a and a second differential stage 93b. The first differential stage 93a, so operates in response to the clock phi _1, are activated in the first period T _1. The second differential stage 93b is so operated in response to the clock phi _2, it is activated in the second period T _2.

The first differential stage 93a includes a pair of n-type field effect transistors MN1 and MN2 that receive differential signals from the inputs 91a and 91b. A current source transistor MN3 is connected to the sources of the n-type field effect transistors MN1 and MN2, and this current source supplies a constant current according to the bias voltage Vbn. A load circuit is connected to the drains of the n-type field effect transistors MN1 and MN2. The load circuit includes p-type field effect transistors MP1 and MP2 having cross-connected gates, and diode-connected p-type field effect transistors MP3 and PM4. Field effect transistor MN1, the inter MN2 drains of being connected field effect transistor MP5, and the gate thereof receives the clock phi _C1 for equalization.

The second differential stage 93b includes a pair of n-type field effect transistors MN6 and MN7 that receive the differential signal from the first differential stage 93a. n-type field effect transistor MN6, to MN7 source is connected a current source transistor MN8, the current source supplies a constant current corresponding to the amplitude of the clock phi _C2. A load circuit is connected to the drains of the n-type field effect transistors MN6 and MN7. This load circuit includes a p-type field effect transistor MP5, PM6 and a gate which are cross-connected, and a p-type field effect transistors MP7, MP8 having a gate receiving the clock phi _C2. N-type field effect transistors MN4 and MN5 having cross-connected gates are connected between the drains of the n-type field effect transistors MN6 and MN7 and the load circuit.

  With such a differential circuit, forward connection and reverse connection are alternately performed, and two levels can be compared with a single comparator. This reduces the circuit scale and power consumption. This circuit is an example, and other circuit configurations may be used.

  While the principles of the invention have been illustrated and described in the preferred embodiment, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. Although the present embodiment has been described with reference to the gain stage shown in FIG. 1, the present invention is not limited to the specific gain stage configuration disclosed in the present embodiment. A gain stage having a single-ended configuration can be used, and a gain stage including more capacitors can also be used. Further, the switch used in the embodiment can include, for example, a MIS analog switch. Furthermore, the configuration of the sensing element used in the embodiment is an exemplification, and various types of sensing elements can be used as necessary. In addition, the present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1 is a diagram illustrating an image sensor. FIG. 2 is a diagram showing a cyclic A / D converter. FIG. 3 is a diagram showing a gain stage and a D / A conversion circuit. FIG. 4 is a timing chart for the cyclic A / D converter. FIG. 5 is a diagram illustrating polarity switching of a signal provided to a single comparator in a fully differential configuration. FIG. 6 is a diagram showing conversion characteristics of the D / A conversion circuit. FIG. 7 is a diagram showing connection of main circuit elements in each of the first sampling step and the second sampling step. FIG. 8 is a diagram showing connection of main circuit elements in each of the A / D conversion step and the third sampling step. FIG. 9 is a diagram illustrating an example of a comparator for the analog-digital converter according to the present embodiment. FIG. 10 is a diagram illustrating an example of a differential circuit and a latch circuit.

Explanation of symbols

T _S ... Sampling period, T _C ... Conversion period, 11 ... Analog to digital converter, 13 ... Analog input, 15 ... Gain stage, 17 ... A / D conversion circuit, 19 ... Logic circuit, 21 ... D / A conversion circuit , 23, operational amplifier circuit, 123, switching circuit, 131, comparator, 131 a, positive input of comparator, 131 b, negative input of comparator, 131 c, 131 d, first and second reference inputs, 133, storage circuit, 143 a, 143b, 143c, 143d ... switch, 145a, 145b, 145d ... D-type flip-flop circuit, 145c ... NOT circuit, 90 ... capacitor coupling circuit, 91 ... differential circuit, 92 ... latch circuit, 95, 97 ... coupling capacitor, 99a~99d ... _{switch, V REF1,} V _{REF2 ...} reference _{signal, V COMP1, V COMP2} ... comparison result, T _COMP1 ... first comparison period, T _COMP2 ... second comparison period

Claims (7)

A gain stage having an input connected to the analog input and first and second outputs, receiving the analog signal during the sampling period and converting the analog signal during the conversion period;
An A / D converter circuit having a pair of inputs for receiving signals from the first and second outputs of the gain stage and an output for providing a digital signal having a ternary digital value;
A logic circuit that generates a control signal in response to the digital signal from the A / D converter circuit;
A D / A conversion circuit for providing a predetermined voltage signal to the gain stage according to the control signal;
A switching circuit connected between the gain stage and the A / D conversion circuit,
The A / D conversion circuit includes:
A positive input and a negative input for receiving signals from the first and second outputs of the gain stage; and first and second reference inputs for receiving first and second reference signals, respectively. A comparator that generates a first comparison result in a first comparison period and a second comparison result in a second comparison period;
A storage circuit having an input connected to the output of the comparator and first and second outputs for providing the digital signal, and storing the first and second comparison results;
The switching circuit is connected between the first and second outputs of the gain stage and the positive and negative inputs of the comparator, and the first output and the second output of the gain stage. An output connected to the positive input and the negative input of the comparator, respectively, to generate the first comparison result, and the second output and the first output of the gain stage are respectively connected to the comparator An analog-to-digital converter, characterized in that a positive input and a negative input are connected to generate the second comparison result. A gain stage having an input connected to the analog input and first and second outputs, receiving the analog signal during the sampling period and converting the analog signal during the conversion period;
An A / D converter circuit having a pair of inputs for receiving signals from the first and second outputs of the gain stage and an output for providing a digital signal having a ternary digital value;
A logic circuit that generates a control signal in response to the digital signal from the A / D converter circuit;
A D / A conversion circuit that provides a predetermined voltage signal to the gain stage according to the control signal,
The A / D conversion circuit includes:
It has a positive input and a negative input for receiving signals from the first and second outputs of the gain stage, and first and second reference inputs, and the first comparison result is used as a first comparison period. And a comparator for generating the second comparison result in the second comparison period,
A switching circuit for switching the first and second reference signals to be provided to the first and second reference inputs;
A storage circuit having an input connected to an output of the comparator and first and second outputs for providing the digital signal, and storing the first and second comparison results;
The switching circuit has an input for receiving the first and second reference signals, an output for providing a switched signal, and a signal source of the first and second reference signals and the first and second Connected to the reference input of
The switching circuit provides the first and second reference signals to the first and second reference inputs of the comparator to generate the first comparison result, and the first and second reference signals An analog-to-digital converter, characterized in that a reference signal is provided to the second and first reference inputs of the comparator for generating the second comparison result.   The comparator includes: a differential circuit having a pair of inputs and a differential output; a first coupling capacitor having one end and the other end connected to one of the pair of inputs of the differential circuit; A second coupling capacitor having one end and the other end connected to the other of the pair of inputs of the differential circuit, and between the other end of the first coupling capacitor and the first reference input A first switch connected to the second coupling capacitor, and a second switch connected between the other end of the second coupling capacitor and the second reference input. 1. The analog-digital converter described in 1.   The comparator includes: a differential circuit having a pair of inputs and a differential output; a first coupling capacitor having one end and the other end connected to one of the pair of inputs of the differential circuit; A second coupling capacitor having one end and the other end connected to the other of the pair of inputs of the differential circuit, and connected between the other end of the first coupling capacitor and the positive input. 3. The method according to claim 2, further comprising: a third switch; and a fourth switch connected between the other end of the second coupling capacitor and the negative input. Analog to digital converter.   4. The comparator includes a latch circuit that receives each signal from the differential output of the differential circuit, and an output of the latch circuit is connected to the input of the storage circuit. The analog-digital converter as described in any one of -4.   The gain stage is connected to an operational amplifier circuit having a non-inverted output and an inverted output and an inverted input, and an input for receiving a signal for A / D conversion during the sampling period, and the operational amplification during the conversion period A capacitor connected to the inverting input of the circuit and another capacitor connected between the inverting input and the non-inverting output of the operational amplifier circuit during the conversion period. The analog-digital converter described in any one of 1-5. An image sensing semiconductor device,
An array comprising a plurality of sensing elements arranged in a plurality of rows and a plurality of columns, the array comprising column lines connected to the sensing elements in the columns;
A plurality of analog-digital converters for processing signals on the column lines, respectively, according to any one of claims 1 to 6,
2. The image sensing semiconductor device according to claim 1, wherein each of the analog-digital converters is connected to the column line.

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