JPH05244490A - Digital camera signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a video signal without a floated black level by having only to clamp an input signal portion through the addition and subtraction of same offset values. CONSTITUTION:An adder circuit 18 adds an offset set by a CPU 14 to a digital signal (data) from an A/D converter 16. The signal is clamped by subtracting a clamp level obtained at a clamp level calculation circuit 20 from an output of the adder circuit 18 by a 1st subtractor circuit 46. An output of the 1st subtractor circuit 46 is given to a zero clip circuit 48 for zero clip processing and the result is fed to a low pass filter 50 and to a 2nd subtractor circuit 52, in which the offset (the same as the sum by the adder circuit 18) set by the CPU 14 is subtracted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera signal processing circuit, and more particularly to a CCD using, for example, a mosaic type color filter or a stripe type color filter.
The present invention relates to a digital camera signal processing circuit for digitally processing an image pickup signal from a digital camera.

[0002]

2. Description of the Related Art Although a video camera using a CCD as an image pickup element has already been realized, the conventional camera is basically an analog signal processing camera. In the case of a CCD having a mosaic type color filter as shown in FIG.
An offset is added to the pixel signal for each pixel according to the type of color separation pulses SP1 and SP2 (FIG. 9). That is, the odd offset is added to each odd CCD output signal and the even offset is added to each even CCD output signal. Then, a luminance signal (Y) is obtained by adding CCD output signals of adjacent pixels, and two types of color signals (Cr and Cb) are obtained by subtracting the color signals (Cr and Cb) alternately every other line. Is output to.

Since the offset is added to the CCD output signal as described above, the color signals (Cr and Cb) are added.
The color signal generated from is different from the actual color. Therefore, in the conventional analog signal processing camera, after generating the color signals (Cr and Cb), the clamp circuit 1 removes the offset due to the influence of the color separation pulse, as shown in FIG.

Further, in the conventional analog signal processing camera, as shown in FIG. 7, a number of clamp circuits 2 to 5 are provided in order to eliminate variations in elements and potential variations due to temperature.
Is provided.

[0005]

In the digital signal processing camera to which the present invention is directed, if the analog signal processing circuit of FIG. 9 is directly replaced by the digital signal processing circuit, the gate scale occupied by the clamp circuits 1 to 5 becomes large. On the other hand, in the digital signal processing circuit, basically, since there is no offset variation during signal processing, it is only necessary to clamp at the input stage. However, when clamped only at the input stage, so-called "black float" occurs.

Therefore, the main object of the present invention is to
It is an object of the present invention to provide a digital camera signal processing circuit which does not cause black floating even if only two clamp circuits are provided.

[0007]

According to the present invention, an A / D conversion means for converting an output signal from a CCD into a digital signal, and a clamp level calculation for calculating a clamp level based on the digital signal from the A / D conversion means. Means, A /
First subtracting means for subtracting the clamp level from the digital signal from the D converting means, addition for adding a predetermined offset value to one of the digital signal from the A / D converting means and the clamped digital signal from the first subtracting means Means, clipping means for zero-clipping the digital signal to which the predetermined offset value has been added by the adding means, low-pass filter means for processing the digital signal from the clipping means, and subtraction of the predetermined offset value from the digital signal from the low-pass filter means Is a digital camera signal processing circuit including a second subtracting means for

[0008]

The output signal from the CCD from which the reset noise has been removed in the correlated double sampling circuit is adjusted to an appropriate amplitude by, for example, an automatic gain control circuit, and then A
It is converted into a digital signal by the / D conversion means. Based on this digital signal, for example, an average value (OB level) of the optical black in the output signal of the CCD is calculated for each line, and a clamp level is calculated from the average value by a recursive filter. The clamp level is obtained by the calculation means. This clamp level is the first from the digital signal from the A / D conversion means.
It is subtracted by the subtraction means and thus this digital signal is clamped. On the other hand, the adding means is provided between the A / D converting means and the first subtracting means or after the first subtracting means, and the adding means is clamped from the digital signal from the A / D converting means or the first subtracting means. A predetermined offset value is added to the digital signal. In that state, if the digital signal is zero clipped by the clipping means,
The negative component of random noise remains due to the offset.
Therefore, if the digital signal from the clipping means is given to the low-pass filter means, and then the same offset value added by the adding means by the second subtracting means is subtracted from the digital signal from the low-pass filter means, the optical black portion is almost zero. Therefore, black floating does not occur.

[0009]

According to the present invention, since only one clamp circuit needs to be provided after the A / D conversion means, the gate scale occupied by the clamp circuit is not so large, and therefore the conventional analog signal processing circuit can be used as it is. The circuit scale can be reduced as compared with the case of conversion to a digital signal processing circuit. In addition, after adding a predetermined offset value by the adding means, it is zero-clipped and passed through the low-pass filter means, and then the same offset value is added to the second value.
Since the subtraction means is used for subtraction, the optical black portion becomes almost zero level and black floating does not occur.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital camera 1 of this embodiment shown in FIG.
Reference numeral 0 includes an automatic gain control (AGC) circuit 12 which receives an output signal from a CCD (not shown) from which reset noise has been removed in a correlated double sampling circuit (not shown). This AGC circuit 12 is supplied from the CPU 14. For example PW
AGC based on the gain control signal given as the M signal
According to the AGC voltage from an AGC voltage generating circuit (not shown) that generates a voltage, the output signal from the CCD is given an optimum amplitude and given to the A / D converter 16. A / D converter 16
Then, the output signal from the CCD is converted into a digital signal, and this digital signal is given to the adding circuit 18 and the clamp level calculating circuit 20.

The adder circuit 18 adds the offset value given from the CPU 14 to the digital signal outputted from the A / D converter 16. This offset value is preferably set according to the magnitude of the gain set in the AGC circuit 12. For example, when the gain of the AGC circuit 12 is large, the offset value is increased, and when the gain is large, the offset value is decreased.

On the other hand, in brief, the clamp level calculating circuit 20 is an average value (“OB level”) of each line of the optical black portion (OB) in the OB level detecting area in the light shielding area shown in FIG. Is called) and the clamp level is calculated based on that. Specifically, the clamp level calculation circuit 20 is shown in FIG. Referring to FIG. 3, the clamp level calculation circuit 20 includes the A / D converter 1
A selection circuit 22 for receiving, for example, an 8-bit digital signal (input data) from 6 is included. The selection circuit 22 selects one of the input data (× 1) or one of the input data (× 2). And output to the adder circuit 24. Through the AND gate 26 to the adder circuit 24,
The data selected by the selection circuits 28, 30 and 32 is applied. The AND gate 26 is the signal VSET shown in FIG.
Controlled by. This signal VSET is O shown in FIG.
This signal is a low level only in each odd pixel and even pixel at the beginning of the B level detection area. In addition, the selection circuit 2
The signals 8 and 30 are controlled by the signal HSET shown in FIG. 4, and selectively output half (1/2) or one (1) of the supplied data. As shown in FIG. 4, this signal HSET is a signal that becomes low level for two odd and even pixels at the beginning of each line of the OB level detection area in FIG. The selection circuit 32 uses the signal ODD / EVEN.
The output of the selection circuit 28 is selected when the signal ODD / EVEN is at the high level, and the output of the selection circuit 30 is selected and output when the signal ODD / EVEN is at the low level. As shown in FIG. 4, the signal ODD / EVEN is a signal that becomes high level when the pixels are odd pixels of the CCD and becomes low level when the pixels are even pixels.

The output of the adder circuit 24 is given to the adder register 32. The addition register 32 includes an odd number register 34 and an even number register 36, and the data of the odd number pixel of the output of the addition circuit 24 is the odd number register 3
4 and the data of the even pixel is registered in the even register 36.
Given to. The outputs from the odd number register 34 and the even number register 36 are given to the two selection circuits 28 and 30 described above, respectively, and are also given to the odd number register 40 and the even number register 42 included in the clamp value register 38, respectively. .. The addition register 32 latches the output from the addition circuit 24, and the clamp value register 38 latches the output from the addition register 32. However, the outputs from the odd number register 34 and the even number register 36 of the addition register 32 are respectively 1/16 and latched in the odd number register 40 and the even number register 42 of the clamp value register 38, respectively.

The odd register 34 of the addition register 32 receives the signal CLKODD as a latch signal, and the even register 36 receives CLKEVENT as a latch signal.
As shown in FIG. 4, the signal CLKODD is a clock output for each odd pixel, and the signal CLKEVENT is a clock output for each even pixel. The signal CLKHD is applied to the odd register 40 and the even register 42 of the clamp value register 38 as a common latch timing signal. As shown in FIG. 4, the signal CLKHD is a signal which becomes high level only in one pixel at the right end shown in FIG. 2 for each line.

The output of the odd number register 40 and the output of the even number register 42 of the clamp value register 38 are given to the selection circuit 44. This selection circuit 44 is controlled by the signal ODD / EVEN like the above selection circuit 32, and outputs the output of the odd number register 40 when the signal ODD / EVEN is at the high level and the output of the even number register 42 when the signal is at the low level. Select and output.

In the clamp level calculation circuit 20 shown in FIG. 3, first, the OB level for eight pixels is calculated for odd-numbered pixels. Therefore, the selection circuit 22 is selected as “× 2” at the timing of the line to be clamped. Therefore, the input data is shifted up by 1 bit, and as a result, twice the input data is output from the selection circuit 22. At this time, the signal VSET which is the control input of the AND gate 26 becomes low level as shown in FIG.
The output of the adder circuit 24 is double the data of the first odd pixel output from the selection circuit 22. This double data is added to each register 34 and 36 of the addition register 32.
And is latched in the odd number register 34 in accordance with the signal CLKODD shown in FIG. The data latched in the odd number register 34 is applied to the selection circuit 28. The selection circuit 28 uses the low level signal HS shown in FIG.
The selection circuit 3 selects the data which is 1 times the input data according to ET.
Output to 2. Since the selection circuit 32 selects the upper input when the signal ODD / EVEN is at the high level and the lower input when the signal ODD / EVEN is at the low level, as a result, the selection circuit 32 is selected.
From, the data of the odd-numbered pixels from the selection circuit 28 is applied to the AND gate 26. That is, the data input to the AND gate 26 at this time is twice the data of the first odd pixel.

When the next data of the second odd-numbered pixel is input, the data doubled again is given to the adder circuit 24 from the selection circuit 22. At this time, since the signal VSET is at a high level, twice the data of the first odd pixel is supplied to the adder circuit 24 through the AND gate 26. Therefore, the adder circuit 24 adds the double data of the first odd pixel and the double data of the second odd pixel, and the addition result is latched in the odd register 34 of the addition register 32. Such an operation is thereafter repeated until the eighth odd pixel, and as a result, the odd register 3 of the addition register 32 is obtained.
In 4, the data obtained by multiplying the input data by 16 will be latched.

In response to the latch signal CLKHD (FIG. 4) which becomes high level at the right end (end) of the screen for each line,
The data latched in the odd number register 34 of the addition register 32 is 1/16, that is, 4-bit downshifted, and the odd number register 4 of the clamp value register 38 is added.
Latched to 0. Therefore, the selection circuit 44 responds to the high level of the signal ODD / EVEN and the OB level detection area latched in the odd number register 40 (FIG. 2).
The OB level data for the odd 8 pixels of the first one line is output.

In the subsequent lines, that is, in the second and subsequent lines, the selection circuit 22 selects "x1" and the selection circuit 28
As for 30 and 30, only "1/2" is selected for the first pixel and "1" is selected for the following 7 pixels. Therefore, the addition register 32 outputs 16 times the data again, and when it is “1/16”, the OB level for 8 pixels for each line is output from the selection circuit 44. That is, a circuit that passes from the adder circuit 24 through the adder register 32, the selection circuits 28, 30 and 32, and the AND gate 26 constitutes a cyclic filter. However, in this embodiment, the weighting coefficient (k) of the recursive filter is set to "1/2", but this coefficient can be arbitrarily set within the range of 0 <k <1. That is, by setting the coefficient (k), the clamp level of the first line remains the same value as the OB level, and the clamp levels of the second and subsequent lines are the coefficient of the clamp level of the previous line and the newly obtained OB level ( It is a weighted average of k). Therefore, even if noise is included in the OB portion of the second and subsequent lines, the influence of the noise on the image can be reduced by 1 / k.

Although only the operation of obtaining the OB level and the clamp level of the odd-numbered pixels has been described,
Also for the even-numbered pixels, the same operation as that for the odd-numbered pixels is performed except that the selection circuits 32 and 44 select the lower input by setting the signal ODD / EVEN to the low level. Omit it. In any case, the circuit of FIG. 3 calculates the clamp level for each odd or even pixel.

In this way, the clamp level calculation circuit 2
The clamp level is output from 0 and is input to the first subtraction circuit 46 shown in FIG. Therefore, the adder circuit 1
The clamp level calculated by the clamp level calculation circuit 20 is subtracted from the data to which the offset value is added in step 8 by the first subtraction circuit 46, and the digital signal from the A / D converter 16 is digitally clamped.

The output of the first subtraction circuit 46 is zero clipped by a zero clipping circuit 48 including, for example, an OR gate (a negative numerical value is forced to a zero level), and then,
The second subtraction circuit 5 through the digital low-pass filter 50
Given to 2. As the subtraction input of the second subtraction circuit 52, the same offset value as that given to the addition circuit 18 from the CPU 14 is given.

That is, referring to FIGS. 5 and 6, the case of this embodiment in which the offset value is added and subtracted by the adder circuit 18 and the second subtraction circuit 52 and the case of not using such an offset value will be described. Will be specifically described. 5A and 6A are both 1-line CCD output signals (digital signals) output from the A / D converter 16 when a subject whose left side is black and whose right side is white are photographed. Is. Since the actual signal contains random noise, it has a waveform as shown in FIG. 5 (A) or FIG. 6 (A). At this time, the clamp level is the level shown by the dotted line, and the first subtraction circuit 46 clamps at this level.

When the offset value is not added, the output of the zero clip circuit 48 becomes a signal as shown in FIG. 5 (B). When this signal passes through the low-pass filter 50, FIG.
The waveform becomes as shown in (C), and the signal in the portion that should be black does not become zero, so a phenomenon called "black floating" occurs. However, when the offset value is added by the adder circuit 18 according to this embodiment, the zero clip circuit 48 is added.
Output signal has a waveform shown in FIG. When this is processed by the low-pass filter 50, the waveform shown in FIG. 6C is obtained, and thereafter, the offset value is subtracted by the second subtraction circuit 52, so that the signal of the optical black portion is obtained as shown in FIG. 6D. Is almost zero, and an image signal without "blackening" can be obtained.

As described above, this offset value is changed according to the gain of the AGC circuit 12. That is,
When the gain is large, the noise also becomes large, so the offset value is increased to prevent black floating, and when the gain is small, the noise is small, so the offset value is made small to increase the signal dynamic range. In the above-described embodiment, the case where the CCD (not shown) has a mosaic type color filter has been described. However, the present invention can also be applied to the case of processing an output signal from a CCD having a stripe type color filter. However, in this case, the clamp level calculation circuit 20 shown in FIG. 1 is replaced with that shown in FIG.

That is, the clamp level calculating circuit 20 'shown in FIG. 7 is the clamp level calculating circuit 20 shown in FIG.
Similarly, includes a selection circuit 22, an addition circuit 24, an AND gate 26, an addition register 32, selection circuits 28 ', 29 and 30', a selection circuit 32 ', a clamp value register 38 and a selection circuit 44'. Selection circuits 32 'and 44'
Is a signal (color separation pulse) SELAB that becomes a high level for each pixel of a stripe type color filter (not shown).
Controlled by C, if the signal SELABC is at the high level at the first pixel, the selection circuits 32 'and 44' select the upper input, and when the signal SELABC is at the high level at the timing of the second pixel, the selection circuit 32 '. Selects the middle input, and when the signal SELABC is at the high level at the timing of the third pixel, the selection circuits 32 'and 44' select the lower input. Other operations can be easily understood from the operation of FIG. 3 described above, and thus detailed description thereof will not be repeated here. In any case, the circuit of FIG. 7 calculates the clamp level corresponding to each pixel every three pixels.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an illustrative view showing an OB level detection area for calculating a clamp level in the embodiment of FIG.

FIG. 3 is a block diagram showing an example of a clamp level calculation circuit in the embodiment of FIG.

FIG. 4 is a timing diagram showing an operation of the clamp level calculation circuit of FIG.

FIG. 5 is a waveform diagram showing a comparative example in the case where the offset value is added and not subtracted in the embodiment of FIG.

FIG. 6 is a waveform chart showing the operation of the embodiment in FIG.

FIG. 7 is a block diagram showing in detail a clamp level calculation circuit when a CCD of a stripe type color filter is used in the embodiment of FIG.

FIG. 8 is an illustrative view showing an array of mosaic color filters.

FIG. 9 is a block diagram showing an example of a conventional analog signal processing circuit.

[Explanation of symbols]

 10 ... Digital signal processing camera 12 ... AGC circuit 14 ... CPU 16 ... A / D converter 18 ... Addition circuit 20, 20 '... Clamp level calculation circuit 46 ... First subtraction circuit 48 ... Zero clip circuit 50 ... Low-pass filter 52 ... Second subtraction circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Asaeda, 2-18 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. Electric Co., Ltd.

Claims (5)

[Claims] 1. An A / D conversion means for converting an output signal from a CCD into a digital signal, a clamp level calculation means for calculating a clamp level based on the digital signal from the A / D conversion means, and the A / D conversion. First subtracting means for subtracting the clamp level from the digital signal from the means, adding a predetermined offset value to one of the digital signal from the A / D converting means and the clamped digital signal from the first subtracting means Adding means, clipping means for zero-clipping the digital signal to which the predetermined offset value has been added by the adding means, low-pass filter means for processing the digital signal from the clipping means, and digital signal from the low-pass filter means The second subtraction means for subtracting the predetermined offset value Obtaining a digital camera signal processing circuit. 2. An automatic gain control means for receiving an output signal from the CCD and giving the output to the A / D conversion means, and a means for giving a gain control signal to the automatic gain control means, the predetermined gain control means. 2. The digital camera signal processing circuit according to claim 1, wherein the offset value is set according to the gain of the automatic gain control means controlled by the gain control signal. 3. The clamp level calculating means obtains, for each line, an average value means for calculating an average value of an optical black portion included in an output signal from the CCD, and for each line, obtains from the average value means. 3. The digital camera signal processing circuit according to claim 1, further comprising a recursive filter means for calculating the clamp level based on the average value of the optical black portion. 4. The CCD includes a mosaic type color filter, the clamp level calculating means calculates a clamp level for each of an odd pixel and an even pixel, and the first
4. The subtraction means subtracts the odd pixel clamp level from the odd pixel digital signal from the A / D conversion means and subtracts the even pixel clamp level from the even pixel digital signal. Digital camera signal processing circuit. 5. The CCD includes a stripe type color filter, the clamp level calculation means calculates a clamp level corresponding to each pixel for every three pixels, and the first subtraction means is the A / D conversion means. 4. The digital camera signal processing circuit according to claim 1, wherein the clamp level corresponding to each pixel is subtracted from the digital signal of each pixel from.