JP4437940B2 - Television camera - Google Patents

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JP4437940B2
JP4437940B2 JP2004150041A JP2004150041A JP4437940B2 JP 4437940 B2 JP4437940 B2 JP 4437940B2 JP 2004150041 A JP2004150041 A JP 2004150041A JP 2004150041 A JP2004150041 A JP 2004150041A JP 4437940 B2 JP4437940 B2 JP 4437940B2
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multiplier
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television camera
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JP2005333424A (en
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昭宏 加藤
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Hitachi Kokusai Electric Inc
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本発明はテレビジョンカメラに関し、特にCCD蓄積補間処理と巡回型ノイズ低減処理の改良に関するものである。   The present invention relates to a television camera, and more particularly to improvements in CCD accumulation interpolation processing and cyclic noise reduction processing.

従来、テレビジョンカメラで映像拡大するための電子ズーム処理を実現する場合、CCD撮像素子の出力映像を、サンプル&ホールド処理(CDS)や自動利得調整(AGC)などのアナログ処理と、アナログ信号のデジタル変換(A/D)処理と、ガンマ補正や輪郭補正などのデジタル処理(DSP)を施した上で、一旦フィールドメモリに全撮像エリアの映像信号を記録し、2フィールド(1フレーム)後に所望の映像データの一部を切り出して、画素の引き伸ばし処理と、隣接画素間の補間処理を行うことで、電気的に映像を拡大する。   Conventionally, when an electronic zoom process for enlarging an image with a television camera is realized, the output image of the CCD image sensor is subjected to analog processing such as sample & hold processing (CDS) and automatic gain adjustment (AGC), and analog signal processing. After digital conversion (A / D) processing and digital processing (DSP) such as gamma correction and contour correction, video signals of all imaging areas are once recorded in the field memory, and desired after 2 fields (1 frame) A portion of the video data is cut out, and the video is electrically enlarged by performing pixel enlargement processing and interpolation processing between adjacent pixels.

また、蓄積補間処理については、CCD撮像素子の露光時間を長くすることにより増倍された信号電荷を取り出し、その映像信号をフィールドメモリに記録しておき、露光中の映像欠落フィールド期間についてはフィールドメモリに記録しておいた数フィールド前の映像信号データを読み出すことで、連続した高感度の映像信号を得る。   As for the accumulation interpolation processing, the signal charge multiplied by increasing the exposure time of the CCD image sensor is taken out, the video signal is recorded in the field memory, and the field for the video missing field period during exposure is recorded. By reading out video signal data several fields before recorded in the memory, continuous high-sensitivity video signals are obtained.

また、巡回型ノイズ低減処理については、A/D変換後の映像信号と1フィールド前の映像信号とをある一定比率で加算することにより、フィールド間の相関が高い映像信号成分にはあまり影響を与えず、フィールド毎にレベルが絶えず変動するノイズ成分は平均化されて小さくなることを利用して、ノイズ低減を行う。
ここで、これらの3つの機能を同時に実現しようとした場合、蓄積補間処理と巡回型ノイズ低減処理はデジタル信号処理(DSP)の前で行い、電子ズーム処理はDSPの後で行うのが一般的である。理由としては、デジタル信号処理でガンマ補正や輪郭補正を行う際にノイズ成分が多く含まれているとノイズ成分を余計に強調してしまうためDSPの前でノイズ低減処理する必要があることと、電子ズーム処理を蓄積補間処理の前で行うとフィールド欠落期間はズーム倍率を変化させることができず、倍率変化の追従が遅くなるからである。
In addition, with regard to the cyclic noise reduction processing, by adding the video signal after A / D conversion and the video signal of one field before at a certain ratio, the video signal component having a high correlation between fields is not greatly affected. The noise is reduced by using the fact that the noise component whose level constantly fluctuates for each field is averaged and becomes smaller.
Here, when these three functions are to be realized at the same time, the accumulation interpolation processing and the cyclic noise reduction processing are generally performed before the digital signal processing (DSP), and the electronic zoom processing is generally performed after the DSP. It is. The reason is that if a large amount of noise components are included when performing gamma correction or contour correction in digital signal processing, the noise components will be excessively emphasized, so that it is necessary to perform noise reduction processing before the DSP, This is because if the electronic zoom processing is performed before the accumulation interpolation processing, the zoom magnification cannot be changed during the field missing period, and the tracking of the magnification change is delayed.

なお、単板テレビジョンカメラで電子ズーム機能と蓄積感度増加機能を併用する例が、特許文献1に開示されている。
特開2000−287124号公報
An example in which an electronic zoom function and a storage sensitivity increasing function are used together in a single-panel television camera is disclosed in Patent Document 1.
JP 2000-287124 A

上述の従来技術は、蓄積補間処理と巡回型ノイズ低減処理を行う回路と電子ズーム処理を行う回路とはDSPを挟んで離れた場所にあるため、フィールドメモリとその制御回路が各々必要になり、回路規模や部品コストが増加してしまう。また、DSPで自動利得調整やレンズアイリス制御のための映像レベル検出を行う場合、DSPの検出エリアとその後の電子ズームにより拡大されたエリアとで差が生じるため、たとえば撮影エリアの中心が暗く、隅に明るい被写体が入っているような場合、DSPは隅の明るい被写体でレベルを合わせてしまい、電子ズームでカメラの画角が変化しても自動利得調整やレンズアイリス制御が動作せず、映像の明るさが変化しないといった問題が生じる。   In the above-described conventional technology, the circuit for performing the accumulation interpolation process and the cyclic noise reduction process and the circuit for performing the electronic zoom process are located apart from each other with the DSP interposed therebetween, so that a field memory and its control circuit are required, respectively. The circuit scale and parts cost will increase. Also, when video level detection for automatic gain adjustment or lens iris control is performed by the DSP, a difference occurs between the detection area of the DSP and the area enlarged by the subsequent electronic zoom, so the center of the shooting area is dark, for example. When there is a bright subject in the corner, the DSP adjusts the level of the bright subject and the automatic gain adjustment and lens iris control do not operate even if the camera angle of view changes with electronic zoom. The problem that the brightness of the camera does not change occurs.

本発明の目的は、上記の問題を解決するため、蓄積感度増加時の映像データ補間とノイズ低減および映像拡大の機能を独立に制御でき、省スペースで低コストのテレビジョンカメラを実現することにある。   An object of the present invention is to realize a space-saving and low-cost television camera that can independently control video data interpolation, noise reduction, and video enlargement functions when the storage sensitivity is increased, in order to solve the above-described problems. is there.

上記の目的を達成するために本発明のテレビジョンカメラは、撮影された映像信号の一部分を電気的に切り出して拡大処理する電子ズーム処理と、CCD撮像素子で長時間露光蓄積された間欠映像信号をメモリで補間して連続した映像を得る蓄積補間処理と、CCD撮像素子の出力映像と1フィールド前の映像とを加算する巡回型ノイズ低減処理とを行うものである。   In order to achieve the above object, the television camera of the present invention includes an electronic zoom process for electrically extracting and enlarging a part of a photographed video signal, and an intermittent video signal accumulated for a long time by a CCD image sensor. Are interpolated in the memory to obtain a continuous image, and a cyclic noise reduction process for adding the output image of the CCD image sensor and the image one field before is performed.

また、本発明は、蓄積感度増加とノイズ低減および画像拡大を行うテレビジョンカメラにおいて、映像データを格納するメモリと演算器とを具備し、前記蓄積感度増加時の映像データ補間と前記ノイズ低減および前記画像拡大は、前記メモリの読出し制御と前記演算器で行うものである。   In addition, the present invention provides a television camera that performs accumulation sensitivity increase, noise reduction, and image enlargement, and includes a memory for storing video data and a computing unit, and interpolates video data when the storage sensitivity increases, reduces noise, and The image enlargement is performed by the memory read control and the arithmetic unit.

さらに、本発明は、入射光を1フィールド以上露光して映像信号を出力する撮像素子と該映像信号をデジタルデータに変換するデジタル変換器と該デジタルデータと第1または第2のデータとを乗算する第1の乗算器と、該第1の乗算器の出力データと第3のデータとを加算する加算器と、該加算器の出力データを記録するメモリと、該メモリから記録されてから2フィールド遅延されたデータを第4または第5のデータと乗算して前記第3のデータを出力する第2の乗算器とを少なくとも備え、前記メモリから記録されてから1フィールド遅延されたデータを映像信号とするものである。   Furthermore, the present invention multiplies the imaging device that outputs video signals by exposing incident light to one or more fields, a digital converter that converts the video signals into digital data, and the digital data and the first or second data. A first multiplier, an adder for adding the output data of the first multiplier and the third data, a memory for recording the output data of the adder, and 2 after being recorded from the memory At least a second multiplier that multiplies the field-delayed data with the fourth or fifth data and outputs the third data, and records the data delayed from the memory by one field after being recorded from the memory It is a signal.

本発明によれば、DSPの前に配置された一組のメモリとメモリ制御回路および乗算器と加算器を用いて、蓄積補間処理と巡回型ノイズ低減処理と電子ズーム処理を実現するのに必要な回路の大部分を共用化することで、省スペースで低コストなテレビジョンカメラが実現でき、さらに上記の3つの処理を独立に制御できるため8通りすべての組み合わせで使用することが可能である。   According to the present invention, it is necessary to realize accumulation interpolation processing, cyclic noise reduction processing, and electronic zoom processing using a set of memory, a memory control circuit, a multiplier, and an adder arranged in front of the DSP. By sharing most of the circuits, a space-saving and low-cost television camera can be realized. Furthermore, the above three processes can be controlled independently, so that all eight combinations can be used. .

以下、本発明によるテレビジョンカメラの一実施例の動作について図1を用いて説明する。図1は本発明の一実施例を示すテレビジョンカメラのブロック図である。
図1において、1は図示していない入射光を赤(R)と緑(G)と青(B)の3原色光に分解する色分解プリズム、2a〜2cは光電変換して得られた電荷を順次転送して映像信号を出力する撮像素子(CCD)、3a〜3cはCCD2a〜2cの映像信号出力をサンプル&ホールドし、所定のレベルになるよう増幅する自動利得制御回路(CDS&AGC)、4a〜4cはアナログ映像信号をデジタル信号に変換するアナログーデジタル変換器(A/D)、5a〜5fは乗算器、6a〜6cは加算器、7はフィールドメモリ、8はメモリ制御回路で、入力ポート8aと蓄積補間回路と巡回型ノイズ低減回路とで共用する出力ポート8bと電子ズーム専用の出力ポート8cから構成される。9は電子ズームにより引き伸ばされた画素と画素との間を、隣接する画素データの混合により補間して滑らかに見せるズーム補間回路、10はガンマ補正や輪郭補正や色調補正など画質向上のための各種のデジタル信号処理を行うDSP、11a〜11bはDSP10によりR,G,B信号からエンコードされた輝度信号(Y)と色信号(C)をアナログ信号に変換するデジタルーアナログ変換器(D/A)、12は輝度信号と色信号を多重してカラー映像信号にする加算器、13はカラー映像信号をモニタ(図示せず)に接続するための接続端子、14はCCD2a〜2cの蓄積および読出し用タイミング信号を生成するCCD駆動信号発生器、15はテレビジョンカメラの垂直同期信号をカウントしてCCD駆動信号発生器14の基準信号を作り、さらにその基準信号に同期して乗算器5a〜5fの係数を切り替えるフィールドカウンタ、16は所定の蓄積時間や電子ズーム倍率になるようにフィールドカウンタ15やメモリ制御回路8にデータを設定するマイクロコンピュータ(CPU)である。
The operation of one embodiment of the television camera according to the present invention will be described below with reference to FIG. FIG. 1 is a block diagram of a television camera showing an embodiment of the present invention.
In FIG. 1, 1 is a color separation prism that decomposes incident light (not shown) into three primary color lights of red (R), green (G), and blue (B), and 2a to 2c are electric charges obtained by photoelectric conversion. Image pickup devices (CCD) 3a to 3c for sequentially transferring the video signals and outputting the video signals. The automatic gain control circuits (CDS & AGC) 4a for sampling and holding the video signal outputs of the CCDs 2a to 2c and amplifying them to a predetermined level -4c are analog-to-digital converters (A / D) for converting analog video signals to digital signals, 5a-5f are multipliers, 6a-6c are adders, 7 is a field memory, 8 is a memory control circuit, and inputs The output port 8b is shared by the port 8a, the accumulation interpolation circuit, and the cyclic noise reduction circuit, and the output port 8c is dedicated for electronic zoom. Reference numeral 9 denotes a zoom interpolation circuit that smoothly interpolates between pixels expanded by electronic zoom by mixing adjacent pixel data, and 10 denotes various types for improving image quality such as gamma correction, contour correction, and tone correction. DSPs 11a to 11b that perform digital signal processing of the digital-analog converter (D / A) that converts the luminance signal (Y) and color signal (C) encoded from the R, G, and B signals by the DSP 10 into analog signals. ), 12 is an adder that multiplexes the luminance signal and the color signal into a color video signal, 13 is a connection terminal for connecting the color video signal to a monitor (not shown), and 14 is an accumulation and readout of the CCDs 2a to 2c. A CCD drive signal generator 15 for generating a timing signal for the camera, and 15 is a reference signal of the CCD drive signal generator 14 by counting the vertical synchronization signal of the television camera. The field counter 16 switches the coefficients of the multipliers 5a to 5f in synchronization with the reference signal, and 16 sets data in the field counter 15 and the memory control circuit 8 so as to have a predetermined accumulation time and electronic zoom magnification. It is a microcomputer (CPU).

次に、4フィールド期間蓄積した場合の蓄積補間処理について説明する。CCD駆動信号発生器14の駆動パルスにより、4フィールドに1回、通常の4倍に増感された映像信号がCCD2a〜2cから読み出され、CDS&AGC3a〜3cおよびA/D4a〜4cを経て、乗算器5a〜5cに入力される。ここではCCD駆動信号に同期して、A/D4a〜4c出力側に繋がる乗算器5a〜5cとメモリ出力ポート8bに繋がる乗算器5d〜5fの係数が変化し、次段の加算器6a〜6cとの組み合わせでセレクタを構成している。セレクタを使用しないのは次に説明する巡回型ノイズ低減回路との共用化を図るためである。図2にA/D4a〜4c出力から画素補間を行うズーム補間回路9の入力までのタイミングチャートを示す。横軸は垂直同期信号(フィールド)単位の経過時間を表している。A/D4a〜4cに映像が出力されるタイミングに合わせて、乗算器5a〜5cの係数は1倍に、乗算器5d〜5fの係数は0倍に設定され、映像が欠落している蓄積期間はそれぞれ0倍と1倍に設定される。したがって、加算器6a〜6cの出力には、CCDの映像出力期間はA/D4a〜4cの出力データが出力され、CCDの蓄積期間はメモリ8bの出力データが出力される。ここで、メモリ出力ポート8bでは、メモリ入力ポート8aからフィールドメモリ7に書き込まれたデータを1フィールド後に読み出しているため、加算器6a〜6cの出力には、CCD2a〜2cの映像出力期間のデータで蓄積中の映像欠落期間が補間され、同じフィールドの映像が4フィールド連続することになる。もう一方のメモリ出力ポート8cでは、メモリ7のデータを2フィールド後に読み出しているため、補間されたデータが2フィールド遅延されて出力される。2フィールド後に読み出す理由はCCDがインターレース走査のため、CCD2a〜2cの走査フィールドとフィールドメモリ7の読み出しフィールドを合わせる必要があるためである。図中の矢印は、実線がフィールドメモリ7を介したデータ移動を、破線が乗算器5a〜5fと加算器6a〜6cを介したデータ移動を表している。   Next, the accumulation interpolation process when accumulating for four field periods will be described. The video signal, which is sensitized four times as usual, is read out from the CCDs 2a to 2c once every four fields by the drive pulse of the CCD drive signal generator 14, and is multiplied through the CDS & AGCs 3a to 3c and A / D 4a to 4c. Input to the devices 5a to 5c. Here, in synchronization with the CCD drive signal, the coefficients of the multipliers 5a to 5c connected to the output side of the A / D 4a to 4c and the multipliers 5d to 5f connected to the memory output port 8b change, and the adders 6a to 6c in the next stage change. The selector is composed of a combination with. The reason for not using the selector is to share it with the cyclic noise reduction circuit described below. FIG. 2 shows a timing chart from the A / D 4a to 4c output to the input of the zoom interpolation circuit 9 that performs pixel interpolation. The horizontal axis represents the elapsed time in units of vertical synchronization signals (fields). In accordance with the timing at which video is output to the A / Ds 4a to 4c, the coefficients of the multipliers 5a to 5c are set to 1 times, the coefficients of the multipliers 5d to 5f are set to 0 times, and the accumulation period in which the video is missing Are set to 0 and 1 respectively. Accordingly, the output data of the A / D 4a to 4c is output during the video output period of the CCD and the output data of the memory 8b is output during the accumulation period of the CCD. Here, in the memory output port 8b, the data written to the field memory 7 from the memory input port 8a is read one field later, so that the output of the adders 6a to 6c includes the data of the video output period of the CCDs 2a to 2c. Thus, the video missing period being accumulated is interpolated, and the video of the same field is continuous for four fields. In the other memory output port 8c, since the data in the memory 7 is read out after two fields, the interpolated data is delayed by two fields and output. The reason for reading after two fields is that the CCD is interlaced, so the scanning fields of the CCDs 2a to 2c and the reading field of the field memory 7 must be matched. In the arrows in the figure, the solid line represents data movement through the field memory 7, and the broken line represents data movement through the multipliers 5a to 5f and the adders 6a to 6c.

次に、この蓄積補間処理に巡回型ノイズ低減処理を併用した場合について説明する。図3は蓄積フィールド数が4、巡回係数が0.5の場合のタイミングチャートである。A/D4a〜4cに映像が出力されるタイミングに合わせて、乗算器5a〜5cの係数は0.5倍に、乗算器5d〜5fの係数は0.5倍に設定され、映像が欠落している蓄積期間はそれぞれ0倍と1倍に設定される。したがって、加算器6a〜6cの出力ではA/D4a〜4cの出力とフィールドメモリ7の出力データの加算平均データで補間された映像が4フィールド連続することになる。フィールド間で加算平均されるため、フィールド間の相関が高い映像信号には影響を与えずに、ランダムに変化するノイズのみ低減することができる。巡回係数は乗算器5d〜5f側の比率が高いほど多くのフィールドに渡ってデータを加算していくことになるため、高いノイズ低減効果が得られる。   Next, a case where a cyclic noise reduction process is used in combination with this accumulation interpolation process will be described. FIG. 3 is a timing chart when the number of accumulated fields is 4 and the cyclic coefficient is 0.5. The coefficients of the multipliers 5a to 5c are set to 0.5 times and the coefficients of the multipliers 5d to 5f are set to 0.5 times in accordance with the timing when the images are output to the A / Ds 4a to 4c. The accumulation periods are set to 0 times and 1 time, respectively. Therefore, at the outputs of the adders 6a to 6c, the video interpolated with the addition average data of the outputs of the A / Ds 4a to 4c and the output data of the field memory 7 is continuous for four fields. Since addition averaging is performed between fields, only randomly changing noise can be reduced without affecting a video signal having a high correlation between fields. As the cyclic coefficient has a higher ratio on the multipliers 5d to 5f side, data is added over more fields, so that a higher noise reduction effect is obtained.

次に、蓄積補間処理と巡回型ノイズ低減処理に加え、電子ズーム処理を併用した場合について図4のタイミングチャートを用いて説明する。メモリ入力ポート8aまでの信号経路は前述と同じであるが、メモリ出力ポート8cの出力には、メモリに記録された加算器6a〜6cの出力データを部分的に切り出して読み出したズームデータが出力される。図4のメモリ出力ポート8cの信号波形は、加算器6a〜6c出力波形の中央部を部分的に切り出して映像拡大したものである。メモリ入力ポート8aでは撮像エリアの水平走査をフィールドメモリのアドレス空間の行に対応させ、垂直走査をメモリのアドレス空間の列に対応させて、順番にメモリに記録しているため、例えば同じ行アドレスと列アドレスを2回連続して読み出せば2倍ズームしたことになる。また、全撮影エリアをメモリに記録しているため、読み出しアドレス範囲を変えれば、撮影エリアの中心だけでなく、任意のエリアをズームアップすることも可能である。また、ズーム倍率を1倍に設定した場合は、蓄積補間処理と巡回型ノイズ低減処理の組み合わせと同じであることは言うまでもない。   Next, the case where the electronic zoom process is used in addition to the accumulation interpolation process and the cyclic noise reduction process will be described with reference to the timing chart of FIG. The signal path to the memory input port 8a is the same as described above, but zoom data obtained by partially cutting out and reading out the output data of the adders 6a to 6c recorded in the memory is output to the output of the memory output port 8c. Is done. The signal waveform of the memory output port 8c in FIG. 4 is obtained by partially cutting out the central portion of the output waveform of the adders 6a to 6c and enlarging the video. In the memory input port 8a, horizontal scanning of the imaging area is associated with a row in the address space of the field memory, and vertical scanning is associated with a column in the address space of the memory and recorded in order in the memory. If the column address is read twice in succession, the zoom is doubled. Further, since all the shooting areas are recorded in the memory, it is possible to zoom in not only on the center of the shooting area but also on any area by changing the read address range. Needless to say, when the zoom magnification is set to 1, it is the same as the combination of the accumulation interpolation process and the cyclic noise reduction process.

以上本発明について詳細に説明したが、本発明は、ここに記載された3板方式テレビジョンカメラに限定されるものではなく、上記以外の単板方式、複数板方式、撮像管方式等の撮像方式に広く適用することができることは言うまでもない。   Although the present invention has been described in detail above, the present invention is not limited to the three-plate system television camera described herein, and imaging other than the above-described single-plate system, multiple-plate system, imaging tube system, etc. Needless to say, it can be widely applied to the method.

本発明の一実施例を示すテレビジョンカメラのブロック図。The block diagram of the television camera which shows one Example of this invention. 本発明の一実施例の蓄積補間処理の動作を説明するためのタイミングチャート。The timing chart for demonstrating the operation | movement of the accumulation | storage interpolation process of one Example of this invention. 本発明の一実施例の蓄積補間処理と巡回型ノイズ低減処理を併用した場合の動作を説明するためのタイミングチャート。The timing chart for demonstrating operation | movement at the time of using together the accumulation | storage interpolation process and cyclic | annular noise reduction process of one Example of this invention. 本発明の一実施例の蓄積補間処理と巡回型ノイズ低減処理と電子ズーム処理を併用した場合の動作を説明するためのタイミングチャート。The timing chart for demonstrating the operation | movement at the time of using together the accumulation interpolation process of one Example of this invention, a cyclic | annular noise reduction process, and an electronic zoom process.

符号の説明Explanation of symbols

1:色分解プリズム、2a〜2c:CCD、3a〜3c:CDS&AGC、4a〜4c:A/D、5a〜5f:乗算器、6a〜6c:加算器、7:フィールドメモリ、8:メモリ制御回路、8a:メモリ入力ポート、8b,8c:メモリ出力ポート、9:ズーム補間回路、10:DSP、11a,11b:D/A、12:加算器、13:接続端子、14:CCD駆動信号発生器、15:フィールドカウンタ、16:CPU。

1: Color separation prism, 2a-2c: CCD, 3a-3c: CDS & AGC, 4a-4c: A / D, 5a-5f: Multiplier, 6a-6c: Adder, 7: Field memory, 8: Memory control circuit 8a: memory input port, 8b, 8c: memory output port, 9: zoom interpolation circuit, 10: DSP, 11a, 11b: D / A, 12: adder, 13: connection terminal, 14: CCD drive signal generator , 15: field counter, 16: CPU.

Claims (1)

蓄積感度増加とノイズ低減および画像拡大を行うテレビジョンカメラにおいて、入射光を1フィールド以上露光して映像信号を出力する撮像素子と該映像信号をデジタルデータに変換するデジタル変換器と乗算器の乗算係数(0から1の値)を変化させて、乗算係数を該デジタルデータ乗算する第1の乗算器と、該第1の乗算器の出力データと第3のデータとを加算する加算器と、該加算器の出力データを記録するメモリと、該メモリ記録されてからフィールド遅延されたデータを1から第1の乗算器の乗算係数(0から1の値)を引いた値と乗算して前記第3のデータを出力する第2の乗算器とを少なくとも備え、前記メモリ記録されてからフィールド遅延されたデータを映像信号とし、前記蓄積感度増加時の映像データ補間と前記ノイズ低減および前記画像拡大は、前記メモリの読出し制御と前記演算器で行うことを特徴とするテレビジョンカメラ。 In a television camera that increases storage sensitivity, reduces noise, and enlarges an image, an image sensor that exposes incident light for one or more fields and outputs a video signal, a digital converter that converts the video signal to digital data, and a multiplier by changing the coefficients (value between 0 and 1), a first multiplier for multiplying the multiplication coefficient to the digital data, an adder for adding the output data and the third data of the first multiplier a memory for recording the output data of the adder, a value obtained by subtracting a multiplication factor (value between 0 and 1) of the first multiplier from 1 to 1 field delayed data from being recorded in the memory multiplier and comprises at least a second multiplier for outputting the third data, said recorded in the memory as a video signal to two-field delay data from the video data interpolation at the time of increasing the accumulation sensitivity Serial noise reduction and the image enlargement, television camera and performing by said arithmetic unit and read control of the memory.
JP2004150041A 2004-05-20 2004-05-20 Television camera Expired - Fee Related JP4437940B2 (en)

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