JPS622778Y2 - - Google Patents
Info
- Publication number
- JPS622778Y2 JPS622778Y2 JP17561682U JP17561682U JPS622778Y2 JP S622778 Y2 JPS622778 Y2 JP S622778Y2 JP 17561682 U JP17561682 U JP 17561682U JP 17561682 U JP17561682 U JP 17561682U JP S622778 Y2 JPS622778 Y2 JP S622778Y2
- Authority
- JP
- Japan
- Prior art keywords
- sealing layer
- thermal expansion
- substrate
- synthetic resin
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007789 sealing Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 19
- 239000000919 ceramic Substances 0.000 claims description 12
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 10
- 229910010272 inorganic material Inorganic materials 0.000 claims description 9
- 239000011147 inorganic material Substances 0.000 claims description 9
- 229920003002 synthetic resin Polymers 0.000 claims description 8
- 239000000057 synthetic resin Substances 0.000 claims description 8
- 239000003463 adsorbent Substances 0.000 claims description 4
- 239000000843 powder Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 description 9
- 239000011347 resin Substances 0.000 description 9
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229920002050 silicone resin Polymers 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229920002545 silicone oil Polymers 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【考案の詳細な説明】
本考案は、IC、トランジスタチツプをリード
線でセラミツク基板の接続端子に接続する式の防
湿処置が施された混成集積回路に関する。[Detailed Description of the Invention] The present invention relates to a moisture-proof hybrid integrated circuit in which an IC or transistor chip is connected to a connection terminal of a ceramic substrate by a lead wire.
従来の混成集積回路は、第１図示のように、配
線基板ａ上に搭載したIC等のリード線接続部品
ｂ及びリード線ｃを軟質シリコン樹脂又は硬質エ
ポキシ樹脂ｄで被覆して封止し、更に配線基板ａ
全体を別の樹脂ｅで被覆して形成されていた。し
かしながら、軟質シリコン樹脂は材料自体の熱膨
張係数が大きいため、急激な温度変化が連続的に
加わつた場合リード線が切断されたり、外装モー
ルド樹脂ｅとの接着性が弱く温度変化により外装
モールドがひび割れする等の不都合があつた。ま
た、エポキシ樹脂は、これとセラミツク基板の熱
膨張係数の差を補う弾力性が無いため、温度変化
の繰返しによりリード線ｃが切断する等の保都合
が存した。 In a conventional hybrid integrated circuit, as shown in the first diagram, lead wire connecting parts b such as ICs mounted on a wiring board a and lead wires c are coated and sealed with a soft silicone resin or a hard epoxy resin d. Furthermore, wiring board a
It was formed by covering the entire body with another resin e. However, since the material itself of soft silicone resin has a large coefficient of thermal expansion, the lead wires may break if sudden temperature changes are applied continuously, and the adhesiveness with the exterior mold resin e is weak and the exterior mold may be damaged due to temperature changes. There were some inconveniences such as cracking. Furthermore, since the epoxy resin does not have the elasticity to compensate for the difference in coefficient of thermal expansion between the epoxy resin and the ceramic substrate, there are disadvantages such as the lead wire c breaking due to repeated temperature changes.
本考案はかかる不都合の無い混成集積回路を提
供することをその目的としたもので、セラミツク
基板１上に配設されたリード線接続部品２及びリ
ード線３が無機質材料を含有する通気孔構造の合
成樹脂から成る第１封止層４と吸着剤粉末及び無
機質材料を含有する無気孔構造の合成樹脂から成
る第２封止層５とで順次被覆され、更に、その他
の部品６を搭載した基板全体が防湿性合成樹脂か
ら成る外装モールド７で被覆され、前記基板１、
第１封止層４、第２封止層５及び外装モールド７
各部の熱膨張係数は、前記基板１から順次増大す
るように選定され、隣接する各部の熱膨張係数の
間に大きな差がないようにされてなる。 The purpose of the present invention is to provide a hybrid integrated circuit free from such inconveniences, in which the lead wire connection parts 2 and the lead wires 3 disposed on the ceramic substrate 1 have a vent structure containing an inorganic material. A substrate that is sequentially coated with a first sealing layer 4 made of synthetic resin and a second sealing layer 5 made of a synthetic resin with a non-porous structure containing adsorbent powder and an inorganic material, and further has other components 6 mounted thereon. The entire body is covered with an exterior mold 7 made of moisture-proof synthetic resin, and the substrate 1,
First sealing layer 4, second sealing layer 5 and exterior mold 7
The coefficient of thermal expansion of each part is selected so as to increase sequentially from the substrate 1, so that there is no large difference between the coefficients of thermal expansion of adjacent parts.
第２図において、１はアルミナ等のセラミツク
基板で、該セラミツク基板１上には、リード線接
続部品２及びその他の部品６が搭載され、該部品
２と、該部品２の端子と基板１上の接続端子とを
接続するリード線３には第１封止層４及び第２封
止層５が順次被覆され、前記基板１全体には外装
モールド７が被覆されている。 In FIG. 2, reference numeral 1 denotes a ceramic substrate made of alumina or the like, and lead wire connection parts 2 and other parts 6 are mounted on the ceramic board 1. The lead wires 3 connecting the connection terminals are sequentially covered with a first sealing layer 4 and a second sealing layer 5, and the entire substrate 1 is covered with an exterior mold 7.
前記第１封止層４は無機質材料を含有する通気
孔構造の合成樹脂から成り、その熱膨張係数は無
機質材料の量によりセラミツク基板のそれの1.5
以内としたものであり、樹脂としては溶剤性樹脂
が適する。 The first sealing layer 4 is made of a synthetic resin with a vent structure containing an inorganic material, and its coefficient of thermal expansion is 1.5 that of the ceramic substrate depending on the amount of the inorganic material.
A solvent-based resin is suitable as the resin.
第２封止層５は吸着剤粉末及び無機質材料を含
有する無気泡構造の合成樹脂から成り、その熱膨
張係数は無機質材料の量により第１封止層４のそ
れの３倍以内とし、かつ外装モールド７のそれの
1/2以内としたものであり、樹脂として無溶剤性
樹脂が適する。この層５は熱膨張緩衝性と共に第
１封止層４を湿気から防護するものであり該層内
に浸入した湿気を吸着剤で吸収する。 The second sealing layer 5 is made of a synthetic resin with a cell-free structure containing adsorbent powder and an inorganic material, and its coefficient of thermal expansion is within three times that of the first sealing layer 4, depending on the amount of the inorganic material, and That of exterior mold 7
The amount should be within 1/2, and a solvent-free resin is suitable as the resin. This layer 5 has thermal expansion buffering properties and protects the first sealing layer 4 from moisture, and uses an adsorbent to absorb moisture that has entered the layer.
前記外装モールド７は防湿性樹脂例えばエポキ
シ樹脂から成る。 The exterior mold 7 is made of moisture-proof resin, such as epoxy resin.
前記構成によれば、第１封止層４、第２封止層
５及び外装モールド７各部の熱膨張係数はセラミ
ツク基板１に対し順次増大するように選定され、
セラミツク基板１と第１封止層４等隣接する各部
の熱膨張係数の間に大きな差がないようにしてい
る。この熱膨張係数の調整は樹脂中にシリカ等の
無機質材料の量により行なつている。 According to the above configuration, the coefficients of thermal expansion of each part of the first sealing layer 4, the second sealing layer 5, and the exterior mold 7 are selected so as to increase sequentially with respect to the ceramic substrate 1,
It is ensured that there is no large difference in the coefficient of thermal expansion of adjacent parts such as the ceramic substrate 1 and the first sealing layer 4. The coefficient of thermal expansion is adjusted by adjusting the amount of inorganic material such as silica in the resin.
かくして温度変化の著しい雰囲気に配置された
場合においてもリード線の断線が生ずることがな
く、また湿気によりIC等の部品の特性が劣化す
ることがない。 In this way, even when placed in an atmosphere with significant temperature changes, the lead wires will not break, and the characteristics of components such as ICs will not deteriorate due to moisture.
実施例
熱膨張係数が７×10-6／℃のアルミナ基板１上
に0.3mmφのリード線３としての金線で接続され
たICチツプ２と該リード線３とを埋没するよう
にシリカを85重量％混合して熱膨張係数が１×
10-5／℃付近に調整された溶剤性フエノール樹脂
で被覆し、150℃の温度で１時間焼付け第１封止
層４を形成した。Example: On an alumina substrate 1 having a coefficient of thermal expansion of 7×10 -6 /°C, 85 silica is buried so as to embed the IC chip 2 connected with a gold wire as a lead wire 3 of 0.3 mmφ and the lead wire 3. When mixed by weight%, the thermal expansion coefficient is 1×
The first sealing layer 4 was formed by coating with a solvent-based phenolic resin adjusted to around 10 -5 /°C and baking at a temperature of 150°C for 1 hour.
次にアルミナ（40重量％）と活性炭（10重量
％）を混合して熱膨張係数が２〜３×10-5／℃に
調整されたエポキシ樹脂を第１封止層４上に塗布
し、100℃の温度で1.5時間焼付け、第２封止層５
を形成した。この焼付けの熱を利用して粉末エポ
キシ樹脂の中に基板を浸漬して樹脂を付着させ
150℃の温度で２時間焼付けて硬化させ３〜４×
10-5／℃の熱膨張係数の防湿モールド７を形成し
た。 Next, an epoxy resin mixed with alumina (40% by weight) and activated carbon (10% by weight) and whose thermal expansion coefficient was adjusted to 2 to 3 × 10 -5 /°C is applied on the first sealing layer 4, Bake at a temperature of 100℃ for 1.5 hours, second sealing layer 5
was formed. The heat of this baking is used to immerse the board in powdered epoxy resin to adhere the resin.
Baked at 150℃ for 2 hours to harden 3~4x
A moisture-proof mold 7 having a thermal expansion coefficient of 10 -5 /°C was formed.
以上のように形成された製品を、125℃に熱し
たシリコンオイル中に10分間保持して取り出し直
ちに−50℃に保持した低温槽に10分間保持する温
度サイクルを繰り返し100回行なつても外装モー
ルドにクラツク及びリード線の断線が生じなかつ
た。 The product formed as described above was placed in silicone oil heated to 125°C for 10 minutes, then immediately removed and placed in a low-temperature bath held at -50°C for 10 minutes. This temperature cycle was repeated 100 times, but no cracks were found in the exterior mold or breaks in the lead wires.
尚、シリコン樹脂を用いた従来のものは、20サ
イクル終了時に約半数に外装クラツクが、約５％
に断線が生じた。エポキシ樹脂の場合同じく20サ
イクルで外装クラツクがなかつたが断線が約８％
生じた。 In addition, with conventional products using silicone resin, approximately half of the cases have exterior cracks at the end of 20 cycles, and approximately 5% of cases have exterior cracks.
A disconnection occurred. In the case of epoxy resin, there was no crack on the exterior after 20 cycles, but about 8% of the wires were broken.
occured.
又、本考案品を２気圧、120℃の飽和蒸気中で
耐湿テストを行なつた結果、20時間のテストでは
異常がなかつた。これに対し従来のものは５時間
で絶縁劣化により半導体の電気特性に異常が発生
した。 Furthermore, the product of the present invention was subjected to a moisture resistance test in saturated steam at 2 atmospheres and 120°C, and no abnormalities were found during the 20 hour test. In contrast, in the conventional case, the electrical properties of the semiconductor became abnormal due to insulation deterioration within 5 hours.
このように本考案によるときは、セラミツク基
板１、第１封止層４、第２封止層５及び外装モー
ルド７等の各部の熱膨張係数を前記基板１から順
次増大するように選定され、隣接する各部の熱膨
張係数の間に大きな差がないようにされたので、
温度変化が連続的に加わつてもリード線が切断さ
れたり、湿気による特性の劣化などが生じない等
の混成集積回路が得られる等の効果がある。 In this way, according to the present invention, the coefficients of thermal expansion of each part of the ceramic substrate 1, the first sealing layer 4, the second sealing layer 5, the exterior mold 7, etc. are selected to increase sequentially from the substrate 1, Since there was no large difference between the thermal expansion coefficients of adjacent parts,
There are effects such as the ability to obtain a hybrid integrated circuit that does not cause lead wires to break or characteristics to deteriorate due to moisture even if temperature changes are continuously applied.
第１図は従来のものの拡大された一部截断側面
図、第２図は本考案の１実施例の拡大された一部
截断側面図を示す。
１……セラミツク基板、２……リード線接続部
品、３……リード線、４……第１封止層、５……
第２封止層、６……その他の部品、７……外装モ
ールド。
FIG. 1 shows an enlarged, partially cut-away side view of a conventional device, and FIG. 2 shows an enlarged, partially cut-away side view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Ceramic substrate, 2...Lead wire connection parts, 3...Lead wires, 4...First sealing layer, 5...
Second sealing layer, 6...Other parts, 7...Exterior mold.
Claims (1)
部品２及びリード線３が無機質材料を含有する通
気孔構造の合成樹脂から成る第１封止層４と吸着
剤粉末及び無機質材料を含有する無気孔構造の合
成樹脂から成る第２封止層５とで順次被覆され、
更に、その他の部品６を搭載した基板全体が防湿
性合成樹脂から成る外装モールド７で被覆され、
前記基板１、第１封止層４、第２封止層５及び外
装モールド７各部の熱膨張係数は、前記基板１か
ら順次増大するように選定され、隣接する各部の
熱膨張係数の間に大きな差がないようにされてな
る混成集積回路。 A first sealing layer 4 made of a synthetic resin with a vent structure containing an inorganic material and a non-porous structure containing an adsorbent powder and an inorganic material are arranged on a ceramic substrate 1, and a lead wire connecting part 2 and a lead wire 3 are arranged on the ceramic substrate 1. sequentially coated with a second sealing layer 5 made of a synthetic resin with a structure,
Furthermore, the entire board on which other parts 6 are mounted is covered with an exterior mold 7 made of moisture-proof synthetic resin,
The thermal expansion coefficients of each part of the substrate 1, the first sealing layer 4, the second sealing layer 5, and the exterior mold 7 are selected so as to increase sequentially from the substrate 1, and there is a difference between the thermal expansion coefficients of adjacent parts. A hybrid integrated circuit in which there are no major differences.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17561682U JPS5981040U (en) | 1982-11-22 | 1982-11-22 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17561682U JPS5981040U (en) | 1982-11-22 | 1982-11-22 | hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5981040U JPS5981040U (en) | 1984-05-31 |
| JPS622778Y2 true JPS622778Y2 (en) | 1987-01-22 |
Family
ID=30382024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17561682U Granted JPS5981040U (en) | 1982-11-22 | 1982-11-22 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5981040U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2796043B2 (en) * | 1993-07-30 | 1998-09-10 | 京セラ株式会社 | Electronic components |
| JP2014116409A (en) * | 2012-12-07 | 2014-06-26 | Denso Corp | Electronic device |
-
1982
- 1982-11-22 JP JP17561682U patent/JPS5981040U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5981040U (en) | 1984-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5165956A (en) | Method of encapsulating an electronic device with a silicone encapsulant | |
| CN108604589A (en) | Semiconductor device and its manufacturing method | |
| JPS622778Y2 (en) | ||
| US6265768B1 (en) | Chip scale package | |
| JPS6077446A (en) | Sealed semiconductor device | |
| JPS60154543A (en) | Semiconductor device using synthetic resin substrate | |
| JPS59154054A (en) | Wire and semiconductor device using it | |
| JPH0337308B2 (en) | ||
| JPH0142356Y2 (en) | ||
| EP0893823B1 (en) | Semiconductor bonding and sealing structure | |
| JPS61230344A (en) | Resin-sealed semiconductor device | |
| JP3147157B2 (en) | Electronic circuit device including semiconductor element | |
| JP2555519Y2 (en) | Surface-mount resin-encapsulated semiconductor device | |
| JPH0590448A (en) | Hybrid integrated circuit | |
| JPS6167247A (en) | Hybrid integrated circuit | |
| JPH0210858A (en) | Resin-sealed semiconductor device | |
| EP0412608A1 (en) | Semiconductor device | |
| JPS63143850A (en) | Semiconductor device | |
| JPS5855673Y2 (en) | Electronic component mounting equipment | |
| JPS59763Y2 (en) | hybrid integrated circuit | |
| JPH04252041A (en) | Manufacture of hybrid integrated circuit | |
| JPS6269538A (en) | Resin sealed semiconductor device | |
| JPH0493052A (en) | Semiconductor integrated circuit device | |
| JPS63316462A (en) | Semiconductor module | |
| JPS62108554A (en) | Hybrid integrated circuit device and manufacture thereof |