JPS62277754A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62277754A JPS62277754A JP61121452A JP12145286A JPS62277754A JP S62277754 A JPS62277754 A JP S62277754A JP 61121452 A JP61121452 A JP 61121452A JP 12145286 A JP12145286 A JP 12145286A JP S62277754 A JPS62277754 A JP S62277754A
- Authority
- JP
- Japan
- Prior art keywords
- lead pin
- hole
- insulating layer
- head section
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 title 1
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 13
- 239000011889 copper foil Substances 0.000 abstract description 10
- 238000007747 plating Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 6
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000001217 buttock Anatomy 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 210000002414 leg Anatomy 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
五 発明の詳細な説明
（産業上の利用分野）
本発明は、多数のビンが植設さｎたＩＣパッケージの製
造方法に関する。Detailed Description of the Invention V. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method of manufacturing an IC package in which a large number of bottles are embedded.
（従来の技術）
従来、有機基板をベースとして多数のリードピンが植設
さｎｒ、＝ｔｃパッケージ（ビングリッドアレイ）は、
例えば両面鋼箔を有するガラスエポキシ基板の所望する
部分にドリル孔を明け、無電解めっき等によって孔内の
導通を図り、レジスト像形成、めっき、エツチング等の
工程を経て導体パターンを形成した後、前記めっきを施
した孔にリードピン會多数植設し、プリント配線板との
接続を図ってきた。なお、前記り−ドピンにおいて、挿
入方向と反対側をリードピン頭部と定義すれば、塊状で
はリードピン頭部直径（第１図Ｌ）は１． 、Ｏｆｆ１
ｆｆｌ程度である。(Prior Art) Conventionally, a nr,=tc package (bin grid array) in which a large number of lead pins are implanted based on an organic substrate,
For example, a drill hole is drilled in a desired part of a glass epoxy substrate having double-sided steel foil, electrical conduction is established in the hole by electroless plating, etc., and a conductive pattern is formed through processes such as resist image formation, plating, and etching. A large number of lead pins were planted in the plated holes to connect with a printed wiring board. In addition, in the above-mentioned lead pin, if the side opposite to the insertion direction is defined as the lead pin head, the diameter of the lead pin head (L in Figure 1) is 1. , Off1
It is about ffl.
（発明が農法しようとする問題点ン
ＩＣパッケージは年々小型扁そ度化の傾向にある。例え
ば２０８ピンを有する一辺５Ｑｍｍ正方形のピングリッ
ドアレイでは、ＩＣテップ恰載領域が一辺２Ｑｍｍの正
方形程度となるため、残さｎた値域におけるリードピン
頭部の占める割付が大きくて高密度化し無い欠点がある
。また、ビン間の上脚を密にすると配線巾を小さくする
必要があり、より精度の尚い作業が安水さγＬるＭ来と
して歩留まりの点で問題がある。(Problem that the invention aims to address) IC packages are becoming smaller and flatter year by year.For example, in a pin grid array with 208 pins and a square of 5Qmm on a side, the IC chip mounting area is about a square of 2Qmm on a side. Therefore, the allocation occupied by the lead pin head in the remaining value range is large, and there is a drawback that high density cannot be achieved.Also, if the upper legs between the bins are densely arranged, the wiring width needs to be reduced, which requires more precision. Since the work is done using cheap water, there is a problem in terms of yield.
史にまた、第１図に示すような従来徊造では、はんだ上
げ以前の−・ンドリングの際、ピンが抜は易い欠点もあ
る。In addition, the conventional retractable structure shown in FIG. 1 also has the disadvantage that the pins are easily pulled out during soldering before soldering.
（問題点を解決するための手段）
以上従来技術の問題点にかんがみ、次の本発明を完成し
た。第２図によって不発明を説明する。(Means for Solving the Problems) In view of the problems of the prior art described above, the following invention has been completed. The non-invention will be explained with reference to FIG.
？縁性を有する配線板用基板１に孔を明けてスルーホー
ルめっき２を形成し、リードピン３を挿入する。次に基
板１の挿入リードピン頭部側の所望する部分にｋｆ２縁
層縁上４成する。この絶縁層は、例えば、スクリーン印
刷機でソルダーレジストや熱硬化性樹脂を塗布しても良
く、接渣用プリプレグあるいを工ＭＣＦ（日立化成社製
）のような片面に銅箔を有する絶縁フィルムを接着剤に
よってその絶縁フィルム仰」と接着させても良い。また
、絶縁層に金属板６ｔ−内蔵して所望する部分に孔明は
ヒ銅箔５と圧着して、熱放散を良くすることもできる。? A hole is made in a wiring board substrate 1 having an edge, a through-hole plating 2 is formed, and a lead pin 3 is inserted. Next, a kf2 edge layer 4 is formed on a desired portion of the board 1 on the head side of the insertion lead pin. This insulating layer may be coated with a solder resist or a thermosetting resin using a screen printing machine, or may be made of an insulating layer having a copper foil on one side, such as prepreg for deposits or MCF (manufactured by Hitachi Chemical Co., Ltd.). The film may be adhered to the insulating film by an adhesive. Alternatively, the metal plate 6t may be built into the insulating layer and pressed onto the arsenic foil 5 at a desired location to improve heat dissipation.
なお絶Ｍａｌ脂単独の場付は、銅箔のリードピン頭部に
対応した部分が圧；ｆｉｉ＃ｆ？ｆに若干盛り上がるた
め、金属板を内蔵する力が表面平坦化のために好ましい
。In addition, when attaching Zettai Mal fat alone, the part corresponding to the head of the copper foil lead pin is pressure; fii#f? Since f is slightly raised, it is preferable to incorporate the metal plate in order to flatten the surface.
次に、銅箔５の所望する部分（後工程でバイアホール７
とする部分）をエツチング除去し、銅箔５をレジストと
してリードピン頭部に達しかつリードピン頭部より小径
の孔（バイアホール）を設けて孔内を等連させた後、表
面にレジスト像全形放し、所望する導体回路パターン８
を形成スル。パイ１ホール７の＃敢は、ウェットエツチ
ングの他に炭酸ガスレーザなどが使用でき、リードピン
の頭部面で止まる構造となる。なお、パイ１ホール形成
工程では、跳にリードピンが挿入ｎているため、ウェッ
トエツチングｆｔする際は基板から突出している凸部（
リードピンの足）に対応した凹部を有するジグで製画を
保禮するか、成るいはレーザ加工のようなドライ工程が
望ましい。最後に、ＩＣチップを搭載する部分は金属板
６までザグリ１工することで得らｎる。Next, a desired portion of the copper foil 5 (via hole 7 in a later process) is
After using the copper foil 5 as a resist to form a hole (via hole) that reaches the lead pin head and has a smaller diameter than the lead pin head so that the inside of the hole is evenly connected, the entire resist image is formed on the surface. Release the desired conductor circuit pattern 8
Forming a sul. In addition to wet etching, a carbon dioxide laser or the like can be used to etch #1 hole 7, and the structure is such that it stops at the head surface of the lead pin. In addition, in the pie hole formation process, lead pins are inserted into the holes, so when performing wet etching, the protrusions protruding from the substrate (
It is preferable to secure the drawing with a jig having a recess corresponding to the lead pin's foot, or to use a dry process such as laser processing. Finally, the part where the IC chip is to be mounted can be obtained by making a counterbore up to the metal plate 6.
（作用）
表面層のパイ１ホール径１ （Ｍ２図ｔＱ ） ｔ Ｉ
Ｊ−ドビン頭部径Ｌ（第１図）より小さくすることによ
って、配線領域を拡大することができる。(Function) Pi 1 hole diameter of surface layer 1 (M2 diagram tQ) t I
By making the head diameter smaller than the J-Dobbin head diameter L (FIG. 1), the wiring area can be expanded.
リードピン３上に絶縁層４を形成することによって、リ
ードピンの保持が安定する。また、レーザ加工によって
バイアホールを形成する場曾に、リードピン頭部でレー
ザ光照射を止める効果がある。By forming the insulating layer 4 on the lead pin 3, the lead pin can be held stably. Further, when forming a via hole by laser processing, there is an effect of stopping the laser beam irradiation at the head of the lead pin.
実施例
第２図において、絶！９！性を有する厚さ１．５ｍｒａ
のガラス布積層板（日立化成社製ＭＣＬ−Ｅ−６７）１
の所望する部分に０．８φ市の孔全ドリル加工し、その
表ｆおよび孔内に銅めっきを施した後レジスト像を形成
し、次いで通常のエツチング方法で銅めつきを除き所望
部分２だけ七残す。さらに孔にリードピン３を植設して
第１次基板１とする。岸さＱ、 ８ｍｒｎのアルミ板６
（住友社製ＳＤＰ−３０Ｍ−ＰＳ）の所望する部分にリ
ードピン頭部径より大きい孔（φ１．２ ｍｍ ）を設
け、表裏をサンドペーパで研がした仮、５％シランカッ
プリング剤（日立化成社製Ａ−１１００）を塗布し１２
０℃、１０分間ＩＸ１．燥したものに表１に示す組成の
孔埋め樹脂４を充填し、その孔埋めｆｆｌ ＩＪ！を介
してｇＡ？？！３５と第１次基板のリードピン頭部面と
を１５０℃、４．０ｋｇ／（プで３０分間加熱圧着する
。なお、前記孔埋め樹脂はシート状にしたものを加熱圧
着しても良い。次にｇＩＡ箔５のｐ）Ｔ望する部分をエ
ツチングして直径０．１關のレーザ孔明は用ホールを形
成する。このホールに炭酸ガスレーザ（島田理化社製）
を照射してリードピン頭部面に璋するバイアホール７全
形成する。次に、スパッタリング装置（日本真空技術製
）Ｋよりスパッタ脩でパイ１ホール内の導通を図っ１こ
優、銅箔５」二にレジスト像を形成し、４μｍ厚の１気
Ｎｉめっき、続いて１μｍ厚の金めつきを施し、金めつ
きをエツチングレジストとして所望する回路パターン８
を得た。なお、パイ１ホールフ円の尋辿ニは通常の無電
解銅めっきを使用しても良い。最後にＩＣチップを搭載
する部分臀工、アルミ板６までザグリ加工することで得
た。In FIG. 2 of the embodiment, absolutely! 9! Thickness: 1.5mra
Glass cloth laminate (MCL-E-67 manufactured by Hitachi Chemical Co., Ltd.) 1
Drill all holes of 0.8φ in the desired part of the hole, apply copper plating to the surface f and inside the hole, form a resist image, and then remove the copper plating using a normal etching method to remove only the desired part 2. Leave seven. Furthermore, lead pins 3 are implanted in the holes to form the primary substrate 1. Shore Q, 8 mrn aluminum plate 6
(SDP-30M-PS manufactured by Sumitomo) A hole (φ1.2 mm) larger than the head diameter of the lead pin was made in the desired part, and the front and back sides were polished with sandpaper. Coat A-1100) and apply 12
0°C, 10 minutes IX1. The dried material was filled with pore-filling resin 4 having the composition shown in Table 1, and the pore-filling resin 4 was filled with ffl IJ! via gA? ? ! 35 and the head surface of the lead pin of the primary board are heat-pressed at 150° C. and 4.0 kg/(press) for 30 minutes. Note that the hole-filling resin may be heat-pressed in the form of a sheet.Next Then, the desired portion of the gIA foil 5 is etched to form a laser hole with a diameter of about 0.1 mm. A carbon dioxide laser (manufactured by Shimada Rika Co., Ltd.) is installed in this hole.
The entire via hole 7 is formed on the head surface of the lead pin. Next, conduction was established in the first hole using sputtering equipment (manufactured by Japan Vacuum Technology Co., Ltd.) using a sputtering device K. A resist image was formed on the copper foil 5", followed by 4 μm thick 1-atm Ni plating. Circuit pattern 8 with gold plating of 1 μm thickness and desired gold plating as an etching resist
I got it. Note that ordinary electroless copper plating may be used for the cross-section of the pie-1-hole circle. Finally, we obtained the partial buttock where the IC chip will be mounted, by counterboring down to the aluminum plate 6.
表１
（発明の効果）
本発明によって配線領域が拡大したため、塊状ンベルで
の歩留ｆ９が同上し、尚一層の高密度化に対処可能とな
った。Table 1 (Effects of the Invention) Since the wiring area has been expanded according to the present invention, the yield f9 of the block-shaped panel has been increased to the same level as above, and it has become possible to cope with even higher density.
本発明によってリードピンの保持が安定Ｌ ７Ｃため、
はんだ上げ以前におけるリードピンの抜は不良が無くな
ったりBecause the present invention stably holds the lead pin L7C,
No more defects when removing lead pins before soldering
第１図は従来のビングリッドアレイを示す断面図、第２
回置へ（ｑ Ｇ二本発明の方法を示す断面面である。
１・・・・−・絶縁性基板、２・・・・・・銅箔、３・
・−・・・リードピン、４・・・・・・絶縁層、５・・
・・・・銅箔、６・・・・・・金属板、７・・・・・・
パイ１ホール、８・・・・・−表面回路、９・・・・・
・ＩＣテッグ、１０・・・・・・ボンディング用ワイヤ
。
と−一Figure 1 is a sectional view showing a conventional bin grid array;
To rotation (q G2) This is a cross-sectional view showing the method of the present invention. 1... Insulating substrate, 2... Copper foil, 3...
...Lead pin, 4...Insulating layer, 5...
...Copper foil, 6...Metal plate, 7...
Pi 1 hole, 8...-Surface circuit, 9...
・ICTEG, 10... Wire for bonding. To-one
Claims (1)
て、該リードピンの頭部側の所望する部分上に絶縁層を
形成し、該絶縁層表面側から該リードピン頭部に達しか
つリードピン頭部より小さい孔を設け、該絶縁層表面に
導体でライン展開して該リードピンと該ラインとを導通
させることを特徴とするＩＣパッケージの製造方法。1. In an IC package in which a large number of lead pins are implanted, an insulating layer is formed on a desired portion of the head side of the lead pin, and a hole that reaches the head of the lead pin from the surface side of the insulating layer and is smaller than the head of the lead pin is formed. 1. A method for manufacturing an IC package, comprising: providing a line with a conductor on the surface of the insulating layer to establish electrical continuity between the lead pin and the line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61121452A JPS62277754A (en) | 1986-05-27 | 1986-05-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61121452A JPS62277754A (en) | 1986-05-27 | 1986-05-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62277754A true JPS62277754A (en) | 1987-12-02 |
Family
ID=14811483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61121452A Pending JPS62277754A (en) | 1986-05-27 | 1986-05-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62277754A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0851724A3 (en) * | 1996-12-26 | 2000-09-27 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and electric components |
-
1986
- 1986-05-27 JP JP61121452A patent/JPS62277754A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0851724A3 (en) * | 1996-12-26 | 2000-09-27 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and electric components |
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