JPS62276973A - Television receiver - Google Patents

Abstract

PURPOSE:To save power consumption by stopping the operation of an A/D conversion means except for the effective scanning period of a TV video signal in a TV receiver. CONSTITUTION:A video signal from a video detection circuit is given to a synchronizing signal separation circuit 2 and an A/D converter 3 via a video amplifier circuit 1. The circuit 2 separates horizontal/vertical synchronizing signals from a video signal and outputs the result to a control circuit 4. The circuit 4 gives drive timing to a 1st and a 2nd drive circuits 6,7 via a shift register 5 and generates a chip-enable signal CE selecting the video signal at each other horizontal scanning and gives it to the device 3. Thus, the device 3 is operated at each scanning and the video signal outputted from the circuit 1 is converted into a digital signal, which is outputted to a shift register 9. Data written in the register 9 is sent to the circuit 7 via a buffer 10 and displayed on a liquid crystal panel 8.

Description

[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to a television receiver.

[Prior art and its problems] Research has been progressing on television receivers using panel-type display devices such as liquid crystal displays. In this type of television receiver, the received and amplified video signal is
A conversion device converts the signal into a digital signal, and the digital signal drives a display device to display an image.

However, panel type display devices such as liquid crystal display devices generally scan '&l! The poles and signal electrodes are arranged in a square pattern, and the scanning voltage is driven in temporary divisions, and A-Df converted digital data is supplied to the signal electrodes to display images.

By the way, the video signal includes horizontal and vertical synchronization signals, and display data is not included during the period of the synchronization signals (retrace period).

However, in the past, the A-D converter was always operated and timing control was used to read only the sampling data during the effective scanning period to the display device.In other words, the sampling data during the retrace period was supplied to the display panel. The display process was performed in such a way that it did not occur.

Therefore, since the A-D conversion operation is performed even during a period when the display is not normally displayed, there is a problem in that power is wasted.

[Object of the invention] This invention was made in view of the above circumstances, and an object of the invention is to reduce power consumption by stopping the operation of the A-D converter during the retrace period of the video signal. .

[Summary of the Invention] In order to achieve the above object, the present invention provides a television receiver that converts a television video signal into a digital signal by an A-D conversion means and displays the digital signal on a panel display device. The key point is to provide means for stopping the operation of the A/D converting means for a period longer than the effective scanning period of the video signal.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
Is the diagram the configuration of the main parts of an LCD TV receiver? This is what is shown. In the figure, 1 is a video amplification circuit, which amplifies the signal from a video detection circuit (not shown), and a synchronous separation circuit 2.
and output to the A-D converter 3. Further, a part of the output signal of the video amplification circuit 1 is sent to an audio amplification circuit (not shown).

The synchronization separation circuit 2Vi separates horizontal and vertical synchronization signals from the input video signal and outputs them to the control circuit 4. The control circuit 4 provides a drive timing signal to the first drive circuit 6 and a timing signal to the second drive circuit 7 via a shift register 52 . The first drive circuit 6 performs vertical scanning of the liquid crystal display panel 8, and the second drive circuit 7 performs two horizontal scans of the liquid crystal display panel 8. Further, the control circuit 4 controls the video signal to 1
A chip enable signal CEI to be selected is generated every water sample scan and is applied to the A/D converter 3. This A-D converter 3 includes a reference potential generation circuit 1, converter A regulators 121 to 1.
2n, a decoder 13, and a bias circuit 14. The reference potential generation circuit 11 generates a low level reference potential vX and a high level reference potential vH according to the white level voltage and black level voltage of the video signal,
These reference potentials vL and vH can be applied directly or through resistors R1 to R1.
The voltage is divided by IIn and input to the reference terminals of comparators 128 to 12n.

The output signal of the video amplification circuit 1 is applied to the comparison terminals of the comparators 12 and 12n. On the other hand, although the details will be described later, the bias circuit 14 operates in synchronization with the chip enable signal plane, and the bias circuit 14 operates in synchronization with the chip enable signal plane,
Apply bias e to n.

Comparator 12. 12n is applied with a bias from the bias circuit 14 and performs an open operation, and inputs its output signal to the decoder 13. This decoder 13 decodes the input signal into, for example, a 4-bit digital signal and sends it to the shift register 9 as an output of the AD converter 3. This shift register 9 is configured so that, for example, the liquid crystal display panel 8 has a 120X
For 160 dot double matrix, 4 dots) x 32
It is configured in 0 stages. And the shift register 9Vc
The input data is sent to the second drive circuit 7 via the buffer 10. This second drive circuit 7 includes a buffer 10
The output of the control circuit 4 is modulated in brightness based on the brightness and pulse from the control circuit 4, and a driving bias is applied to the liquid crystal display/main channel 8.

Next, the comparator 12. , 12. ... and the details of the bias circuit 14 portion will be explained with reference to FIG. The bias circuit 14 mainly includes, for example, N-channel transistors 21 to 24, diodes 25.degree. 26, and a Schittky diode 27. The terminal 28 to which the chino enable signal CE is applied is grounded via a diode 25 having the polarity shown, and is also connected to the base of the transistor 21 via a diode 26.

The base and collector of this transistor 21 are connected to the vcct source via resistors 29 and 30, respectively, and the emitter is connected to the vcct source through resistors 29 and 30, respectively. It is connected to the base of the transistor 22 as well as to ground through the transistor 22 . This transistor 22f'
i, the emitter is grounded, and the collector is connected to the collector of the transistor 23 and the transistor 2 through the diode 27.
Connected to the base of 4. And the transistor 2
The collector of No. 3 is connected to the VCC power supply via a resistor 32, and the emitter is grounded via a resistor 33. Further, the collector of the transistor 24 is connected directly to vcc1! The emitter is grounded through a resistor 34 and connected to the base of the transistor 23. Then, the emitter output potential of the transistor 24 is set to the comparator 12.
．． ．． Switching transistors 35.122, . ．． 35. ... is supplied as a base bias.

Next, the operation of the above embodiment will be explained. The chip enable signal CE is a signal that selects the video signal existing between the horizontal synchronization signals every other scan, as shown in FIG.
It is at high level every scan, and is at low level at other times. A signal CE obtained by inverting the chip enable signal CE is sent from the control circuit 4 to the bias circuit 14.
This is the signal given to Therefore, the chip enable signal CFJ is transmitted to the bias circuit 14 whose details are shown in FIG.
When the voltage is applied to the terminal 28 of the transistor 21, the diode 26 is turned on during the low level period, and the base potential of the transistor 21 becomes low level. Therefore, the transistor 21
The base current does not flow and the transistor 22 is turned off, and at the same time, the transistor 22 is also turned off.

When this transistor 22 is off, no current flows through the diode 27, and the collector of the transistor 23 and the base W of the transistor 24 are kept at a high potential. Therefore, transistors 24 and 23 are both turned on, supplying appropriate base currents to switching transistors 351 and 35 of consummarators 121 and 12, and so on. As a result, transistor 35. ．． 35.
... are turned on, and comparators 128.12. ... becomes operational and samples the video signal.

On the other hand, during the period when the chig enable signal CE is at a high level, the diode 26 becomes reverse biased and turns off.
The base potential of transistor 2 rises. Therefore, transistor 21 is turned on, transistor 22 is turned on at the same time, current flows through diode 27, and transistor 24 is turned on.
lowers the base potential of 0.4 V to about 0.4 V. Therefore, transistors 24 and 23 are turned off, and transistor 35
,.

No base current is supplied to 35, . As a result, transistor 35. , 35. ...is turned off,
Comparator 12. , 12. ... is in a non-operating state.

In this way, the A/D converter 3 operates every other scan, converts the video signal output from the video amplifier circuit 1 into a 4-bit digital signal, and outputs the digital signal to the shift register 9. The data written in this shift register 9 is sent to the second movement circuit 7 via the buffer 10 and displayed on the liquid crystal display panel 8. In the above embodiment, constant current control to the comparator is performed using the chip enable signal CE, but it goes without saying that the present invention is not limited to the above embodiment, and the same may be done using a non-inverted chip enable signal CE. Further, in the above embodiment, the video signal is selected every other scan, but it goes without saying that all effective scanning lines may be selected. In short,
The operation of the A/D converter may be stopped during the blanking period other than the effective scanning period.

[Effects of the Invention] As explained above, according to the present invention, the operation of the A-D converter is stopped except during the effective scanning period of the video signal, which reduces power consumption. It can be measured.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention. Fig. 1 is a circuit configuration diagram, Fig. 2 is a diagram showing details of the comparator and bias circuit portion in Fig. 1, and Fig. 3 is a diagram showing a video signal and a chip enable signal. FIG. 3... A-D converter, 11... Reference potential generation circuit, 12, to 12n... Comparator, 13... Decoder, 14... Bias circuit.

Claims (1)

[Scope of Claims] In a television receiver that converts a television video signal into digital data by an A-D conversion means and displays the digital data on a panel display device, the above A-D is used except during the effective scanning period of the television video signal.
A television receiver characterized by being provided with means for stopping the operation of the converting means.