JPS62276863A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPS62276863A JPS62276863A JP61119226A JP11922686A JPS62276863A JP S62276863 A JPS62276863 A JP S62276863A JP 61119226 A JP61119226 A JP 61119226A JP 11922686 A JP11922686 A JP 11922686A JP S62276863 A JPS62276863 A JP S62276863A
- Authority
- JP
- Japan
- Prior art keywords
- header
- package
- resin
- pellet
- electronic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 claims description 4
- 238000004080 punching Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000008188 pellet Substances 0.000 abstract description 19
- 239000011347 resin Substances 0.000 abstract description 13
- 229920005989 resin Polymers 0.000 abstract description 13
- 230000008646 thermal stress Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 230000035882 stress Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は、電子装置、特に、ヘッダの構造についての改
良に関し、例えば、樹脂封止型パフケージを備えている
面付実装型のトランジスタ（以下、ＵＰＡＫトランジス
タという。〕に利用して育効な技術に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Industrial Field of Application] The present invention relates to improvements in the structure of electronic devices, particularly headers, and, for example, a surface equipped with a resin-sealed puff cage. This invention relates to a technology that can be effectively applied to UPAK transistors (hereinafter referred to as UPAK transistors).
ＵＰＡＫ ）ランジスクとして、パッケージに植設され
ているヘッダがパッケージの内部における外周に鍔を備
えており、この鍔部によってヘッダのパッケージからの
抜は止めを行うようにしているものがある。Some UPAK) run discs have a header implanted in a package that is provided with a flange on the outer periphery inside the package, and this flange prevents the header from being removed from the package.
なお、樹脂封止型パッケージを備えているトランジスタ
を述べである例としては、株式会社工業調査会発行「電
子材料１９８１年１１月号」昭和５６年１１月１日発行
Ｐ４２〜Ｐ４６、がある。An example of a transistor having a resin-sealed package is ``Electronic Materials November 1981'' published by Kogyo Research Association Co., Ltd., pages 42 to 46, published on November 1, 1981.
このようなＵＰＡＫ）ランジスタにおいては、出荷時ま
たは入荷時における抜き取り検査される際に、熱衝撃試
験や温度サイクル試験において加熱されると、ペレット
にクランク不良が発見されるという問題点があることが
、本発明者によって明らかにされた。In such UPAK) transistors, there is a problem that crank defects may be found in the pellets if they are heated during thermal shock tests or temperature cycle tests during sampling inspections at the time of shipment or arrival. , was revealed by the present inventor.
本発明の目的は、熱ストレスによる不良の発生を防止す
ることができる電子装置を提供することにある。An object of the present invention is to provide an electronic device that can prevent defects caused by thermal stress.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
Ｃ問題点を解決するための手段〕
本願において開示される発明のうち代表的なものの概要
を説明すれば、次の通りである。Means for Solving Problem C] Representative inventions disclosed in this application will be summarized as follows.
すなわち、樹脂封止型パッケージの内部においてヘッダ
の外周に凹凸部を設けたものである。That is, an uneven portion is provided on the outer periphery of the header inside the resin-sealed package.
前記した手段によれば、ヘッダ外周の凹凸部がパンケー
ジの内部において樹脂に喰い付くため、熱的試験によっ
てパッケージおよびヘッダが加熱されてこれらに応力が
加わっても、樹脂がヘッダに対してずれることはない。According to the above-mentioned means, the uneven portion on the outer periphery of the header bites into the resin inside the pan cage, so even if the package and header are heated and stress is applied to them during a thermal test, the resin will not shift relative to the header. There isn't.
その結果、ヘッダ上のペレットにストレスが加わること
は抑止ないしは十分に抑制されることになるため、ペレ
ットにクランク等の損傷が発生することは防止されるこ
とになる。As a result, stress is suppressed or sufficiently suppressed from being applied to the pellet on the header, and damage to the pellet due to cranking or the like is prevented.
第１図は本発明の一実施例であるＵＰＡＫ ）ランジス
クを示すパッケージを除いた状態の斜視図、第２図は第
３図の■〜■碌に沿う正面断面図、第３図は第２図のＩ
Ｉ−Ｉ［線に沿う平面断面図である。Fig. 1 is a perspective view of a UPAK lanzik which is an embodiment of the present invention, with the package removed; Figure I
It is a plane sectional view taken along the line I-I.
本実施例において、電子装置としてのＵＰＡＫトランジ
スタ１は、導電性および熱伝導性を有する材料を用いて
形成されているヘッダ２と２本のインナリード３．３と
を備えており、両インナリード３．３はへ７ダ２の両脇
に互いに平行に並設されている。ヘッダ２および両イン
ナリード３．３にはアウタリード４が一方向に突出する
ようにそれぞれ一体的に連結されている。ヘッダ２の一
端面（以下、上面とする。）上にはトランジスタ回路（
図示せず）を作り込まれたペレット５がポンディングさ
れている。また、このヘッダ４の両脇に配されたインナ
リード３．３とペレット５との間にはボンディングワイ
ヤ６がそれぞれボンディングされており、ペレット５の
回路は各インナリードを経てアウタリード４にそれぞれ
電気的に引き出されている。In this embodiment, a UPAK transistor 1 as an electronic device includes a header 2 and two inner leads 3.3 formed using a material having electrical conductivity and thermal conductivity. 3.3 are arranged parallel to each other on both sides of the header 2. An outer lead 4 is integrally connected to the header 2 and both inner leads 3.3 so as to protrude in one direction. A transistor circuit (
Pellets 5, which are made up of molten metal (not shown), are pounded. Further, bonding wires 6 are bonded between the inner leads 3.3 and the pellet 5 arranged on both sides of the header 4, and the circuit of the pellet 5 is electrically connected to the outer lead 4 through each inner lead. It has been brought out specifically.
そして、ヘッダ２は大略長方形の平盤形状に形成されて
おり、ヘッダ２の外周の上部にはヘッダ２における肉厚
の約半分の厚さを有する鍔部７が形成されている。この
鍔部７には複数個の凹部８ａおよび凸部８ｂが交互に配
されて形成されている。鍔部７および凹凸部８の形成方
法としては、ヘッダ２の打ち抜きプレス加工時に凹凸部
８をヘッダ２の外周部に同時に打ち抜き成形し、続いて
、ヘッダ２の外周下部における凹凸部８の四部８ａに相
当する幅の部分を約半分にコイニング（押印）加工して
形成する方法を使用するとよい。この方法によれば、生
産性の低下を抑制しつつ、凹凸部８を形成することがで
きる。The header 2 is formed into a generally rectangular flat plate shape, and a flange portion 7 having a thickness approximately half of the thickness of the header 2 is formed at the upper part of the outer periphery of the header 2. This collar portion 7 is formed with a plurality of recesses 8a and projections 8b arranged alternately. As a method for forming the flange portion 7 and the uneven portion 8, the uneven portion 8 is simultaneously punched and formed on the outer periphery of the header 2 when the header 2 is punched and press-formed, and then the four portions 8a of the uneven portion 8 on the lower outer periphery of the header 2 are formed. It is preferable to use a method of coining (sealing) a portion of the width equivalent to approximately half. According to this method, the uneven portion 8 can be formed while suppressing a decrease in productivity.
このトランジスタ１は樹脂封止型パッケージ９を備えて
おり、パッケージ９は適当な樹脂を用いてヘッダ２の下
面を除く部分、インナリード３、ペレット５およびボン
ディングワイヤ６を非気密封止するようにトランスファ
成形法等のような適当な手段により一体成形されている
。そして、ヘッダ２の外面上部に形成された鍔部７にお
ける凹凸部８はパッケージ９の内部に完全に埋め込まれ
ている。This transistor 1 includes a resin-sealed package 9, and the package 9 uses a suitable resin to non-hermetically seal the header 2 except for the bottom surface, the inner lead 3, the pellet 5, and the bonding wire 6. It is integrally molded by a suitable method such as a transfer molding method. The uneven portion 8 of the flange portion 7 formed on the upper outer surface of the header 2 is completely embedded inside the package 9.
次に作用を説明する。Next, the effect will be explained.
前記のように構成されたＵＰＡＫ ｌ−ランジスタ１は
、出荷時や入荷時において抜き取り検査を実施される。The UPAK l-transistor 1 configured as described above is subjected to a sampling inspection at the time of shipment or arrival.
この祭、熱衝撃試験や温度サイクル試験等が実施される
ため、［ＪＰＡＫ トランジスタ１は加熱される。この
加熱により、パッケージ９およびヘッダ２は熱ストレス
を受ける。At this festival, thermal shock tests, temperature cycle tests, etc. are conducted, so [JPAK transistor 1 is heated. Due to this heating, the package 9 and the header 2 are subjected to thermal stress.
ところで、ヘッダに凹凸部が形成されていない場合、熱
ストレスによってパッケージの樹脂が膨張して動くため
、ヘッダ上に固着されたペレットに応力が加わり、これ
によってペレットにクランク等のような損傷が発生する
。このようなペレットの損傷が発見されると、製品の信
頼性が低下されるため、使用はｆ挙止される。By the way, if the header does not have uneven parts, the resin in the package expands and moves due to thermal stress, which applies stress to the pellet fixed on the header, which can cause damage to the pellet such as a crank. do. If such pellet damage is discovered, the reliability of the product is reduced and its use is therefore discouraged.
しかし、本実施例においては、ヘッダ２の外周部に上部
７とともに凹凸部８が形成されているため、ペレットの
損傷は防止される。すなわち、パッケージ９の樹脂は鍔
部７および凹凸部８に喰い付くことによって！Ｂ械的に
拘束されるため、樹脂が動くのを阻止され、その結果、
樹脂からペレ。However, in this embodiment, since the uneven portion 8 is formed on the outer peripheral portion of the header 2 together with the upper portion 7, damage to the pellets is prevented. That is, the resin of the package 9 bites into the flange portion 7 and the uneven portions 8! B. Due to mechanical restraint, the resin is prevented from moving, and as a result,
Pele from resin.
ト５に応力が加わることは抑止ないしは抑制されるため
、ベレット５に損傷が発生することは防止される。Since stress is suppressed or suppressed from being applied to the pellet 5, damage to the pellet 5 is prevented.
前記実施例によれば次の効果が得られる。According to the embodiment described above, the following effects can be obtained.
（１） ヘッダの外周部に凹凸部をバフケージの内部
において形成することにより、パッケージの樹脂を凹凸
部によって機械的に拘束させることができため、樹脂が
熱ストレスによって動くのを阻止することができ、ペレ
ットの損傷を防止することができる。(1) By forming an uneven part on the outer periphery of the header inside the buff cage, the resin of the package can be mechanically restrained by the uneven part, thereby preventing the resin from moving due to thermal stress. , can prevent pellet damage.
（２）熱ストレスによるペレットの損傷を防止すること
により、ＵＰＡＫ トランジスタの品質および信頼性を
高めることができる。(2) By preventing pellet damage due to thermal stress, the quality and reliability of UPAK transistors can be improved.
（３）凹凸部を打ち抜きプレス加工およびコイニング加
工によって作成することにより、生産性の低下を抑制し
つつ凹凸部を形成することができるため、コスト環を招
くことなしに、製品の品質および信頼性を高めることが
できる。(3) By creating the uneven portion by punching press processing and coining processing, it is possible to form the uneven portion while suppressing a decrease in productivity, thereby improving the quality and reliability of the product without incurring costs. can be increased.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸説しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples and can be modified in various ways without departing from the gist of the invention. Not even.
例えば、凹凸部は打ち抜きプレス加工およびコイニング
加工によって作成するに限らず、エツチング加工によっ
て作成してもよい。この場合、マスクパターンにより一
体加工することができるとともに、鍔部は片面二ノチン
グ処理により作り出すことができる。For example, the uneven portions are not limited to being created by punching press work and coining work, but may also be created by etching work. In this case, integral processing can be performed using a mask pattern, and the flange can be created by double-notching treatment on one side.
凹凸部の形状は四角形に形成するに限らず、三角形また
は半円形等に形成してもよい。The shape of the uneven portion is not limited to a rectangular shape, but may be formed into a triangular shape, a semicircular shape, or the like.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＵＰＡＫ）ランジス
タに適用した場合について説明したが、それに限定され
るものではなく、本発明は少なくとも、ヒートシンクが
必要な電子装置全般に適用することができる。The above explanation has mainly been about the case where the invention made by the present inventor is applied to the field of application (UPAK) transistor, which is the background of the invention, but it is not limited thereto, and the present invention requires at least a heat sink. It can be applied to all kinds of electronic devices.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、次の通りである。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
ヘッダの外周部に凹凸部をパッケージの内部において形
成することにより、パッケージの樹脂を凹凸部によって
機械的に拘束させることができるため、樹脂が熱ストレ
スによって動くのを阻止することができ、その結果、ベ
レットの損傷等の発生を防止することができる。By forming an uneven part on the outer periphery of the header inside the package, the resin of the package can be mechanically restrained by the uneven part, which prevents the resin from moving due to thermal stress. , the occurrence of damage to the beret, etc. can be prevented.
第１図は本発明の一実施例であるＵＰＡＫ ）ランジス
タを示すパフケージを除いた状態の斜視図、第２図は第
３図のＩＩ−［［線に沿う正面断面図、第３図は第２図
のｔｔ−ｎ線に沿う平面断面図である。
１・・・ＵＰＡＫ ）ランジスタ（電子装置）、２・
・ ・ヘッダ、３・ ・ ・インナリード、４・ ・・
アウタリード、５・ ・ベレット、６・・・ボンディ
ングワイヤ、７・・・鍔部、８・・・凹凸部、８ａ・・
・凹部、８ｂ・・・凸部、９・・・パッケージ、１１・
・・透孔。FIG. 1 is a perspective view of a UPAK transistor according to an embodiment of the present invention with the puff cage removed; FIG. 2 is a front cross-sectional view taken along line II-[[ of FIG. 3; FIG. 3 is a plan sectional view taken along the tt-n line in FIG. 2; 1...UPAK) transistor (electronic device), 2.
・ ・Header, 3... ・Inner lead, 4...
Outer lead, 5... Bellet, 6... Bonding wire, 7... Flange, 8... Uneven part, 8a...
・Concave portion, 8b...Convex portion, 9...Package, 11.
...Through hole.
Claims (1)
一部が露出されているヘッダが、パッケージの内部にお
ける外周に凹凸部を設けられていることを特徴とする電
子装置。 ２、凹凸部が、ヘッダの打ち抜きプレス加工時に同時成
形された後、凸部を厚さ方向にコイニング加工されて形
成されていることを特徴とする特許請求の範囲第１項記
載の電子装置。 ３、凹凸部が、エッチング加工により一体成形されてい
ることを特徴とする特許請求の範囲第１項記載の電子装
置。[Claims] 1. Implanted in a resin-sealed package,
An electronic device characterized in that a partially exposed header is provided with an uneven portion on the outer periphery inside the package. 2. The electronic device according to claim 1, wherein the concave and convex portions are formed by coining the convex portions in the thickness direction after being simultaneously formed during punching and press processing of the header. 3. The electronic device according to claim 1, wherein the uneven portion is integrally formed by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61119226A JPS62276863A (en) | 1986-05-26 | 1986-05-26 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61119226A JPS62276863A (en) | 1986-05-26 | 1986-05-26 | Electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62276863A true JPS62276863A (en) | 1987-12-01 |
Family
ID=14756079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61119226A Pending JPS62276863A (en) | 1986-05-26 | 1986-05-26 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62276863A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5497032A (en) * | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
| JP2008541435A (en) * | 2005-05-03 | 2008-11-20 | インターナショナル レクティファイアー コーポレイション | Wirebond device package for semiconductor devices having elongated electrodes |
| JP2011077286A (en) * | 2009-09-30 | 2011-04-14 | Shindengen Electric Mfg Co Ltd | Semiconductor package and method for manufacturing the same |
-
1986
- 1986-05-26 JP JP61119226A patent/JPS62276863A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5497032A (en) * | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
| US5804468A (en) * | 1993-03-17 | 1998-09-08 | Fujitsu Limited | Process for manufacturing a packaged semiconductor having a divided leadframe stage |
| JP2008541435A (en) * | 2005-05-03 | 2008-11-20 | インターナショナル レクティファイアー コーポレイション | Wirebond device package for semiconductor devices having elongated electrodes |
| JP2011077286A (en) * | 2009-09-30 | 2011-04-14 | Shindengen Electric Mfg Co Ltd | Semiconductor package and method for manufacturing the same |
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