JPS6227632B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a speed control device for an electric motor using a conventionally used so-called PLL control method.

In the PLL control method, a pulse voltage with a frequency corresponding to the rotational speed of the motor is generated by an encoder installed inside or outside the motor, and the phase difference between this pulse voltage and a reference pulse voltage corresponding to the reference speed of the motor. This is a motor speed control method that controls the applied voltage based on the signal obtained by detecting the This PLL control method has shortcomings, which will be described later, and is therefore rarely used. Several PLL-specific devices have been developed to solve these problems, but they are all complicated and expensive. The present invention aims to solve this problem with a simple circuit.

Embodiments of the present invention will be described with reference to the drawings. 1st
In the figure, 1 is an electric motor, and 2 is a phase detector, which is coupled to the electric motor 1 and detects its rotational phase. 3
is a waveform shaping circuit that shapes the waveform of the output of the phase detector 2, and outputs a digital signal consisting of one or more pulses for one revolution of the motor 1. A reference oscillator 4 outputs a digital signal having twice the frequency of the signal generated by the phase detector 2 when the motor 1 is at a synchronous rotational speed. 5 is a D-type flip-flop, the output of the waveform shaping circuit 3 is input to its data input terminal D, and the clock input terminal CP
The output of the reference oscillator 4 is input to . Reference numeral 6 denotes a matching circuit which receives the output signal from the output terminal Q of the D-type flip-flop 5 and the phase signal from the waveform shaping circuit 3. The output of the matching circuit 6 is amplified by an amplifier 7 and controls the speed control circuit 8 of the motor 1. 9 is a power source.

4a to 4h show time charts for explaining the operation of FIG. 1. In the same figure, a is the reference oscillator 4.
The output signal b is a reference signal with a period twice that of a. c is an output signal of the waveform shaping circuit 3, and the figure shows a case where the period is slightly longer than the reference signal b, that is, a case where the rotational speed of the electric motor is slower than the reference rotational speed.

First, in FIG. 1, the D-type flip-flop 5
A conventional example in which there is no matching circuit 6, that is, only the matching circuit 6 is used as a phase comparator, will be described. Fourth
FIG. d shows an output signal of a matching circuit (the polarity is reversed in the figure as a mismatching circuit) which receives the reference signal b and the output signal c of the waveform shaping circuit as inputs. As is clear from the figure, when the input signals do not match, “H”
It becomes a level signal. As the phase lags, the average output voltage value increases as shown in g in the figure. At time _t1 , after the phase of the output c of the waveform shaping circuit lags the reference signal b by one cycle or more,
The output of the mismatch circuit decreases, and then increases after time _t2 , which is delayed by one period or more, and this process is repeated.

Next, in FIG. 1, the D-type flip-flop 5
The case of the device of the present invention in which the following is connected will be explained. FIG. 4a shows a reference signal having twice the frequency of the reference signal b, and this reference signal a becomes the clock pulse input to the D-type flip-flop 5. on the other hand,
The output signal c of the waveform shaping circuit 3 becomes the D input of the D-type flip-flop 5. A D-type flip-flop latches the D input signal on the rising edge of the clock pulse. Therefore, the output signal is synchronized with the signal a, as shown in e, and operates at a period of 1/2 minute. At time _t1 , if the output c of the waveform shaping circuit lags the reference signal b by one cycle or more,
The output of the D-type flip-flop 5 does not change, and thereafter operates with a phase shift of one cycle. This output signal e and the output signal c of the waveform shaping circuit are phase-compared in a matching circuit 6, and the output is as shown in f. The average voltage of signal f is shown in h,
It increases as the phase lags behind the reference signal, and increases again from 0 when it lags by one cycle or more. From the above explanation, the phase comparison characteristics of the conventional device are shown in FIG. 2A, and the phase comparison characteristics of the device of the present invention are shown in FIG. 2B.

FIG. 2 shows the average value of the output signal of the matching circuit 6 when the motor 1 is rotating at a speed slightly slower than the synchronous rotation speed, and A shows the average value of the output signal of the matching circuit 6 without the D-type flip-flop 5 of the present invention. B is for the conventional device, and B is for the device of the present invention. Generally, when a PLL control circuit performs synchronous pull-in of a motor, the final stable state is stabilized at a certain phase difference with respect to the reference frequency. When the phase is about to lag, the condition for stability is that the voltage applied to the motor increases. Therefore, in the phase comparison characteristic shown in FIG. 2A, a stable point exists only once every two periods. As shown by A,
In a conventional circuit configuration including only the matching circuit 6, there are cases in which the output of the matching circuit 6 increases and cases in which it decreases over time, and it is clear that when it decreases, the control system becomes unstable. . On the other hand, the output of the matching circuit 6 of the present invention increases with the passage of time as shown in B, is reset when a phase difference of one period occurs, and increases again from the reset state, so the control system is stable. do. That is, since the D-type flip-flop 5 of the present invention latches and outputs the data input at that time every time the clock input rises, the period of the output of the reference oscillator 4 and the half period of the output of the phase detector 2 are equal in time. When, that is, when the electric motor 1 is rotating at a synchronous speed,
It is clear that the D-type flip-flop 5 acts as a 1/2 period divider. If this cycle is different, the rising edge of the output of the reference oscillator 4 will cause D depending on the data input, that is, the polarity of the output of the phase detector 2.
A case arises in which the Q output of the type flip-flop 5 does not change. At this time, the frequency dividing function is temporarily not performed, and the output signal of the reference oscillator 4 is skipped. As a result of this skip operation, the output signal of the matching circuit 6 is reset as shown in FIG. 2B, and increases again from the reset state, thereby eliminating the unstable effect on the control system. That is, even if synchronization once fails or steps out, there is a stable point in the next cycle, so there is an advantage that resynchronization can be easily performed.

FIG. 3 shows another embodiment of the present invention in which a speed feedback signal is added using a mono-multivibrator in order to further improve the stability of the control system. 10 is the matching circuit 6
A mono multivibrator (MM) that operates on the falling edge of the output signal of
is added to the output of the matching circuit 6 by. Since the fall of the output signal of the matching circuit 6 occurs at the rise and fall of the phase signal, the mono multivibrator 10 operates in response to the rise and fall of the phase signal. Therefore, the frequency of the output signal of the mono-multivibrator 10 is twice the frequency of the phase signal, which facilitates smoothing and further stabilizes the control system. Note that in a conventional circuit including only a matching circuit, the fall of the output signal of the matching circuit 6 does not necessarily occur at the rising and falling edges of the phase signal, but may also occur at the rising and falling edges of the reference oscillator 4. Therefore, the speed feedback signal shown in FIG. 3 cannot be used.

As described above, the present invention uses a phase signal obtained by shaping the output of the phase detector 2 coupled to the motor 1 by the waveform shaping circuit 3 as data input, and when the motor is at a synchronous rotational speed, the phase detector 2 A matching circuit 6 which has a D-type flip-flop whose clock input is the output signal of the reference oscillator 4 which generates a signal having twice the period of the generated signal, and which inputs the output of the D-type flip-flop and the phase signal. The motor speed control circuit 8 is configured to be controlled by a signal whose output is amplified, and the matching circuit 6 is controlled by skipping the frequency division of the output signal of the reference oscillator 4 according to the state of the phase signal. It is characterized by resetting the output of. Therefore, the output of the matching circuit 6, that is, the control signal increases again from the reset state as shown in FIG. 2B, so that the PLL control system can be operated stably. If necessary, a matching circuit 6 may be added as shown in the embodiment of FIG.
By adding a speed feedback signal using the mono-multivibrator 10 operated by the output of the control system, the stability of the control system can be further improved.

[Brief explanation of the drawing]

FIG. 1: A block diagram showing the configuration of an embodiment of the present invention, FIG. 2: A diagram showing the control signal A of the conventional device and the control signal B of the device of the present invention, FIG. FIG. 4 is a block diagram showing the configuration of the embodiment; a time chart for explaining the operation of FIG. 1; DESCRIPTION OF SYMBOLS 1... Electric motor, 2... Phase detector, 3... Waveform shaping circuit, 4... Reference oscillator, 5... D-type flip-flop, 6... Matching circuit, 7... Amplifier, 8... Speed control circuit, 9... Power supply, 10... mono multivibrator,
11...Adder.

Claims (1)

[Claims] 1. Data is a phase signal that is a rectangular wave signal that repeats an H level and an L level every half cycle, which is a signal obtained by shaping the output of a phase detector coupled to a motor with a waveform shaping circuit. a D-type flip-flop whose clock input is the output signal of a reference oscillator that generates a signal having twice the frequency of the signal generated by the phase detector when the motor is at a synchronous rotational speed; A speed control device for an electric motor, characterized in that a speed control circuit is controlled by a signal obtained by amplifying the output of a flip-flop and the output of a matching circuit inputting the phase signal. 2. A mono multivibrator operated by the output of the matching circuit and an adder for adding the output of the mono multivibrator and the output of the matching circuit are provided, and the output of the adder is added by an amplified signal. 2. A speed control device for an electric motor according to claim 1, wherein said speed control device controls a speed control circuit.